JPS5813041A - Decoder - Google Patents

Abstract

PURPOSE:To reduce the generation of passing-each-other noises generated when a read out clock signal overlaps with an internal clock signal, by preventing integral multiple relation between the frequency of the internal clock signal and that of the readout clock signal. CONSTITUTION:An input PCM signal 1 while synchronizing with a read clock signal 2 is inputted to a decoder for digital-analog conversion. Its output is supplied to a switched capacitor filter 4 to remove higher harmonic components, obtaining an output analog signal 5. The decoder 3 and switched capacitor filter 4 are controlled by timing control signals 7 and 8 from a control circuit 6. At this time, the frequency division ratio of the frequency divider in a PLL circuit 20 is selected properly so as to constitute the frequency of an internal clock signal 8 is not a multiple of the frequency of a readout clock signal 2.

Description

[Detailed Description of the Invention] This invention provides a decoder and/or encoder (hereinafter referred to as a codec) having a filter having a sampling function.
This is related to S/N improvement.

FIG. 1 is a block diagram showing the basic configuration of the codec. In FIG. 1, when the input PCM signal 1 is input to the decoder 3 in synchronization with the readout signal 2, the decoder 3 performs sidizotal-to-analog conversion, and this output is applied to the filter 4. For this, a switched filter or a sita filter (hereinafter referred to as SCF) having a sample function is used. An output analog signal 5 from which high frequency components have been removed by the filter 4 is obtained. In this case, the deodor 3 and the filter 4 are controlled by the timing control signal 7.8 from the control section 6. The internal ripple signal 9 supplied to the control section 6 is obtained by adding the synchronized ripple signal 10 to the PI, L circuit 20.

Analog-to-digital conversion to obtain the output PCM signal 11 from the input analog signal 5' can be performed by the reverse operation of the above case. That is, the input analog signal 5' is input to the encoder 12 through the filter 4'. . Output PC from encoder 12 in synchronization with read clock signal 2
An M signal 11 is obtained.

In this case as well, the control section 6 controls the encoder 12 and the filter 4' using the timing control signals 13 and 14, as in the case of digital-to-analog conversion. FIG. 2 shows the configuration of the PLL circuit 20 used in FIG. 1. The phase comparator 21 uses the frequency of the synchronized clock signals 1 and 0 and the frequency divider 22
The output frequency 23 of the voltage controlled oscillator 24 (V
CO).

The frequency of the internal clock signal 9, which is the output of the VCO, is determined by the division ratio of the divider 22. If the division ratio is n, the frequency of the internal clock signal 9 is the synchronous clock signal 10.
It is n times the 0 frequency.

Conventionally, in audio processing codecs, the frequency division ratio of the PLL circuit 20 is set to 8 or 16 for the frequency of 1 synchronous clock signal 10 of 8 kHz, and the frequency of the internal clock signal 9 is set to 128 kHz or 256 kHz. The frequency of signal 2 is 1,544k
Hz or 2.048 kHz is used in many cases. In such a configuration, if S, C, F, etc. having a sampling function are used as filters, the filters 4, 4 are transmitted from the control unit 6. ' control signal supplied to 8.
14 sampling pulse and readout signal 2)L? This method has a disadvantage in that the S/N ratio deteriorates when the signals overlap each other. That is, the PLL circuit 20
In many cases, the internal clock signal 9 obtained through This is because passing noise is generated in the part that overlaps with the pulse of signal 2.
If the frequency division ratio of the circuit 20 is set to 16, if the read clock signal 2 is 1.544 kHz, the internal clock signal 9 will be 256 kHz, so since the two signals are not in a multiple relationship, the two signals will overlap. It is not necessary to take into account the deterioration of S/N due to difference noise, but if the readout black signal 2 is 2.048 kHz, the internal black signal 9 is 256 kHz. Since they are in a multiple relationship, both signals always overlap, resulting in a significant deterioration of the S/N ratio. It is undesirable that the S/N characteristic deteriorates depending on the Fujinami number relationship between the internal black signal and the read (7 output black signal).

In order to eliminate this drawback, the present invention selects the internal clock frequency so that the frequencies of the internal clock signal and the read clock signal do not have a multiple relationship. If the frequency of the synchronized clock signal 10 is 9 kHz in Figure 1 and the readout clock frequency is 2.048 kHz, P in Figure 2
If the frequency division ratio of the frequency divider 22 of the LL circuit 20 is selected to be 17, the frequency of the internal clock signal 9 will be 136. It becomes kHz. In this way, since the two signals are not in a multiple relationship, the number of overlapping signals is greatly reduced, and the S/N deterioration due to cross-talk noise is also reduced to a small extent. Generally, in audio processing codecs, the frequency of the synchronous clock signal 10 is selected to be 8 kHz, so simply selecting the division ratio of the frequency divider 22 in the PLL circuit 20 according to the frequency of the readout clock signal 2 will It is possible to obtain an internal clock signal 9 that reduces generation of cross noise.

In the above explanation, we have discussed the case where there are two types of clock signals, an internal clock signal and a read clock signal, and a single codec is used to obtain a frequency relationship between the clock signals that does not degrade the S/N. Even in the case of having clock signals of This invention has the excellent effect of significantly reducing SA deterioration in analog-to-digital or digital-to-analog conversion simply by changing the division ratio of the divider in the PLL circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the codec, and FIG. 2 is a diagram showing the internal configuration of the PLL circuit shown in FIG. 1. 1... Input PCM signal, 2... Read clock signal, 3... Decoder, 4.4'... Filter, 5...
・Output analog signal, 5'...Input analog signal, 6
...Control unit, 7.8, 13.14...Control signal, 9
... Internal clock signal, 10 ... Synchronous clock signal, 11 ... Output PCM signal, 12 ... Encoder 1
22... Branch unit. Procedural amendment (1 illusion, f, L6, 10, 22゜ Commissioner of the Japan Patent Office 1, Display of the case 1982 Patent Application No. 110740 2, Invention title decoder 3, Person making the amendment case) Relationship with Patent Application Personnel Office (
Address: 165) 1-7-12 Toranomon, Minato-ku, Tokyo Name (029)! Representative of Chuo Electric Works S Co., Ltd.
Director and President Masao Miyake 4, Agent
(1 other person) Address: No. 12, No. 12, 1-7, Toranomon, Minato-ku, Tokyo 105, Subject of amendment 6, Contents of amendment 1) "Output frequency 23" on page 3, line 6 of the specification. Correct it to "the frequency of output frequency 23". 2) In line 14 of the same page of the same book, replace “8 or 16” with “1”.
6 or 32”. 3) On page 4, lines 10 to 12 of the same book, the phrase ``Reading...'' is replaced with ``The internal clock signal 9 is 128 kHz, so if the read clock signal 2 is 1,544 kHz, ” he corrected. 4) On the 16th line of the same page in the same book, replace r256kHzJ with r.
Corrected to 128kHzJ. 5) On page 6, line 6 of the same book, the word "digital" is corrected to "digital".

Claims (1)

[Claims] The input binary digital signal, the readout black signal, and the input binary digital signal are digital-to-analog converted in synchronization with the readout black and white signal. a clock signal, a PLL circuit that creates an internal clock signal from the synchronous clock signal, and a frequency division ratio in the PLL circuit that does not cause the frequency of the read clock signal to be a multiple of the internal clock signal frequency. a frequency divider for controlling the timing of the decoder and the filter in response to the internal clock signal to obtain an output analog signal from the filter.