JPS58138043A - Ic bonding method - Google Patents

Ic bonding method

Info

Publication number
JPS58138043A
JPS58138043A JP57020772A JP2077282A JPS58138043A JP S58138043 A JPS58138043 A JP S58138043A JP 57020772 A JP57020772 A JP 57020772A JP 2077282 A JP2077282 A JP 2077282A JP S58138043 A JPS58138043 A JP S58138043A
Authority
JP
Japan
Prior art keywords
finger lead
bonding
finger
small hole
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57020772A
Other languages
Japanese (ja)
Inventor
Isao Komine
小峰　勲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Original Assignee
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to JP57020772A priority Critical patent/JPS58138043A/en
Publication of JPS58138043A publication Critical patent/JPS58138043A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/077—Connecting of TAB connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable the thin type formation of a mount structure at low cost by a method wherein a small through-hole is provided at the top end of a finger lead, and an Au ball formed at the top end of an extremely fine metallic wire is thermal compression bonded on the IC electrode via small hole of the finger lead. CONSTITUTION:In the plane drawing and the sectional drawing of the main part of a circuit substrate, the numeral 1 repersents an insulation substrate constituted of resin of polyimide, etc., and 2 the finger lead constituted of Cu foil formed on the insulation substrate 1. The finger lead 2 projects to the inner side of the device hole b for bonding formed on the insulation substrate 1. The small hole a is provided at the top end of the finger lead 2 at the position corresponded to the position of the IC electrode. The small hole a is necessary for a bonding which is performed. Besides, Au plating, etc. is performed to the finger lead 2 to keep conductivity and corrosion resistance.

Description

【発明の詳細な説明】 本発明はＩＣのボンディング方法忙関する。回路基板Ｋ
ＩＣをボンディングする方法は、一般に回路基板の接続
端子とＩＣの電極とを、各１対ずつ金又はアルミニウム
等の極細線で結線してい（ワイヤーボンディング方式が
最も多（採用されていた。このワイヤーボンディング方
式は、ワイヤーを１ピンずつ張るため、多（の工数を要
し、たとえ全自動の装置を用いたとしても、装置１台当
りの能力は限られているという欠点が有った。又ワイヤ
ーを張る事によりワイヤーループが、回路基板とｔＣの
各々の表面から盛り上って形成されるために、実装構造
を必要以上に厚（してしまうという欠点も有った。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for bonding ICs. circuit board K
The method of bonding ICs is generally to connect the connection terminals of the circuit board and the electrodes of the IC with a pair of ultra-fine wires such as gold or aluminum (wire bonding method is the most commonly used method). The bonding method requires a large number of man-hours because the wires are stretched one pin at a time, and even if fully automatic equipment is used, there is a drawback that the capacity of each equipment is limited. By stretching the wire, wire loops are formed rising from the surfaces of the circuit board and tC, so there is also the drawback that the mounting structure becomes thicker than necessary.

このワイヤーボンディング方式の欠点を解消させる方法
として、ワイヤレス方式と呼ばれるフリップチップ方式
やミニモ・ラド方式が採用されている。このワイヤレス
方式はｌピンずつワイヤーを張る事なく各電極を同時に
接続するため、ボンディング工程の工数を削減する事が
出来、かつ実装構造の薄型化という目的、は違せられた
。しかし、ＩＣの各電極に半田又は金の突起電極を形成
する必要が有り、そのために多（の処理工程を要し、コ
ストの低減に関しては大きな障壁となる欠点が有った。As a method to overcome the drawbacks of this wire bonding method, a flip-chip method called a wireless method and a MiniMo-RAD method have been adopted. Since this wireless method connects each electrode at the same time without having to stretch wires for each pin, it is possible to reduce the number of steps in the bonding process, and the goal of making the mounting structure thinner is different. However, it is necessary to form protruding electrodes of solder or gold on each electrode of the IC, which requires a large number of processing steps, which has the disadvantage of being a major barrier to cost reduction.

本発明の目的は、上記欠点を解消し低コストでかつ実装
構造の薄型化が可能なボンディング方式な提供する事に
あり、その要旨は、絶縁基板に形成したフィンガーリー
ドと、ＩＣの電極とを接続するボンディング方法忙おい
て、前記フィンガーリードの先端に貫通する小孔を設け
、極細金線の先端に形成した金ボールを、前記フィンガ
ーリードの小孔を介して、前記ＩＣの電極に熱圧着させ
る事を特徴とする。An object of the present invention is to provide a bonding method that eliminates the above-mentioned drawbacks and allows for a low-cost and thin mounting structure. In the bonding method for connection, a small penetrating hole is provided at the tip of the finger lead, and a gold ball formed at the tip of the ultra-fine gold wire is thermocompression bonded to the electrode of the IC through the small hole of the finger lead. It is characterized by causing

以下図に従り【本発明の詳細な説明する。The present invention will be described in detail below according to the drawings.

第１図（Ａ）、（Ｂ）は本発明の実施例における回路基
板の要部平面図とその断面図である。１はポリイミド等
の樹脂で成る絶縁基板であり、２は絶縁基板１に形成さ
れた銅箔で成るフィンガーリードである。該フィンガー
リード２は、絶縁基板１に形成されたボンディング用の
デバイス孔すの内側に突出している。前記フィンガーリ
ード２の先端には、後述するＩＣの電極位置に対応する
位置に、小孔ａが設け【ある。該小孔ａは後述するボン
ディングのために必要なものである。FIGS. 1A and 1B are a plan view and a cross-sectional view of a main part of a circuit board according to an embodiment of the present invention. 1 is an insulating substrate made of resin such as polyimide; 2 is a finger lead made of copper foil formed on the insulating substrate 1; The finger leads 2 protrude inside a device hole for bonding formed in the insulating substrate 1. A small hole a is provided at the tip of the finger lead 2 at a position corresponding to the electrode position of the IC, which will be described later. The small hole a is necessary for bonding, which will be described later.

又、前記フィンガーリード２には、導電性及び耐腐蝕性
を保たせるために、金メッキ等を施してお（。Furthermore, the finger leads 2 are plated with gold or the like in order to maintain conductivity and corrosion resistance.

第２図は、本発明の他の実施例におけるフィンガーリー
ドの要部拡大図を示し、フィンガーリード２の巾寸法は
、先端部の外径寸法より小さく選定しである。こうする
事により後述するボンディング時において、熱の放散を
少なくする事が出来る。FIG. 2 shows an enlarged view of the main part of a finger lead in another embodiment of the present invention, and the width of the finger lead 2 is selected to be smaller than the outer diameter of the tip. By doing so, it is possible to reduce heat dissipation during bonding, which will be described later.

第３図は本発明のさらに他の実施例におけるフィンガー
リードの要部拡大図を示し、フィンガーリード２の先端
忙設けられた小孔ａの近傍にくびれ部Ｃを形成してお（
。誼くびれ部Ｃを設ける事により、第２図における実施
例と同じ（、ボンディング時における熱の放散を少な（
する事が出来る。FIG. 3 shows an enlarged view of the main part of a finger reed in still another embodiment of the present invention, in which a constricted portion C is formed near a small hole a formed in the tip of the finger reed 2.
. By providing the constricted portion C, the heat dissipation during bonding can be reduced (the same as the embodiment shown in Fig. 2).
I can do it.

第４図（Ａ）〜（Ｄ）は、本発明によるＩＣのボンディ
ング方法を、動作順に示した。要部断面図であり、図中
第１図と同一番号は、同一部材又は同一箇所を示す。FIGS. 4(A) to 4(D) show the IC bonding method according to the present invention in the order of operation. It is a sectional view of a main part, and the same numbers as in FIG. 1 indicate the same members or the same locations.

第４図（Ａ）は、回路基板１のフィンガーリード２とＩ
Ｃ３の電極ｄとを正しく位置合せした状態を示すボンデ
ィング部の要部断面図である。フィンガーリード２の先
端に設けられた小孔ａは、ボンディングが完了した時、
対応する前記電極ｄと一致する位置に設けておく。FIG. 4(A) shows the finger leads 2 and I of the circuit board 1.
FIG. 7 is a cross-sectional view of a main part of the bonding part showing a state in which the electrode d of C3 is correctly aligned. The small hole a provided at the tip of the finger lead 2 is formed when bonding is completed.
It is provided at a position that coincides with the corresponding electrode d.

又、前記小孔ａの寸法は、後述する押潰した金ポールの
外径寸法に対し、２／３程度の寸法にしておく事により
充分なボンディング強度が得られる。Further, sufficient bonding strength can be obtained by setting the size of the small hole a to be about 2/3 of the outer diameter of the crushed gold pole described later.

第４図（Ｂ）は、ボンディング位置に、ポンディフグツ
ールであるキャピラＩＪ　−６を位置合せした状態を示
すボンディング部の要部断面図である。FIG. 4(B) is a cross-sectional view of the main part of the bonding part showing a state in which the capillar IJ-6, which is a Pondifugu tool, is aligned at the bonding position.

前記キャピラリー６は通常一般に使われているワイヤー
ボンディング用のキャピラリーを使用出来る。又、該キ
ャピラリーｅには２５μ〜３５μ程度の極細の金線ｆが
通されており、該金線ｆの先端には一般のワイヤーボン
ディングと同様に１球状のいわゆる金ポールｇが形成さ
れている。As the capillary 6, a commonly used capillary for wire bonding can be used. In addition, an extremely thin gold wire f of about 25 μm to 35 μm is passed through the capillary e, and a so-called gold pole g having a spherical shape is formed at the tip of the gold wire f, as in general wire bonding. .

第４図（Ｃ）は、キャピラリーｅが降下し、さらに一定
圧力で金ボールｇをフィンガーリード２の小孔ａを介し
て押潰した状態を示すボンディング部の要部断面図であ
る。ＩＣ３はＩＣ保持板４で保持されており、さらに該
保持板４には３００℃〜３５０℃程度の熱を加えておく
。このキャピラリーｅの圧力と保持板４からの加熱とに
より、金ボールｇは押潰されると同時にＩＣ３の電極ｄ
と熱圧着される。又、金ボールｇが押潰される事により
、前記フィンガーリード２は、ＩＣ６の電極ｄに金ボー
ルｇでリベツティングされる結果になる。FIG. 4(C) is a sectional view of a main part of the bonding part showing a state in which the capillary e descends and further crushes the gold ball g through the small hole a of the finger lead 2 with a constant pressure. The IC 3 is held by an IC holding plate 4, and heat of about 300°C to 350°C is applied to the holding plate 4. Due to the pressure of the capillary e and the heating from the holding plate 4, the gold ball g is crushed and at the same time the electrode d of the IC3
and heat-compression bonded. Further, by crushing the gold ball g, the finger lead 2 is riveted to the electrode d of the IC 6 by the gold ball g.

第４図（Ｄ）は、金線ｆを金ポールｇから切り離した状
態のボンディング部の要部断面図である。FIG. 4(D) is a cross-sectional view of the main part of the bonding part with the gold wire f separated from the gold pole g.

金線ｆを金ボールｇから切り離す際は、図示していない
がキャピラリーｅの上部にある金線クランパーで金線ｆ
を保持して引き上げ、次にキャビラＩＪ−ｅが上昇する
。これは通常一般のワイヤーボンディングにおける七カ
ントボンドの際の動作と同じであり、従来のワイヤーボ
ンダーをわずかに動作変更するのみで容易に可能である
。又、金線ｆは金ボールｇの付根部分が最も弱いため、
確実に付根部分で切れる。When separating the gold wire f from the gold ball g, use a gold wire clamper (not shown) at the top of the capillary e to separate the gold wire f from the gold ball g.
, and then the cab IJ-e rises. This is the same operation as in seven-cant bonding in general wire bonding, and can be easily achieved by only slightly modifying the operation of a conventional wire bonder. Also, since the gold wire f is weakest at the base of the gold ball g,
You can definitely cut it at the base.

この後、切り離された金線ｆの先端を水素トーチ等で溶
かして再び金ボールｇを形成し、次のボンディング位置
へ移動する。Thereafter, the tip of the separated gold wire f is melted with a hydrogen torch or the like to form a gold ball g again, and the gold ball g is moved to the next bonding position.

上記第４図の（Ｂ）〜（Ｄ）Ｋおける動作を繰り返して
、全てのフィンガーリードと電極とをボンディングして
いく。The operations in (B) to (D)K in FIG. 4 above are repeated to bond all the finger leads and electrodes.

以上に述べたごとく、本発明によるポンディング方法を
採用する事により、従来のワイヤーボンディング方式に
比べ、ワイヤーループを張る必要が無いために実装構造
の薄型化が実現出き、かつボンディング速度は１／２〜
１／３に短縮する事が、従来のワイヤーボンダーを一部
改造するのみで実現出来る。さらに、一般のワイヤレス
方式に比べても、突起電極を設けておく事は、不要であ
るため、大巾なコストダウンが可能となった。この様に
本発明によれば薄型実装構造を低コストで提供する事が
出来、その効果は太きい。As described above, by adopting the bonding method according to the present invention, compared to the conventional wire bonding method, it is possible to realize a thinner mounting structure because there is no need to stretch wire loops, and the bonding speed is 1. /2~
Reducing the time to 1/3 can be achieved by only partially modifying the conventional wire bonder. Furthermore, compared to general wireless systems, there is no need to provide protruding electrodes, making it possible to significantly reduce costs. As described above, according to the present invention, a thin mounting structure can be provided at low cost, and its effects are significant.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（Ａ）、（Ｂ）は本発明の実施例における回路基
板の要部平面図とその断面図、第２図及び第３図は夫々
本発明の他の実施例におけるフィンガーリードの要部拡
大図、第４図（Ａ）〜（Ｄ）ｋ示した要部断面図。 １・・・・・・絶縁基板、 ２・・・・・・フィンガーリード、 ３・・・・・・ＩＣ１ ａ・・・・・・小孔、 ｄ・・・・・・電極、 ｇ・・・・・・金ボール。 第ｉｍｌ 第２ｒｌ！Ｊ 第３図 第４図1(A) and (B) are a plan view and a sectional view of the main parts of a circuit board in an embodiment of the present invention, and FIGS. 2 and 3 are essential parts of finger leads in other embodiments of the present invention, respectively. An enlarged view of a portion, and a sectional view of a main part shown in FIGS. 4(A) to (D)k. 1... Insulating substrate, 2... Finger lead, 3... IC1 a... Small hole, d... Electrode, g... ...Gold ball. 2nd iml 2nd rl! J Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板に形成したフィンガーリードと、ＩＣの電極と
を接続するボンディング方法において、前記フィンガー
リードの先端に貫通する小孔を設け、極細金線の先端に
形成した金ポールを、前記フィンガーリードの小孔を介
して、前記ＩＣの電極に熱圧着される事を特徴とするＩ
Ｃのボンディング方法。In a bonding method for connecting finger leads formed on an insulating substrate and electrodes of an IC, a small hole is provided at the tip of the finger lead, and a gold pole formed at the tip of an ultra-fine gold wire is inserted into the small hole of the finger lead. I characterized in that it is thermocompression bonded to the electrode of the IC through the hole.
C bonding method.
JP57020772A 1982-02-12 1982-02-12 Ic bonding method Pending JPS58138043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57020772A JPS58138043A (en) 1982-02-12 1982-02-12 Ic bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57020772A JPS58138043A (en) 1982-02-12 1982-02-12 Ic bonding method

Publications (1)

Publication Number Publication Date
JPS58138043A true JPS58138043A (en) 1983-08-16

Family

ID=12036449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57020772A Pending JPS58138043A (en) 1982-02-12 1982-02-12 Ic bonding method

Country Status (1)

Country Link
JP (1) JPS58138043A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7167344B2 (en) 2001-01-11 2007-01-23 Alps Electric Co., Ltd. Magnetic head actuator having finely movable tracking device
US7221541B2 (en) 1992-11-27 2007-05-22 Fujitsu Limited Magnetic head supporting mechanism

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7221541B2 (en) 1992-11-27 2007-05-22 Fujitsu Limited Magnetic head supporting mechanism
US7167344B2 (en) 2001-01-11 2007-01-23 Alps Electric Co., Ltd. Magnetic head actuator having finely movable tracking device

Similar Documents

Publication Publication Date Title
JP3935370B2 (en) Bumped semiconductor element manufacturing method, semiconductor device and manufacturing method thereof, circuit board, and electronic device
US5594275A (en) J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5536973A (en) Semiconductor device including a semiconductor element mounted on a substrate using bump-shaped connecting electrodes
US6740541B2 (en) Unmolded package for a semiconductor device
US6878570B2 (en) Thin stacked package and manufacturing method thereof
US5942795A (en) Leaded substrate carrier for integrated circuit device and leaded substrate carrier device assembly
JP3584930B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
US6440835B1 (en) Method of connecting a conductive trace to a semiconductor chip
US7044357B2 (en) Bump formation method and wire bonding method
JP3573133B2 (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
JP2002043357A (en) Semiconductor device and manufacturing method thereof
JPH0595015A (en) Semiconductor device
US6350632B1 (en) Semiconductor chip assembly with ball bond connection joint
US5704593A (en) Film carrier tape for semiconductor package and semiconductor device employing the same
JPH11354572A (en) Semiconductor chip package and method of manufacturing the same
JPS58138043A (en) Ic bonding method
JPH09162230A (en) Electronic circuit device and method of manufacturing the same
KR20190057801A (en) Semiconductor devices having wire bonding structures and methods of fabricating the same
JP3322642B2 (en) Method for manufacturing semiconductor device
JP3855532B2 (en) Connection method between IC chip and circuit board
US20140120661A1 (en) Flip chip packaging method
KR100881024B1 (en) Chip scale package to improve high frequency characteristics and manufacturing method thereof
JP2003017624A (en) Semiconductor device
JPH09306953A (en) Bare chip mounted semiconductor device and manufacturing method thereof
JPH0574853A (en) Connection structure of semiconductor device