JPS58155457A - Information processing device - Google Patents

Abstract

PURPOSE:To shorten a processing time, and to execute optimum processing, by decoding each of at least two instructions whose work length is different from each other, and generating a control signal having the same function substantially. CONSTITUTION:A two word instruction for outputting a data to an output port 3 is decoded by an instruction decoder 8, and a decoding signal 11 is sent to a port controlling circuit 7. As a result, control signals 13, 14 are generated from the circuit 7. On the other hand, as for an one word instruction, an instruction decoder 9 is selected, this one word instruction is decoded by the decoder 9, and a signal 12 which is same as the signal 11 is generated. Accordingly, for instance, when an output instruction of one word is executed, the decoding signal 12 from the decoder 9 is sent to the circuit 7, and from the circuit 7, the control signals 13, 14 which make the output port 3 active are generated. In this way, when the decoder 9 is made active or non-active by a signal 10, it becomes possible to process two kinds of output instructions whose word length is different from each other, in an optimum time, and the processing is executed very efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that decodes instructions and processes information according to the results. The number of bits of an instruction for controlling an information processing device is generally fixed. For example, if each instruction is coded with 4 bits, 16 types of instructions can be set in the memory. However, in order to execute complex processing, the number of types of instructions must be increased.

Therefore, it is common practice to use a plurality of 4-bit codes to form one instruction. Examples include a 2m instruction and a 3-word instruction. As a result, it has become possible to increase the number of types of instructions with a limited number of bits, but the disadvantage is that the instruction execution time becomes longer. This is because, for example, to execute a two-word instruction, the memory must be accessed at least twice, which requires at least two machine cycles, and the processing time increases accordingly. However, in the past, efforts were made to improve processing capacity rather than processing time, so an increase in processing time was unavoidable.

Also, as an instruction to execute one process, simply 1
Only one type was available. This can be said to be an inevitable design matter from the viewpoint of effective utilization of the capacity.

On the other hand, if we analyze in detail the actual processing of such an information processing device, there are some operations that can be executed by using only part of the information contained in one instruction without using all of the information.

That is, there are some processes that can be executed with a one-word instruction without using a two-word instruction. An example is an output command. This instruction is an instruction that controls the process of outputting data from the boat (output section); the first instruction section is for controlling the boat to perform the output operation, and the first instruction section is for providing address information for selecting the boat. In some cases, the command is stored in memory as a 2-instruction from a 2-instruction section.

This command has a boat selection function, so it is an effective command that can arbitrarily control multiple peripheral devices depending on the processing, but if the boat to which data should be output has been specified in advance, it is not possible to select the boat. There is no need to do this; just controlling the boat's output is sufficient. That is, one machine cycle is sufficient. However, since the instruction itself is a two-word instruction, two machine cycles naturally had to be spent. This is because the hardware is designed so that output processing cannot be executed unless a two-word instruction is read.

Specifically, in a microcomputer that requires a two-word instruction to select a port and output data from it during normal operation, the port from which the operation test is output is determined in advance, but the two-word instruction is used. Therefore, it takes time to read the instructions, resulting in a longer test time, and requires more hardware (for example, memory capacity for storing test patterns) of the equipment for testing. is bad and disadvantageous.

An object of the present invention is to shorten processing time without reducing processing capacity and to provide an information processing apparatus that can be optimally applied to processing in each building.

The information processing apparatus of the present invention is characterized by having a control circuit that generates a control signal for decoding at least two types of instructions having different word lengths and executing substantially the same processing.

According to the present invention, for example, the tx
Since a control signal can be generated, by selecting one of them depending on the processing content, processing can be performed in an optimal time without reducing processing capacity.

For example, if there is a free code on the instruction code, you can use it and assign it as a one-word instruction to be used during testing. It can be used as a word output command, and test results can be output in one machine/cycle. On the other hand, for an output command consisting of a two-word command, boat selection and output control can be executed using at least two or more cycles per cycle, without reducing processing performance.

Incidentally, if there is no free code as described above, it is only necessary to switch and use a certain specific instruction that the system has as a one-word output instruction used at the time of testing.

Next, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, a data bus 1 is coupled to an output port 3 comprising an output latch 4 and a driver 5 and connected to an external terminal 2. The packing decoder unit 15 has a first instruction decoder 8 and a second instruction decoder 9, and each data signal 11 and 12 is a port for generating a signal for controlling the output operation of the output port 3. Control circuit 7 chivalry supply 3 arises. 13 is a latch control signal sent from the instruction decoder section 15 to the output latch 4 to capture data on the data bus 1, and 14 is a control signal sent from the instruction decoder section 15 to the driver 5 to activate it. be. Reference numeral 10 denotes a control signal 1 for driving the second instruction decoder, which is inputted from an external switch or generated internally depending on the processing content (for example, by determining the processing content).

The operation of this embodiment is as follows.

When outputting data from the output port 3, the boat control circuit 7 receives the decoder output and generates a signal 13 for activating the output port 4 and a signal 14 for activating the driver 5. . When these signals 13 and 14 are generated, the data on the data bus 1 is read into the output latch 4, this output 6 is input to the driver 5, and the data is output to the external terminal 2. Here, the 2 candy command for outputting data to the output boat 3 is decoded by the command decoder 8 and a decode signal is sent to the boat control circuit 7.

Send 11. As a result, control signals 13 and 14 are generated from the boat control circuit 7. On the other hand, for -word instructions, instruction decoder 9 is selected (in response to signal 10), the - instructions are decoded by instruction decoder 10, and signal 12 similar to signal 11 is generated. Therefore, for example, when a one-word output command is executed, the decode signal 12 from the instruction decoder 9 is sent to the control circuit 7, and the control circuit 7 sends the decode signal 12 to the boat 3.
A control signal 13.14 is generated which activates.

One machine cycle at most is sufficient for this, and is used, for example, when outputting test results, and the port 3 to be outputted has already been determined.

Furthermore, since the signal IO is not generated during times other than testing, the instruction decoder 9 becomes inactive, and an attempt to execute a one-word output instruction becomes invalid. However, at this time, the instruction decoder 8 is valid, and if a two-word output instruction requiring boat selection information is, for example, two or more machine sensors, the instruction decoder 9 is controlled to be active or inactive by the signal 10, so that the system It is possible to process at least two types of output commands with different word lengths in the optimum time without affecting the word length, which is extremely efficient.

In addition, if there is no free code to which such a -word instruction can be assigned, in FIG. A similar effect can be obtained by adding a control circuit that switches using the signal 10 to input the command decoder 9 to the instruction decoder 9.

The present invention aims to shorten processing time by decoding at least two types of commands with different word lengths to generate control signals with similar functions. , is effective for instructions other than the output instructions of the embodiment, and can be similarly applied to normal program processing other than test processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of a microcomputer according to an embodiment of the present invention. 1... Data bus, 2... External terminal,
3... Output boat, 4... Output latch, 5... Buffer, 7... Boat control circuit, 8... First Instruction decoder, 9...
...Second instruction decoder, 10...Control signal,
15...Instruction decoder section 5, #-1 diagram

Claims (1)

[Claims] An information processing apparatus comprising a control circuit that generates control signals having substantially the same function by decoding at least two instructions having different word lengths.