JPS58159083A - Sampling pulse generating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a sampling pulse generation circuit suitable for a circuit that generates sampling pulses for sampling a teletext multiplex signal in, for example, an apparatus for receiving teletext broadcasting. Regarding.

[Technical background of the invention]

In a text multiplex receiver, the sampling pulse for sampling the received text multiplex signal generally has a frequency 815 times the color subcarrier frequency wLfsc, and its phase is set at the leading edge of the text multiplex signal. The clock twin signal CR (frequency '415fxc) is synchronized with the clock twin signal CR (frequency '415fxc).

FIG. 1 is a circuit diagram showing a conventional circuit for generating the nine sampling pulses mentioned above. In FIG.
7A locked loop that outputs signal 81 of ig (
(hereinafter referred to as PLL). 12 is a 5-stage ring counter circuit constituted by JK flip-flop circuits 121-128. Among these, JK flip-flop circuits 121 to 125 form the main body of the ring kakunta, and JK
Flip-flop circuits 126 to 128 are used to supply signals to a phase correction circuit 14, which will be described later. Each JIm
The 1m flip-flop paths 121S-128 each have a phase of 35 using the PLLII output signal 81 as a clock signal.
@ Frequency 4/5 f s c ll with sm increments
Output No. 7i. 13 is a sampling pulse output circuit. This sampling pulse output circuit 13 is constituted by an exclusive-OR circuit 131, and uses the Q output signal of the JK7 lip-flop circuit 1211123 as an input signal and outputs a signal with a frequency of 8/5 fsc as a sampling pulse SP. As mentioned above, it is necessary to synchronize the phase with the clock line signal CR of the character multiplex signal. This operation is performed by the phase correction circuit 14. This phase correction circuit 14 is composed of a S/D circuit 1411142 and an AND circuit 143. Hereinafter, the operation of the phase correction circuit 14 will be explained with reference to the signal waveform diagrams of FIGS. 2 and 3. In the figure, 8 is the output signal of the JK flip-flop 1 flip @125 of the 5R ring counter 12. This No. 11 88 has a frequency of 41 as mentioned above.
The output signal S1 of RL and Lll is 1/1 with the 5fsc signal.
The frequency is divided into 10 and the result is worshiped. Then, the phase correction circuit 14 outputs the output signal Sm of the JK Fritzno flop circuit 125.
1 located before and after this No. 16 S2 based on
A leading edge pulse Pt and a trailing edge pulse P snow with a width of 7°5y1alIIC are generated. And this pulse ' 1 , P'' e
tel 1 Gating is performed using the clock run gate signal G and the four-way run-in signal CR shown in the figure. Although Nm of the clock run gate signal G will be described later, the clock run-in signal CR
It becomes 0 level at the 0 level position in the fifth period of , and is a pulse for extracting the clock line signal from the character multiplex signal. The pulse gated by the phase correction circuit 14 is JK
It is used as the set H1t of the flip-flop circuit 125. Standard No. 18 S now! If the phase of the clock twin signal CR is behind that of the clock twin signal CR, then the leading edge pulse P
! is gated, and the JK flip-flop circuit 125 is set to the leading edge pulse Pt. As a result, the phase of the reference signal 83 is advanced by one cycle of the output signal S1 of the PLL 11.

Conversely, the 8th phase of the reference signal is the clock run-in signal CR.
, the trailing edge pulse Ps is gated and the JK flip-flop circuit 125 is set to the set state by the trailing edge pulse Pg-. This causes the phase of the reference signal s2 to be delayed by 35 sam (36').

In this way, the reference signal SZ is 35SsI! cJ! ! The operation of the five-stage running counter circuit 12 can be synchronized with the clock fin signal CR by moving the clock fin signal CR. As a result, the sampling pulse J
The phase of iI' can be synchronized with the clock run-in signal CR. In addition, in such a phase correction operation, the phase difference between the reference signal BS and the clock run-in signal CR is determined by the reference signal 81 as shown in FIG. 0 delayed from run-in signal CR
It can be kept within the range of ~35s-. Furthermore, when the phase difference between the reference signal S2 and the clock run-in signal CR is the largest, even if the phase difference is 180" (1755ea), the clock line/in signal CR is
Phase correction can be done by photons for each period. Therefore, the click run gate signal G is clocked as described above.
It is set so that it becomes 0 level at the 0 level position of the fifth period of the in signal CRO.

[Problems with background technology]! -7 However, the above configuration has the following drawbacks. This will be explained below with reference to Figure 4. Fourth
The figure shows the reference signal B and this reference signal H! whose phase is delayed within the range of θ to 35% with respect to the clock line/in signal CR and which are synchronized in good condition. A sampling pulse 8F synchronized with is shown. Note that in the above configuration, the Young Ring pulse 8F has a phase difference of 35% with respect to the reference signal 88.

It is not delayed. Therefore, the phase of the reference signal 8m will change by 35 swwa when the phase of the black fin-in signal CM changes and a phase correction operation is applied. In other words,
It will have a jitter of 35%. As a result, the sampling pulse 8F also has a jitter of 35 m-minutes.

The jitter of the sampling pulse 8P has a large influence, such as causing errors in the data obtained by sampling, so it is better to keep it as small as possible. 1g1
To reduce the nine jitters described above in the configuration shown in the figure, use PLLI.
There is no other way than to increase the output II4 wave number of l. However, using too high a frequency is undesirable from the viewpoint of increasing circuit regulation and operational continuity.

[Purpose of the invention]

This invention was made to deal with the above-mentioned circumstances, and -
To provide a sampling pulse generation circuit capable of suppressing the jitter of a sampling pulse 8F to the intermediate level of the jitter in the configuration number of FIG. 1 by setting the output frequency of a PLLII to tt as shown in FIG. 1. With the goal.

[Key points of invention]

Therefore, if the present invention is explained using, for example, Figure 11g5, the PLL 21 is A second sampling pulse 8P2, which is synchronized with a phase difference of half the output period, is generated by the second 5-stage tsunta tsunta repair 24, second sampling pulse output circuit 26, etc., and the phase is shifted. When the correction circuit 28 completes the operation of synchronizing the operation of the 11M2 5-stage switching circuit 22.24 with the clock line/in signal CH, the discrimination circuit 29 discriminates the phase difference, and the sampling is performed based on the discrimination result. The phase difference is changed to PL by the pulse switching circuit 27.
When it is in the half period direction of the output period of L21, the second sampling pulse BP is selected, and when it is within the range from half period to one period, the first sampling pulse 8P1 is selected.
It is constructed so as to obtain the following, and the phase difference is reduced.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described as an example with reference to the drawings. FIG. 5 is a block diagram showing a circuit of one embodiment. FIG. 6 is a circuit diagram showing an example of a specific circuit configuration of the cocoon 5 diagram. Here, in order to simplify the explanation, the structure and operation of FIG. 5 will be explained with reference to FIG. 6. In Fig. 6, 21 is a PLL, and the F as shown in Fig. 1 above.
Similarly to LI, 11, a signal 81 of frequency *(8flC) is generated. This signal 8! is the first 5-stage Zung counter @l
Supplied to @22. This 5R ring force counter circuit 22
is AND circuit 221, JK flip-flop circuit 222
It consists of ~227. And each JK flip frog @
@222 to 227 are the output signals 8 of the PLL 21! By obtaining the clock signal through the AND circuit 221, a signal with a frequency of 415 fsr is output. In addition, J
The K flip-flop circuit 227 is a 5-stage ring counter circuit 2 for a phase correction circuit 28 and a discrimination circuit 29, which will be described later.
This is provided to supply the second output signal.

Reference numeral 23 denotes a sampling pulse generation circuit of the morphism I, which is composed of an exclusive OR circuit 231. This sampling pulse generation circuit 23 is a JK flip-flop circuit 22.
A first sampling pulse 8Pl with a frequency of 8/5 fsc is derived by taking the F/F/F/2.224 q output signal.

24 is a second 5-stage ring counter circuit.

This second five-stage ring counter circuit 24 is composed of TK flip-flop circuits 241 to 245. As an input signal to Jl of the JK flip-flop circuit 24 in the first stage of this platform, Q1 of the Jl flip-flop circuit 222 in the first stage of the first five-stage ring counter circuit 22 is input.
In addition, each of the rK flip-flop circuits 241 to 245 uses the output signal s of the PLL 21.
i is inverted by the inverter circuit 25 and a good signal is sent to the crotter 1.
It has been obtained as a number. As a result, the output signal of each JK flip-flop circuit 241-245 is 17.
The phase of the fifth phase is delayed and becomes 9-I'f1.

Reference numeral 26 denotes a second sampling pulse output circuit, which is constituted by an exclusive or circuit d261. This FC-flush OR circuit 261 is able to control the FF-flush OR of the q output No. 1 of the JK7 lip 70 tube circuit 2411243.
) is derived. This 20th sampling pulse BP2 is the previous first sampling pulse 82! The phase is shifted by 17.5S-.

27 is the eleventh second sampling pulse output circuit 23.
11th g2 sampling pulse 8 output from 26
This is a sampling pulse switching circuit that switches 1Ps1 BPg. This sampling pulse switching circuit 27 consists of NAND circuits 271-273. Note that the switching operation of the sampling pulse switching circuit 27 is controlled by a discrimination circuit 29, which will be described later.

The phase correction circuit 28 is composed of NAND circuits 281, 282 and an AND circuit 283. This phase correction circuit 28
is the operation of the eleventh second five-stage ring counter circuit 22.24 using the output signal of the eleventh second five-stage ring counter circuit 22.24, the clock run-in signal CR, and the first clock run gate signal G1. is synchronized with the clock run-in signal CR, and performs the same operation as the 1 phase correction circuit 14 shown in FIG.

Discrimination circuit 29 is NAND circuit 291, 292, JK free□
It consists of a tube flop circuit 293. This discrimination episode w629
is the output signal of the 11th second 5-stage ring counter circuit 22, 24, the signal obtained by inverting the clock run-in 1fI No. C and R by the inverter circuit 30, and the second run cylinder run gate signal Gx. 11 Second 5-stage ring counter circuit 22. Is the lf1 operation of 24 synchronized with the clock run-in signal CR with a phase delay within the range of O to 17.5 smc? 17.5 ~35
Li! determines whether synchronization is achieved with a phase delay within m1 of the sample, and controls the switching operation of the sampling pulse switching circuit w & 21 based on the result of this determination. ! i
Small signal that guides the I control signal.

In the above configuration, the PLL 21 constitutes the oscillation means, the first five-stage ring counter @22 constitutes the frequency dividing means, and the first sampling pulse output circuit 23 constitutes the first sampling pulse output means. The second five-stage ring counter circuit 24, the inverter circuit 25, and the 20th numbering pulse output circuit 26 constitute a second sampling pulse output means, and the sampling pulse switching circuit w&27 constitutes a numbering pulse switching means. The phase correction circuit 28
A phase correction means is constituted by the phase correction means, and a discrimination means is constituted by the discrimination circuit 29 and the inverter circuit 30.

Here, the operation of the circuit shown in FIG. 5 and FIG.
This will be explained with reference to the No. 1 waveform diagrams shown in FIGS. The phase correction circuit 28 performs tongue-to-edge phase correction similarly to the phase correction circuit 14 shown in FIG. 1 above.

That is, as shown in FIG.
Pulses Pr1 Pg are created such that they are located at the leading and trailing edges of 1 and have g17.5%. Then, this leading edge pulse PIN*edge pulse P8 is gated to the clock run-in signal CR. In this case, if the leading edge pulse P1 is gated, the reference I11 signal is advanced in phase by 35 minutes.

If the trailing edge pulse P2 is gated instead, the reference signal 83 will be delayed in phase by 35%. By performing such phase correction, even if the phase difference between the clock run-in signal CR and the reference signal 8 is only 180' (175% formula), it will be corrected in the 5th cycle from the time when the clock run-in signal CR is generated. The phase correction operation can be completed. Then, the reference signal 8 and clock run in 1i! The phase difference between the reference signal 8 and the clock run-in signal CR can be kept within the range of θ to 35 when the reference signal 8 is delayed from the clock run-in signal CR. Therefore, the first clock run-in gate signal G1 is
Similar to clock run gate G shown in the figure, clock run in 114c! It is set to become O level at the 0 level position of the 5th cycle of 'l.

When the phase correction is completed, the phase difference between the clock run-in signal CR and the reference signal 82 is 0 to 17.5 in the discrimination cycle 1NI29.
It is determined whether it is in the range of gwe or in the range of 17.5 to 35 @wag. That is, the discrimination circuit 29
1. Using the output signals of the second five-stage ring counter circuit 22 and 24, two pulses Pg and F4 are generated at the leading edge of the reference signal 81 as shown in FIG. Each pulse PI, P4 has a width of 1
7.555W, and the phase difference between the two is 1
It is set to 7.5@m. NAND circuit 291.29
2 connects the clock run-in signal CR to the inverter Fgl 3
0, the inverted signal CR and the second clock run gate signal Gl generate a clock Ps.

Gate P4. In this case, the clock run gate No. 18 G2 of the entertainment 2 completes the phase correction operation, and at the pth floor where the phase relationship between the reference signal S2 and the clock run-in signal CR is determined, two Since Ps and Pi are used to check how they are gated by the inverted clock run-in signal CR&, the first clock run-in signal G1 is delayed by 350 minutes. It is set to be the level.

Such an operation of the discriminating circuit 290 is performed as follows in response to the phase relation between the reference signal day 2 and the clock run-in signal CR.
It is distinguished into This is the case when the phase difference between the 4i reference signal 83 and the clock run-in signal CR is between the state shown in FIG. 8a and the state shown in FIG. That is, the phase difference between the reference signal aS and the clock run-in signal Cft is 17
．． This is the case where it exists in the 5-35% range. In this case, it is input to the NAND circuit 291) (only the signal Pi is gated).

Another case is when the phase difference between the reference signal 8 and the clock run-in signal CR is between the state shown in the eighth row and the state shown in the same figure. That is, the reference signal IIs, clock line y*4+cR and 01[11 are O~17.5sm
This is the case where there is a In this case, the descendant Nando circuit 29
1.292 input pulse F8. Both P4 are obtained.

By the way, the pulse P3 output from the NAND Igll 1291 is used as set No. 1 of the JK flip-flop circuit 293, and the pulse A4 output from the NAND circuit 292 is used as a reset signal for the JK flip-flop circuit 293. Therefore, the output state of the J]C flip-flop circuit 2930 is also distinguished into the following two cases depending on the phase difference between the reference signal B3 and the clock run-in signal CR. That is, when the phase difference between the reference signal 8 and the clock run-in signal CR is within 17.5 to 35@as, the JK flip-flop 1g1fi293 is set as a foreshadowing by the pulse P1 output from the NAND circuit 291. , the Q output level is l. On the other hand, the phase difference between the reference signal and the clock run-in signal CR is O~
When kicking 17.5%, JK flip-flop times v11
293 is initially set by the pulse Ps output from the NAND circuit 291, but is immediately reset by the pulse P4 output from the NAND circuit 292.

Therefore, the q level becomes O.

The Q output lIt and Q output signals of the JK flip-flop circuit 293 operating in this manner are respectively sent to the NAND circuit 2 as control signals for the sampling pulse switching circuit 270.
71,272. And JK flip 70
Depending on the output state of the knob circuit 293, any one of the first sampling pulse, the second sampling pulse art, and the second sampling pulse 8Fg output from the eleventh and second exclusive OR circuits 231 and 261 is selected.

FIG. 9 is a signal waveform diagram for explaining the operation of the sampling pulse switching circuit 27. 11g shows the clock run-in signal CR. For the same S, the phase difference between the clock run-in signal CR and the reference No. 11t mg is 0 to 17.5 am.
1% second sampling pulse 111P*, 1. Indicates the phase of s. In the same figure, the 11th second Templing pulse EIPt is shown when the phase difference is within the range of 17.5% to 35% zero.

Shows Toro 0th place. FIG. 4 shows the sampling pulse 8F selected by the sampling pulse switching wAllI127. Note that the phase difference between the 11th and 2nd sampling pulses 8Fs and BPx is 17.555w+6 as mentioned above, but in the case of the 6th - configuration, the 1f)
Sampling pulse [h is the reference signal 8 as shown in 8-
! The phase is 3sssII! It's late, 17v,,
l@2(7)Funf17ngpulse HPl is 52.5 duck kicks behind.

Now, assuming that the phase difference between the clock run-in signal CR and the reference signal 8 is within the range of 0 to 17.5 seconds, JK7
Since the lip prop circuit 293 is in the reset state,
In the sampling pulse switching circuit 27, the second sampling pulse 8P! shown by the solid line in FIG. -, the JK flip-flop circuit 293 is set, so the sampling pulse switching circuit 27 selects the first sampling pulse BPK shown by the solid line in FIG. In either case of Figure 9b1-, the sampling pulse shown in figure d is output, and the jitter is within 17.5%.In other words, the phase of the clock run-in signal CR changes and the phase correction operation is performed. done,
Even if the reference signal jitters by 35%, the sampling pulse will jitter by only half that amount, 17.5%.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented in various other ways.

It goes without saying that the present invention can also be applied to circuits other than the sampling pulse generation circuit of the character multiplex receiver 111 device.

〔Effect of the invention〕

As described above, according to this invention, it is possible to provide a sampling pulse generation circuit that can output sampling pulses with less jitter.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional sampling pulse generation circuit in a text multiplex receiver, and Figs. 2 and 3 are signal waveforms for explaining the operation of the circuit shown in Fig. 1-1.
The figure also shows the signal **gl, 5th vA to explain the defect.
1 is a circuit diagram of an embodiment of the sampling pulse generation circuit according to the present invention, and FIG. 1 is a line diagram showing an example of a specific configuration of the circuit shown in ll5llll, FIG.
~(-) No. 9ig(・) to (d) are signal waveform diagrams for explaining the operation of the circuits shown in FIG. S and FIG. 6. 2 l ・++ '1? L L 22... -First 5-stage ring counter circuit 23...First sampling pulse output circuit 24...Second 5-stage ring counter circuit 25...Inverter circuit 26...Second sampling pulse output El&27.
... Sampling pulse switching circuit 28 ... Phase correction circuit 29 ... Discrimination circuit 30 ... Inverter circuit Applicant's agent Patent attorney Takehiko Suzue Figure 2 1! 3 Figure 4 Q p 511 21)

Claims (1)

[Claims] an oscillating means for outputting a signal having a frequency N (natural number) times the frequency of an input signal; a dividing means for frequency-dividing the output signal of the oscillating means to obtain a signal having the same frequency as the input signal; a first sampling pulse output means for outputting a first sampling pulse for sampling the writing input signal using the branch output signal of the means;
) second sampling pulse output means for outputting a second sampling pulse synchronized with the sampling pulse and whose phase is shifted from the second pulse by a half period of the output period of the oscillation means; By detecting the phase difference between the output signal and the input signal and setting the frequency division means to an initial state, the phase difference between the frequency division output signal and the input signal is reduced to within the output period of the division means. When the phase correction by this phase correction means is completed, the phase difference between the Dm1 frequency-divided output signal and the input signal is equal to half the output period of the oscillation means. Based on the discrimination results of the discriminating means for discriminating whether it is in the increment or within a1 from half a cycle to one cycle, and the discriminating means for Hi, @
By selecting one of the sampling pulses No. 2 as the Jll large input signal sampling pulse, a sampling pulse whose phase difference with the input signal falls within a half period of the output period of the Nishiki oscillation means is created as the cough sampling pulse. A sampling pulse L having a sampling pulse switching means capable of obtaining