JPS58166755A - 回路アセンブリ - Google Patents

回路アセンブリ

Info

Publication number
JPS58166755A
JPS58166755A JP57049121A JP4912182A JPS58166755A JP S58166755 A JPS58166755 A JP S58166755A JP 57049121 A JP57049121 A JP 57049121A JP 4912182 A JP4912182 A JP 4912182A JP S58166755 A JPS58166755 A JP S58166755A
Authority
JP
Japan
Prior art keywords
elements
chip
output pins
input
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57049121A
Other languages
English (en)
Japanese (ja)
Other versions
JPH046105B2 (2
Inventor
Bunichi Tagami
田上　文一
Fumiyuki Kobayashi
小林　二三幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57049121A priority Critical patent/JPS58166755A/ja
Publication of JPS58166755A publication Critical patent/JPS58166755A/ja
Publication of JPH046105B2 publication Critical patent/JPH046105B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
JP57049121A 1982-03-29 1982-03-29 回路アセンブリ Granted JPS58166755A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57049121A JPS58166755A (ja) 1982-03-29 1982-03-29 回路アセンブリ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57049121A JPS58166755A (ja) 1982-03-29 1982-03-29 回路アセンブリ

Publications (2)

Publication Number Publication Date
JPS58166755A true JPS58166755A (ja) 1983-10-01
JPH046105B2 JPH046105B2 (2) 1992-02-04

Family

ID=12822227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57049121A Granted JPS58166755A (ja) 1982-03-29 1982-03-29 回路アセンブリ

Country Status (1)

Country Link
JP (1) JPS58166755A (2)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477085A (en) * 1993-11-26 1995-12-19 Nec Corporation Bonding structure of dielectric substrates for impedance matching circuits on a packaging substrate involved in microwave integrated circuits
US5642262A (en) * 1995-02-23 1997-06-24 Altera Corporation High-density programmable logic device in a multi-chip module package with improved interconnect scheme
JP2006310411A (ja) * 2005-04-26 2006-11-09 Fujitsu Ltd 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52131955U (2) * 1976-04-01 1977-10-06
JPS5771352U (2) * 1980-10-20 1982-04-30
JPS5780836U (2) * 1980-10-31 1982-05-19
JPS5780837U (2) * 1980-10-31 1982-05-19
JPS5787544U (2) * 1980-11-17 1982-05-29
JPS5797961U (2) * 1980-12-08 1982-06-16

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52131955U (2) * 1976-04-01 1977-10-06
JPS5771352U (2) * 1980-10-20 1982-04-30
JPS5780836U (2) * 1980-10-31 1982-05-19
JPS5780837U (2) * 1980-10-31 1982-05-19
JPS5787544U (2) * 1980-11-17 1982-05-29
JPS5797961U (2) * 1980-12-08 1982-06-16

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477085A (en) * 1993-11-26 1995-12-19 Nec Corporation Bonding structure of dielectric substrates for impedance matching circuits on a packaging substrate involved in microwave integrated circuits
US5642262A (en) * 1995-02-23 1997-06-24 Altera Corporation High-density programmable logic device in a multi-chip module package with improved interconnect scheme
US6642064B1 (en) 1995-02-23 2003-11-04 Altera Corporation Method of making a high density programmable logic device in a multichip module package
JP2006310411A (ja) * 2005-04-26 2006-11-09 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
JPH046105B2 (2) 1992-02-04

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