JPS5817656A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an OMOS (comple-mentary semiconductor device) suitable for use in complementary insulated gate field effect semiconductor devices, such as inverters and NAND gate circuits.
The present invention relates to a method for manufacturing MOS.

To manufacture this type of 0MO8, it is generally necessary to define the P-type well 8i0. A mask is formed on the surface of the N-type silicon substrate by photoetching, and then the above-mentioned Sin,
Boron is introduced into a region where no mask exists to form a P-type well, and then selective oxidation is performed with a silicon nitride film deposited to define the active region. A field 810 for device isolation is selectively grown over the mold silicon. However, in this method, when processing the oxidation-resistant mask made of the silicon nitride film into a predetermined pattern by photoetching, the boundary area between the P-type well and the N-type silicon is At the top, it is necessary to provide a step corresponding to the shape of the above-mentioned Sin and mask to increase the pressure on the substrate. For example, when forming a P-type well, by using the step of the substrate that occurs in the boundary area between the 5tO1 film that grows on the well and the above-mentioned Sin mask, the surface oxidation after all the Sin on the substrate surface is removed by etching. In some cases, a step corresponding to the step of the substrate is provided on the StO film made to be longer than the other, and this step is used as an alignment guide.

Alternatively, after forming the P-type well, by performing surface oxidation while leaving the sio mask as it is, the 8i0. membrane and 8i0. It is also conceivable to provide a step in the boundary area with the mask.

However, even if the offset is made, a step is required to provide a step as a matching guide (i.e., the above-mentioned 8i0. etching and surface oxidation step, or surface oxidation step), which increases the number of man-hours and is disadvantageous in terms of workability. It turned out to be. Moreover, the 8i0. In other words, the step itself is 810. 8i on membrane and N-type silicon
0. Since it is based on the difference in film thickness between the film and the film, the amount of penetration of the bird's beak part of the field 810@ film that grows during the next selective oxidation into the area below the periphery of the oxidation-resistant mask is determined by the pH value.
The difference between the well and the N-type silicon is K. As the effective area of the active region becomes smaller on the side where the amount of one bite in this rounding is larger, it is necessary to make the oxidation-resistant mask pattern wider in advance in anticipation of the amount of bite, which limits the ability to increase the degree of integration. I also found out something.

Therefore, the object of the present invention is, in particular, to provide a P-channel and an N-channel I G FET (Insulated G FET).
ateField Effect Transisto
It is an object of the present invention to provide a method that facilitates workability and achieves high integration without using any of the above-mentioned steps when forming a mask pattern for determining the active region (r).

To achieve this objective, according to the present invention, after forming an oxidation-resistant mask that defines the active region, this oxidation-resistant mask is used as a alignment guide during well formation, and the introduction of impurities for the well is performed using an oxidation-resistant mask. I try to do it through a mask.

Hereinafter, embodiments of the present invention illustrated in the drawings will be described in detail.

First, as shown in FIG. 1, the entire surface of an N-type silicon substrate 1 is heat treated in an oxidizing atmosphere to form a thin 8i0° film 2 with a uniform thickness, and then chemically coated on the Si film 2. A silicon nitride film 3 is deposited by optical vapor deposition (OVD).

Next, as shown in Fig. 2, 7 otoresists 4
was deposited in a predetermined pattern, and using this as a mask, the underlying silicon nitride layer 3 was etched to form each M I 8 FET (MetalInsul
ator 8emiconductor Field
The oxidation-resistant mask shape is patterned to define each active region of the EffectTransistor. Therefore, the region immediately below the removed portion 5 of this oxidation-resistant mask 3 is exposed to both MI 8
This is a region where a field 8i0@ film for isolating the FET is to be formed.

Next, as shown in FIG. 3, the photoresist 4 is removed by etching, and after t, the entire surface is irradiated with a boron ion beam 6. At this time, by selecting the fT implantation energy of the ions, the ion beam 6 is transmitted not only through the silicon nitride film 2 but also through the silicon nitride film 3, and a boron implantation region 7 is formed over the entire surface area of the substrate 1 by, for example, 4X. 10”c
It is formed uniformly with a dose of ra-''.

Next, as shown in FIG.
A photoresist 8 is applied over one of the oxidation-resistant masks 3 so as to cover a portion of the opening 5 . The pattern of this photoresist 8 determines the N-type well and P-type well, which will be described later.
It should be noted that a photomask was provided using this as a reference (mask alignment guide), and patterning was performed by photoetching.

Next, as shown in FIG. 5, the entire surface is irradiated with a phosphorus ion beam 9 using the photoresist 8 as a mask. The energy of this ion beam is 7 phosphorus ions, 8
is not transmitted, but 8i0. It is selected to transmit through the membrane 2 and the oxidation-resistant mask 3.

As a result, phosphorus is implanted directly under the sio film 2 and the oxidation-resistant mask 3 in the region not covered with the photoresist 8, and a phosphorus implantation region 10 is formed at a dose of 8×10"Ca1-". Since this amount of phosphorus implantation is in excess and about double that of the boron implantation region 7, the boron concentration in the boron implantation region 7 is compensated to become N-type, and the phosphorus concentration in the phosphorus implantation region 10 is relatively V
C4X 10” (approximately 12).

Next, as shown in FIG. 6, the K photoresist 8 is removed by etching and then heat treatment is performed to drive and diffuse impurities in the boron implanted region 7 and the phosphorous implanted region 10, thereby forming the P-type well 11 and the N-type well 12. Each other Kr14! II to form.

Next, as shown in FIG. 7, a heat treatment is performed in an oxidizing atmosphere to selectively grow a field 8i01 film 15 for element isolation in a region where the oxidation-resistant mask 3 is not present. During this selective oxidation, since the thickness of the 8i01 film 2 on each well 11 and 12 is uniform (see FIG. 1), the field 8i01 film 15 under the oxidation-resistant mask 3 is
The amount of penetration of the bird beak part of 1.5m is 11 in both wells.
and 12 are equal to each other.

Next, after removing the oxidation-resistant mask 3, the underlying Sin film, and the film 2 by etching, a gate oxide film 18 is formed in each element region by thermal oxidation in an oxidizing atmosphere, as shown in FIG. Polysilicon is grown on the entire surface, and after a known phosphorus treatment, patterning is performed by photoetching to form polysilicon films 19 and 20 in the shape of gate electrodes, respectively.

Next, as shown in FIG. 9, the surfaces of each polysilicon film 19 and 2o are thinned by thermal oxidation in an oxidizing atmosphere.
II 21 and H 221 after forming HL, N type fy
A photoresist 23 is deposited on the area of the x-hole 12, and the entire surface is irradiated with an ion beam 24 of phosphorus or arsenic. This allows the photoresist 23. Field 810. Membrane 1
Using 5 and polysilicon film 19 as masks, ions are implanted through gate oxide film 18, and through annealing, N+ semiconductor regions 25 and 26, which will become source or drain regions, are formed in self-aligned lines (self-aligned K).

Next, by covering the region of the P-type well 11 with a photoresist (not shown) and irradiating it with boron ions, a P+-type region, which will become a source or drain region, is formed in the N-type well 12 as shown in FIG. Semiconductor regions 27 and 28 are also formed by self-alignment lines, respectively. After a phosphosilicate glass film 29 is deposited on the entire surface by OVD, known photoetching is performed to form contact holes 30, 31, 32, and 33, respectively.

Next, as shown in FIG. 11, aluminum is deposited on the entire surface using, for example, vacuum evaporation technology, and patterned using known photoetching to form each aluminum pattern [134, 35].
, 36 are formed respectively. This is a P-type twer] 1
The N-channel MI8FET on the side and the P-channel MI5FET on the N-type well 12 side are connected to each other by aluminum interconnections, a common input is given to the polysilicon gate electrodes 19 and 20, and a common input is provided from each diffusion region 26 and 27. Create a 0MO8 inverter, NAND gate, etc. that extracts the output.

According to the method of this embodiment explained above, each MI8FET
The photoresist 8 for well formation is patterned using the oxidation-resistant mask itself, which determines the active area of the well (Fig. 4), and in particular, the phosphorus implantation for the N-type well is performed through the oxidation-resistant mask 3 (Fig. 5). Therefore, to form the active region, it is not necessary to use the step as described above as a mask alignment guide, and therefore, etching or surface oxidation of StO for such a step is unnecessary.
It is possible to reduce man-hours and improve work efficiency. In this case, each well 11 and 12 is implanted with Poron (
Since the well regions are defined by the phosphorus implantation (FIG. 5) K using the latter seven photoresist patterns 8 as a mask (FIG. 3), the well regions can always be formed at predetermined positions with self-alignment.

In addition, in the selective oxidation process (Fig. 7), the 8i0 film 2 under the oxidation-resistant mask 3 is made of a surface oxide film formed to a uniform thickness in the process shown in Fig. 1, so that the field part is 8i0. The amount of encroachment of the bird's beak portion 15a of the film 15 is equal for both the P-channel and N-channel FETs; Since they are formed with the same area, the 8i0. Compared to the method of forming steps, the area of the oxidation-resistant mask can be reduced, and the spacing between each active region can be made smaller, allowing for highly integrated MO8I.
You can create O.

Furthermore, after first implanting boron into the entire surface (Fig. 3), ffN
A photoresist 8 for well 11 is provided (Fig. 4), and using this as a mask, phosphorus is implanted so as to pass through the oxidation-resistant mask 3 (Fig. 5), so it is used as a mask for determining the N-type well. 8, each well 12 and 11
can be formed with Selfa Line.

Although the present invention has been illustrated above, the embodiments described above can be further modified based on the technical concept of non-invention.

For example, the boron implantation shown in FIG.
It may be carried out immediately after the formation of. In the step shown in FIG. 3, phosphorus is implanted into the entire surface, and the photoresist 8 shown in FIG. 4 is provided on the N-type well region, and in the step shown in FIG. You may also do so. Furthermore, the conductivity type of each semiconductor region described above can be converted to an opposite conductivity type. Note that the present invention is applicable not only to the above-mentioned OMOS IO but also to various devices in which elements are isolated by a field oxide film and have a well in the element region.

[Brief explanation of drawings]

FIGS. 1 to 11 are cross-sectional views showing a method for manufacturing 0MO8 according to an embodiment of the present invention in order of steps. In addition, in the symbols used in the drawings, 2 is 8i0
．． 3 is an oxidation-resistant mask, 4 and 8 are photoresists,
7 is boron implantation area, 10 is phosphorus implantation area 1, 11
is P-type well, 12 is N-type well, 15 is field 8
i01 film, 19 and 20 are polysilicon gate electrodes, 2
5 to 28 are source or drain regions. Agent, Patent Attorney Bo 1) Li Xin Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. forming an oxidation-resistant mask in a predetermined pattern on a semiconductor substrate to define an active region; forming a second mask on the semiconductor substrate to define a well region based on the pattern of the oxidation-resistant mask; selectively introducing a predetermined impurity into the semiconductor substrate side through the oxidation-resistant mask using the second mask, and forming a well region having a shape corresponding to the second mask by heat treatment. and a step of selectively growing a field oxide film for element isolation on the semiconductor substrate using the oxidation-resistant mask after removing the second mask. Production method.