JPS58183A - Manufacturing method for semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a highly integrated, shallow diffused layer by a method wherein a well region on a semiconductor substrate and a region on the substrate lacking such are divided by a field oxide film and the surfaces of the respective regions are provided with gate electrodes across gate oxide films, and the gate oxide films act as masks for the formation of channel regions, and the channel regions are formed by diffusion. CONSTITUTION:A P<-> type well region 202 is diffusedly formed in an N type semiconductor substrate 201 and the resultant PN junction exposed on the surface of the substrate 201 and a part of the portion lacking a PN junction are respectively covered with thick field oxide films 203. Thin gate oxide films 204 are provided to respectively cover the surfaces surrounded by the films 203, and the central portion is provided with a polycrystalline Si made gate electrode 205. They are alternately covered with a mask 206 exemplifiedly of resist for the application of an impurity for the formation of a P channel and an N channel 207. After this, only the superficial layer of the electrode 205 is oxidated for the formation of an oxide film 208 and the entire surface including the film 208 is covered with an oxide film 210. A window is provided and each channel 207 is provided with an Al electrode 212 across a polycrystalline Si layer 209.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing 0M0TIIWjlXGO. As is well known, the 0M0I element is a bipolar element 1M
It can be said that this element is extremely superior in terms of power consumption per paper compared to the 01 element. For this reason, they are used in many meter-pull devices that use electricity as a power source. Furthermore, due to the advantage of low power consumption, OII is expected to be used as a replacement for pie pouch elements or summer Mol elements in the future. On the other hand, recently, in addition to low power consumption,
^Isbeed. The highly integrated awes Yasuko ON is also in progress. As a result, a shallow diffusion layer with a short length and a shallow diffusion layer of 0M
08) When the diffusion layer that is necessary for the chingister element is made shallow, especially as an interlayer, the diffusion layer, in the case of the NO glue stimulator element, the source/drashi layer, and the metal wiring, generally, When in contact with aluminum or silicon-containing metal (hereinafter referred to as aluminum), the diffusion coefficient of aluminum into the silicon substrate is relatively large. The source ψ diffuses to a layer below the drain layer, destroying the PM junction, and may not operate as an MO8 device.Therefore, in the present invention, the diffusion layer is made shallow, and the aluminum penetration seen above is avoided. 0M that can prevent the phenomenon
This is a method for manufacturing an O8 element.

#
Field enhancement a' formed by selectively oxidizing the substrate
103800-10001 gate oxide film 104. A gate electrode 105 is formed of polycrystalline silicon, and a resist 1 is formed.
06, the P and Y channel regions are separately masked, and B ions and P ions, respectively, are diffused into the substrate by an ion implantation device to form P and N channel source/drain layers 107. (Figure 1 (IE)') Next,
A silicon oxide film 108 is deposited by vapor phase growth or the like, and a contact hole 109 is formed in a part of the diffusion layer by a photoetching process.

(FIG. 1(A)) Further, aluminum (Al-based silicon) is deposited by sputter deposition or the like, and the aluminum is connected to the diffusion layer 107 by the same photo-etching process to form an aluminum wiring 110. . (Figure 1 (C)) Using the above method, 0M0
The B element is manufactured. However, in recent years, the depth of the diffusion layer (referred to as X) has become shallower due to speed and miniaturization, but aluminum exhibits large compatibility with silicon substrates, and therefore, as shown in Figure 1 (j). As shown in , after forming the aluminum 110, the aluminum 110 reacts with the substrate 107 (corresponding to the diffusion layer here) by a thermal process such as a sink. At this time, if d is shallower than the reaction layer between aluminum and the substrate 107, the aluminum will penetrate into the substrate 101, and the gap between the substrate 101 and the diffusion layer 107 will be reduced. Father-in-law's attack is destroyed and normal M
Does not work as an Os transistor. Therefore, with the conventional method, it was not possible to blindly reduce the depth of X. In the present invention, s') can be made shallow, and the degree of integration is as good as that of conventional manufacturing methods. FIG. 2 is a cross-sectional view of the manufacturing process of the 0M0B process O of the present invention. N-type substrate 201, P-well 202 field oxide film 203
．． A gate oxide M 204 + gate electrode 205 of polycrystalline silicon is formed, and a P channel 2 is formed using a resist or a silicon oxide or nitride film as a mask 206.
'07, M channel 207 is doped with impurities.

(Fig. 2 (α)) After light oxidizing the upper layer of the gate electrode 205 to form an oxide film 208 of 500 to 10001, a contact hole is opened in the gate oxide film 204 and polycrystalline silicon is formed. , 500 to 20,001 was deposited and the contact portion was photoetched to be larger than the contact hole. Next, by vapor phase growth etc., 3
000~6000X silicon oxide film 210 is deposited, a contact hole is formed in the -Ml' channel region,
P is applied to the P diffusion layer 207 through the polycrystalline silicon 209.
B ions, which are type impurities, are diffused.

(Fig. 2 (h)) Furthermore, a contact hole is opened on the M channel side, and a resist or silicon nitride film is used as a mask 211k.
and then doped with P ions, Mu ions, etc. (FIG. 2(C)) Finally, the above mask material 211 is removed, and Arun silicon 212 is sputter-deposited and etched to complete contact with the source and drain. (Second
Figure (tL)) Figure 2 (-) shows the contact portion with the diffusion layer. In the present invention, diffusion is performed once again only in the contact area, so even if the X (in this case d) in the MOll) transistor channel part is shallow, the contact part's X (d) becomes deeper than d. . Moreover, since the aluminum 212 is absorbed into the substrate diffusion layer 209 via the polycrystalline silicon 209, the depth of the aluminum substrate 207 is shallower than before, and the depth of the aluminum substrate 207 is shallower than before. Breakthroughs can be prevented. In this manner, by using polycrystalline silicon in the contact portion, a C1MO8 element with a shallow channel diffusion layer, high degree of integration, and no isbead can be manufactured.

[Brief explanation of drawings]

Figure 1 (lL) to Cd) shows the conventional silicon gate O
MO! 110 is a diagram illustrating an example of a manufacturing method. Figure 2 (α)
〜(#) indicates the manufacturing method of 0MO8-O of the present invention.
i:i. Applicant: Iwa Seikosha Co., Ltd. Agent: Patent Attorney: Tsutomu Mogami Figure 1

Claims (1)

[Claims] In a method for manufacturing a complementary metal oxide conductor element (hereinafter referred to as a QMOI element), a contact nail is formed to expose a part of the substrate when the O-contact part of the substrate and the metal wiring is connected to each other. , deposit polycrystalline silicon, lllOM
O5l element□? In the channel region, the polycrystalline silicon is passed through to diffuse the decap impurity into the substrate, and in the channel region, the polycrystalline silicon is passed through the polycrystalline silicon to diffuse the M 臘 impurity into the substrate to form a metal layer. . A method of manufacturing a semiconductor device, comprising patterning the metal layer and contacting the P channel and the summer channel diffusion layer with a gold layer wiring via polycrystalline silicon.