JPS58184A - Manufacturing method for insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent pad caused contamination and thereby to stabilize element characteristics by a method wherein a polycrystalline Si layer is provided in the bonding pad forming section on an SiO2 film and the entire surface is coated with a PSG film whereupon a pad is built. CONSTITUTION:A P type well region 8 is diffusedly formed in an N type Si substrate 11. The whole surface is covered with an SiO2 film 12 and openings are provided in places where a source, drain, and gate and to be provided. Next, the substrate 11 and the exposed surface of the region 8 are coated with a gate SiO2 film and an polycrystalline Si film is grown over the entire surface including the SiO2 film. Etching is performed for the formation of gate electrodes 9a and 9b on the substrate 11 and the region 8 with a prescribed size SiO2 film working as underlay. At the same time, a bonding pad forming polycrystalline Si film 17 is formed on one of the films 12 surviving the etching process. Formation follows on the entire surface of an SiO2 film 10a, wherein a window is provided. A P<+> type source and drain regions are diffusedly formed on the both sides of the electrode 9a and an N<+> type source and drain regions are diffusedly formed on the both sides of the electrode 9b. At the same time, after endowing the film 17 with conductivity, the entire surface is coated with a PSG film 15 across which an Al pad 13 is provided on the film 17.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing an insulated gate type semiconductor device.

In particular, the present invention relates to a method of manufacturing a MOS IC having a silicon gate structure.

In an insulated gate type semiconductor device, the surface charge of the conductor is controlled by a gate electrode (11111i) via an insulator, so the characteristics of the surface of the conductor are particularly important.

The present inventor has analyzed leak failures that are likely to occur due to variations in the surface characteristics of the above-mentioned conductor.

It was found that this was mainly caused by contamination during the aluminum deposition process for forming electrodes and wiring. The dirt is particularly large in the pounding pad area.

That is, the thermally oxidized 5iQ1 film 2 covering the silicon substrate 1
Aluminum bonding pad 3 formed on top
In the vicinity of pad 3 and internal interconnections (not shown)
During aluminum evaporation to form aluminum 3, the aluminum 3 is contaminated by positive ions such as Na+ ions, and the contaminated ions enter the oxide film 2, thus forming an inversion layer 4 on the surface of the substrate 1, resulting in flattening of that part.・Band voltage vFB decreases and threshold voltage ■th changes (first
(see figure). In FIG. 1, reference numeral 5 indicates a PSG film covering the oxide film 2, and reference numeral 6 indicates a C V D Si Ot film formed on the substrate 1 after the formation of the pad 3.
It is a membrane.

Therefore, in order to find out what kind of WI structure is best to prevent the fluctuation of the torsion th, we prepared a first-order bonding pad form (like Yu), and in each case, aluminum V when pad 3 is contaminated, 8V
abeta.

Prisoner Same as Figure 1 above, but CV D Si
The end of the Ot film 6 reaches the top of the aluminum pad 3 and is no longer in use. (1st et (A)) V, B = -50V0)
Thermal oxidation S10. A aluminum pad 3 is formed on the upper surface of the PSG film 5 covering the film 2.

[Figure 2 (8)]] V, B = -6 fcl Same as in Figure 1 above, but aluminum
The PEG film 5 is not formed under the periphery of the pad 30. [
:Figure 2 +C1:) V, B = -12V (g) Thermochemistry S
A polycrystalline silicon layer 7 is formed on the film 2 and below the aluminum pearl layer 3.

[flc2 Figure nV, B--4V0 (G) Same as above, but PSG film 5 is interposed between aluminum pad 3 and polycrystalline silicon 7. (211th (IC) V, B=OV+V+ are the parameters of the degree of contamination, and from these results it can be seen that in the case of (Kon) above, contamination of only three bonding pads can be prevented most efficiently.

The present invention was born from the above experimental results.

Its purpose is to perform aluminum bonding as described above.
The purpose is to prevent contamination of the pads 3 and stabilize the device characteristics.

Therefore, in the present invention, as shown in FIG. 2 (G) above,
The above thermal oxidation 8iQ is on the film (first insulating film) 2.

A polycrystalline silicon layer 7 is formed in the area where the bonding pad 3 is to be formed, and a PSG film (an insulating film 2) is formed on the upper surface of the substrate 1 containing the polycrystalline silicon.
It is characterized in that the bonding pad 3 is formed on the film 5. Moreover, it is also characterized in that the polycrystalline silicon 7 is formed at the time of forming the polycrystalline silicon that will become the gate electrode.In this case, the aluminum pad 3 and the first insulating film 2
It is necessary to provide a layer containing phosphorus between the two.

By doing so, it is possible to prevent surface inversion caused by contaminant ions that also enter the aluminum pad 3. Therefore, the second insulating film 5 and/or the polycrystalline silicon 7 are doped with phosphorus.

A specific manufacturing method of the present invention will be explained below.

FIG. 3 (al~(61 is a C-MOS
ple-mentary Metal oxide
8 semiconductor) is shown. +a+ N-type silicon substrate (<100>,
2Ω1m) IIKP type well 8 and substrate 11
Of the upper thermally oxidized 8i0* film (8500A thickness → 12, the portions corresponding to the source, drain/gate portions are selectively removed.tbl) By heat-treating the substrate 11, the 8iQ, film for forming the gate insulating film is removed. (0,1~0.2
After forming a polycrystalline silicon film (0.4 to 0.5 μm thick) for gate electrode formation by the VCCVD method, the silicon Ml is photoetched to form gates 9a and 9b. do. At this time, the polycrystalline silicon 17 in the portion where the bonding pad will be formed is left on the thermally oxidized S+Ot [12].

(cl On the above substrate 11, polycrystalline silicon 17 and P type '7 El 8 s minute t5115 CVD 8 i
A P+ source S and drain D are formed by diffusing boron using the film 10a (3000A thick) as a mask. ldl (Contrary to C1, polycrystalline silicon 17 and P-type well 8 (')Fj except 15 minutesffli 5
CVD 8 io, film (3000A thickness) N+ source S' by phosphorus diffusion using film (3000A thickness) 10b as a mask
, forming a drain D'. At this time, the polycrystalline silicon 717, which is an important part of the present invention, is also doped with phosphorus. lel
PS is applied to the entire upper surface of the substrate 11 by CVD' method.
G film (9000A liaison) 15%: formed, followed by film 15
After selectively removing the connotact portion, the bonding pad 13 and the source, drain/gate electrodes are formed by photoetching aluminum (13500A thick) deposited on the entire surface, and then the top surface of the substrate 11 is A PSG film (5000A thick) 16 is formed so that only the aluminum pad 13 portion is exposed. Due to this.

A bonding pad configuration similar to that shown in FIG. 2 (8) is obtained.

In addition, FIG. 4 (sub-1dl shows a processing process diagram when the present invention is applied to a P-channel type silicon gate MOS.
Portions of the ift film 22 corresponding to the source, drain, and gate portions are selectively removed, and a gate 9c' is formed in the same manner as in step (b) for C-MO8K. At this time, the polycrystalline silicon 27 is left on the thermally oxidized S t Ot M 22 in the area where the bonding pad will be formed, but the silicon 27 is diffused with boron to form the P+ north S and drain D. It is P-shaped. Therefore, in the present invention, in order to convert the silicon 27 into N-type, before proceeding to the first step, for example, the N-type silicon 27 is
+ Silico/phosphorus on 27 during diffusion etc.? Dope. (bl
A PSG film 2 is formed on the entire upper surface of the substrate 21 by CVD method.
5 is formed, and then a contact portion of the film 25 is selectively removed. After depositing lcl aluminum on the entire surface, bonding pad 2 is formed by photo-etching.
3, and source, drain, and gate electrodes are formed. fdl The KPSG film 261 is formed so as to expose the aluminum pad 23 portion of the substrate 21.

Note that in the case of an N-channel/channel type MOS, the polycrystalline silicon under the bonding pad is also doped with phosphorus when forming the source and drain, so it is clear that the present invention can be easily applied. Ah, uh.

As described above, according to the method for manufacturing the insulated gate type conductor device of the present invention, the aluminum bonding pad 3
, 13.23 Underneath the treated protective film (PEG film 5)
, 15.25. Since polycrystalline silicon y7,17.27) is arranged, surface contamination from the pad portion can be prevented and electronic characteristics can be stabilized.

The protective film also has the effect of protecting the underlying layer during wire body/dying.

[Brief explanation of drawings]

1st fi! J is a cross-sectional view for explaining the heel point in a conventional device of this type, #I2 (4) to (Q is a cross-sectional view showing various types of bonding pads used in experiments that are the basis of the present invention) , FIG. 3 111~(el indicates the present invention C-
Processing process diagram when applied to MOS. FIGS. 4m to 4fdl are process process diagrams when the present invention is applied to a MOS having a P-channel type silicon gate structure. 1.11.21...Silicon substrate, 2,12.22.
... Heat intoxication Sin, film, 3,13.23... Aluminum bonding para)", 5.15.25...
PSGII, 6, 16.26...P 8 G! g%7
, 17°27... Polycrystalline silicon. Agent Patent Attorney Susuki 1) Toshiyuki, - Tori Figure 2 Q 1 Law Li -C4 (, ()

Claims (1)

[Claims] 1. A step of forming a thick insulating film and a thin insulating film on the conductor, a step of selectively forming a polycrystalline silicon layer on the thick insulating film and the thin insulating film, and a step of forming a polycrystalline silicon layer on the thin insulating film. Forming source and drain regions on the surface of the conductor using the polycrystalline silicon/layer as a mask, forming the thick insulating film, the thin insulating film, and the polycrystalline silicon layer formed thereon so as to cover them. An insulated gate type semiconductor comprising the steps of forming another insulating film, and forming a metal layer on the polycrystalline silicon layer formed on the thick insulating film via the other insulating film. Method of manufacturing the device.