JPS5818940A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To highly integrate an electrode wiring pattern by a method wherein a resist mask is applied to an insulating film on an Si substrate for opening and Al is stacked by making high level difference and after applying the removal of etching to the Al by leaving the second resist at the window section by self- matching, the resist is removed to superimpose Al wiring. CONSTITUTION:The first resin mask 24 is provided at SiO2 23 on an Si substrate 22 having diffusion 21 for opening and Al 26 is evaporated to cover the Al 26 with the second resin 27. Plasma etching is applied by using O2 and the resin 27 is left at the window section only. The resin 27 is used as a mask and the removal of etching is applied to the Al 26 except the window section and the Al 26 is left at only the window by removing the resin 24, 27. Next, Al is evaporated for photo etching and a desired electrode pattern 28 is made. This composition can leave the second resin at the window section by self-matching and electrode wiring pattern size is reduced without a decrease in yield for high density and reliability can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for fabricating a highly reliable semiconductor device that achieves high density by reducing the nine-turn dimension of electrode wiring.

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as ICs) are becoming larger and larger year by year, and along with this, the dimensions of their holes and turns are becoming smaller. This tendency is particularly remarkable in memory ICs. In a memory IC, since the number of electrode wirings is large, the area occupied by the electrode wirings is also very large, and each electrode wiring is connected to an impurity diffusion region in a semiconductor substrate via a contact window. In the conventional design standard, for example, if the standard is 3 μm, the contact window is 3 μm.
The electrode wiring wired thereon has a dimension of about 5 μm in consideration of mask alignment accuracy, etching accuracy, etc. For this reason, the dimensions of the electrode wiring only around the contact window are large.
In ICs that require a large number of windows, the chip area increases, resulting in a decrease in the reliability of the chip substrate and, ultimately, in the yield. In order to solve this problem, it may be possible to make the dimensions of the electrode wiring and the contact window the same, but due to misalignment of the mask and thinning of the electrode wiring due to etching, a part of the contact window may be exposed. In addition to lower reliability, there is a new problem in that the contact area of the electrode wiring becomes smaller, which increases the number of contact failures.

In order to solve this problem, a manufacturing method as shown in FIG. 1 has also been proposed. In step (a), an insulating film 3 is formed on a semiconductor substrate 2 having an impurity diffusion region 1, and then a photoresist is formed in accordance with the impurity diffusion region 1. In step (b), the photoresist 4 is etched using an etching mask. The exposed insulating film 3 is removed by etching to form a contact window 5, and then a first metal film 6 having the same thickness as the insulating film 3 is deposited. In step (c), photoreno stock turn 4 and this photoresist no? The metal film 6 on the turns 4 is removed at the same time to flatten the surface. Next, in step (d), a second metal film for electrode wiring is vapor deposited on the surface and connected to a part of the first metal film 6, and then an electrode wiring pattern 7 is formed.

According to such a process, the first metal film 6 is buried in the contact window 5 at the same height as the surrounding insulating film 3, so that the electrode wiring/mother turn 7 is formed. In this case, the electrical connection with the impurity diffusion region 1 is ensured and simplified. Furthermore, in the past, the width of the electrode wiring/e-turn was made wider only around the contact portion to prevent wire breakage due to a step in the periphery, but according to the above method, the first metal film 6 is embedded in the contact window 5. Therefore, electrode wiring and
Although there are effects such as being able to reduce the size of the lean, there are also the following problems. In other words, as the method for vapor deposition of the electrode wiring metal that forms the electrode wiring and mother turns, we adopted the suction evaporation method, which provides good coverage of the surface steps of the semiconductor substrate. Then, when depositing the first metal film, the coverage was too good, so the (,
), a thick metal film 13 is also deposited on the contact window 110 and the turn edge portion 12. FIG. 3 is a plan view showing the state of the metal film 13 formed by this step-like vapor deposition method, and the thickness of the metal film at the cut-turn edge portion 12 is approximately the same as that at the flat portion. Even if photorenost removal is attempted in this state, the metal film thickness of the pattern etch portion 12 is large, so the solvent will not penetrate. Even if the solvent penetrates through the pinhole 15, the metal film of the contact window 11 Since the metal film 13' on the photoresist no. 13 and the photoresist no. 13 and the turn 14 are not separated, the photoresist stock turn 13' is not removed, and it is very difficult to leave the metal film 13 only on the contact window. .

An object of the present invention is to provide a method for manufacturing a semiconductor device using an electrode/gut formation method that solves these problems.

Next, a method of manufacturing a semiconductor device according to the present invention will be explained based on the embodiment shown in FIG.

Step a: Having an impurity diffusion region 21, for example, Sr +
Si is placed on a semiconductor substrate 22 such as CaAg or GaP.
02.

An insulating film 2.3 of Si3N4*Ta203 or the like is formed, and a photoresist pattern '24 is formed in alignment with the impurity diffusion region 21.

Step b: Using the first resin turf 24 as an etching mask, the exposed portion of the insulating film 23 is removed by wet etching, dry etching, etc. to form a contact window 25.

Step C: At, Au with the same thickness as the above insulating film.

A first metal film 26 consisting of M or the like is deposited, and a second resin 27 of photoresist is applied to the entire surface.

Step d Dry etching such as plasma etching, snokter etching, ion etching, etc. is performed on the surface of the second resin 270 using oxygen gas, leaving the second resin 27 only in the tactile area 25.Step e 2nd- Using the resin 27 as an etching mask, the first metal film 26 other than the contact portions 25 is removed by etching. ! Step f: Remove the first resin 24 and the second resin 27, leaving the first metal films 2 and 6 only on the contact portions 25.

Step g After depositing a second metal film for electrode wiring such as AlrMorAu, desired electrode wiring/mother turns 28 are formed by photolithography.

Previously, it was 5i02 (:';5000X)
(Dmi) (Since the first metal was embedded in the contact window with 0 step difference, it was difficult to leave the second resist only in the contact window portion with a good yield due to the small step difference, but in the present invention, is the first renos I (≧10.0O
OX) and an insulating film are stacked to form a multilayer structure, it is possible to form a large step, and the second resist can be easily left in the contact window with good yield, and the first resist can be easily removed. The process can also be omitted.

By adopting the above process, it is possible to leave the second resin in a self-aligned manner with respect to the contact window, and a thick metal is deposited on the four-turn edge of the contact part. It also becomes possible to form electrode wiring and mother turns without reducing yield.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing a conventional method for manufacturing a semiconductor device, FIG. 2 is a cross-sectional view to explain problems with the conventional method, FIG. 3 is a plan view thereof, and FIG. 21. Impurity diffusion region, 22. Semiconductor substrate, 2.
3... Insulating film, 24... First resin mother turn, 2
5... Contact window, 26... Metal film, 27...
Second resin, 28...electrode wiring/mother turn. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A first layer having a predetermined turn on an insulating film on a semiconductor substrate.
forming a resin film and etching off the insulating film using the first resin film as an etching mask; depositing a first metal film with the same thickness as the insulating film and depositing a second resin on the surface; a step of applying a film, a step of etching the second resin film until the surface of the first metal film on the first resin film is exposed, and a step of etching the second resin film using the second resin film as an etching mask. The first metal film is etched on, and the first metal film is etched on. The method is characterized by comprising a step of removing the second resin film, and a step of depositing a second metal film and selectively leaving the second metal film so as to be connected to the first metal film. A method for manufacturing a semiconductor device.