JPS58194574U - Synchronous separation circuit - Google Patents

Synchronous separation circuit

Info

Publication number
JPS58194574U
JPS58194574U JP9199882U JP9199882U JPS58194574U JP S58194574 U JPS58194574 U JP S58194574U JP 9199882 U JP9199882 U JP 9199882U JP 9199882 U JP9199882 U JP 9199882U JP S58194574 U JPS58194574 U JP S58194574U
Authority
JP
Japan
Prior art keywords
circuit
separation circuit
synchronous separation
integration circuit
integration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9199882U
Other languages
Japanese (ja)
Inventor
正義 漆谷
義博 青井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9199882U priority Critical patent/JPS58194574U/en
Publication of JPS58194574U publication Critical patent/JPS58194574U/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の同期分離回路め回路図、第２図は第１図
の各部波形図、第３図は本考案の一実施例における同期
分離回路の回路図である。FIG. 1 is a circuit diagram of a conventional synchronous separation circuit, FIG. 2 is a waveform diagram of each part of FIG. 1, and FIG. 3 is a circuit diagram of a synchronous separation circuit according to an embodiment of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複合映像信号から雑音成分を除去する積分回路と、該積
分回路出力から水平若しくは垂直同期信号を分離する回
路とを備える同期分離回路において、前記積分回路の放
電路に、並列に且つ順方向にダイオードを接続してなる
同期分離回路。In a synchronization separation circuit comprising an integration circuit that removes noise components from a composite video signal and a circuit that separates a horizontal or vertical synchronization signal from the output of the integration circuit, a diode is connected in parallel and in the forward direction to a discharge path of the integration circuit. A synchronous separation circuit is formed by connecting the .
JP9199882U 1982-06-18 1982-06-18 Synchronous separation circuit Pending JPS58194574U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9199882U JPS58194574U (en) 1982-06-18 1982-06-18 Synchronous separation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9199882U JPS58194574U (en) 1982-06-18 1982-06-18 Synchronous separation circuit

Publications (1)

Publication Number Publication Date
JPS58194574U true JPS58194574U (en) 1983-12-24

Family

ID=30100216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9199882U Pending JPS58194574U (en) 1982-06-18 1982-06-18 Synchronous separation circuit

Country Status (1)

Country Link
JP (1) JPS58194574U (en)

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