JPS58196742A - Digital signal multiplexing method - Google Patents

Abstract

PURPOSE:To multiplex high-speed signals, by multiplexing digital signals into which a synchronizing and a discrimination signal are inserted previously on bit multiplex basis. CONSTITUTION:A master clock 4-4 is frequency-divided by two at a DFF4-1, whose output is supplied to the 1st signal generation part 4-2 and the 2nd signal generation part 4-3; and their outputs 4-10 and 4-11 are ANDed with signals Q and Q' of the DFF4-1 by AND gates 4 and 4 and their outputs are ORed by an OR gate 4-12 to multiplex digital signals (the 1st signal 4-7 and the 2nd signal 4-8) into which the synchronizing signal and discrimination signal are inserted previously.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for multiplexing high-speed signals in high-speed digital signal transmission.

FIG. 1 shows a conventional method of multiplexing two signals. In FIG. 1, 1-1.1-2 are two signals to be multiplexed, a first signal and a second signal. A1
-2~A, +2. The bits in the respective signals B, . . . -Bi+2tit are shown.

1-3 is the multiplexed word after multiplexing, 1-43YNC
is multiplexed information having identification signal information. FIG. 2 is a block diagram of a circuit for performing the above multiplexing. In FIG. 2, 2-1 is a clock conversion section, 2-2 is a first signal generation section, 2-3 is a second signal generation section, and 2-4 is a multiplexing section. 2-5 is a master clock, 2-6 is the same as the clock to the multiplexed WJ 2-4, and 2-7 is a clock with a frequency corresponding to the first and second signals. 2-8 and 2-9 are the first signal and second signal 1-2 in FIG. 1, and 2-10 is a multiplexed signal after multiplexing.

Next, the operation of the F multiplexing method will be explained. For example, the bit rate of the first signal 1-1 and the second signal 1-2 is set to 400.
Mbps, and if 1 pint of multiplexed information 1-4 is added every time 8 bits are multiplexed, the multiplexed signal 1-4 is added.
The bit rate of 3 is (4007 x (8) EN-1)/8) = 400X-Mbps.

Therefore, the clock 2-6 to the master clock 2-5 and the multiplexer 2-4 is 400x MHz, and the clock 2-6 to the first signal generator 2-2 and the second signal generator 2-3 is 400x MHz.
7 is 4ooMHz. The clock converter 2-1 must convert this clock. The multiplexer 2-4 generates 1 bit of multiplex information 1 every time it multiplexes the two signals 2-8 and 2-9 by 8 bits.
, -4 to output a multiplexed signal 2-10. However, in the above configuration, the clock conversion is at a ratio of 17=8, and the circuit that performs this conversion is complex. Also, multiplexing section 2--4? However, not only that, but if the bit rate becomes as high as the above example, the clock converter 2-1. The multiplexing section 2-4 had a drawback that it could not be realized by commercially available ICs such as ECL.

The present invention simplifies the configuration of the part that operates at the highest speed by performing single tζ bit multiplexing without giving multiplexing information during multiplexing, and by identifying after bit multiplexing during demultiplexing. , the purpose is to facilitate implementation.

When multiplexing, bit multiplexing is performed without giving multiple 1R information,
At the time of multiplex decomposition, by identifying after bit multiplex decomposition, it becomes easy to perform bit multiplexing, bit multiplex decomposition, and division of the clock by n (n implementation) for the part that operates at the highest speed.

An embodiment of the present invention will be described below. Figure 3 is 2
16 is a method of multiplexing two signals of the present invention. 3-1.3-2 are two signals to be multiplexed, the first
signal and second signal, and the difference from those in the conventional example is that a synchronization signal and an identification signal, or a signal that serves both (hereinafter referred to as an identification signal) Sa 3-4, Sb 3
−5.

This is a multiplexed signal after 3-3rd bit multiplication. In Figure 3, the temporal positional relationship of 5a3-4 and 5b3-5 is the same, but this is not necessarily necessary. Figures 4 and 6 show the operation of multiplexing and multiple decomposition in Figure 3. FIG. 2 is a block diagram of a circuit that performs this. In Figure 4 4-1
is the D-furinog 70 that divides the master clock 4-4 by 2.
Numeral 4-2 is a first signal generating section, 4-3 is a second signal generating section, and 4-5 and 4-6' are clocks obtained by dividing the master clock 4-4 by two, which are in opposite phases to each other. 4
-7.4-8 are the first signal and the second signal, and correspond to 3-1 and 3-2 in FIG. 3, respectively. 4-9 is a clock 4-5 that divides the first signal 4-7 and second signal 4-8 by two.
．． This is a multiplexed signal in which bits are multiplexed by AND gates 4-10 and 4-11 and OR gate 4-12 using 4-6. In FIG. 6, 5-1 is a bit multiplex decomposition unit that demultiplexes the multiplexed signal 6-4 using a clock 6-6, and 5-6.5-7 is the output bit multiplexed signal. . 5-2 is.

It is a signal identification unit that identifies which signal the signal 5-7 is.1. Based on the switching signal 6-10, the switching section 5-3 switches the two signals 5-8, 5-9 to the desired signal 1.

Next, the operation of the multiplexing method configured as shown in F will be explained. 61\J&-i is a time chart showing the operation of each part in Fig. 4, and the numbers correspond to each other. The waveforms of the M11 signal 4-7 and the second signal 4-8 are examples. First signal 4-7. The AND gate 4-10 performs the AND of the second signal 4-8 and the 2-frequency divided clock 4-5.
4-10 and use those logics as an or game) 4-
12 to obtain multiplexed signals 4-9. At the 51st link, the multiplexed signal 6-4 is demultiplexed, but the bit demultiplexer 5-1 only demultiplexes l(K bits, so
It is not determined whether the first signal or the second signal is output to the output 6-6.5-7. Therefore, the signal identification section 6-2
In this embodiment, it is determined whether the signal 5-7 is the first signal or the second signal, and the switching section 6-3 is thereby controlled to output the desired signal. A first example of the identification signal is shown in FIG. 7-1.7-2 shows the frame structure of the first and M22 signals to be multiplexed. 7
-3 is the frame signal of the first signal and “i” every 8 bits
, "o", and 7-4 is the second transmission frame signal with "l 11I," every 9 bits.
This is an alternating pattern of I"O".The above rain sounds have different frame lengths, so the signal identification section 6-2 synchronizes with an 8-bit frame, but depending on whether it synchronizes with a 9-bit frame, the two above The second example of the identification signal is shown in Fig. 8. In Fig. 8, 8-1.8-2
shows the frame structure of the first and second signals to be multiplexed. 8-3゜8-4 are the first and second respectively
In this example, the above two signals have the same frame length, but each frame signal 8-3, 8-4 has a length of 3 bits and is "101".
Since the signal is different from "110", the signal identifying section 5-2 can distinguish between the two signals based on the difference in the frame signals.

As described in 1 above, the present invention uses a plurality of signals to be multiplexed that already have a synchronization signal and an identification signal, or a signal that can serve as both, and does not give multiplexing information when multiplexing. When pit multiplexing and demultiplexing, bit multiplexing and demultiplexing are performed, and then the signals are distinguished by identification signals (this is why multiplexing, which must operate at the highest speed,
The multiplex decomposition and clock conversion parts are bit multiplexed,
Bit multiplicity decomposition and clock frequency division by n (n is an integer) are required, and these configurations are simple, which has the advantage of being easy to implement.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional method for multiplexing two signals, FIG. 2 is a block diagram of a circuit that performs the operation of the method shown in FIG. 1, and FIG. 3 is a diagram showing a second embodiment of the present invention. Fig. 4 and Fig. 6 are diagrams showing a method of multiplexing two signals, respectively.
A block diagram of a circuit for multiplexing and demultiplexing that performs the operation of the method shown in the figure, FIG. 6 is a time chart showing the operation of each part of FIG. 4, and FIGS. 7 and 8 are examples of identification signals. 3-1.3-2...Two signals to be multiplexed, 3-4.3-5...Synchronization signal, identification signal, or a signal that can also be used as these signals, 4- 1...D-
Flip-flop, 4-2...First signal generation section, 4-4...Master clock, 4-6 Master clock divided by two clock, 4-6...Master clock 2-divided clock (used inversely to 4-5), 4-7.4-
8...First and second signals, 4-9...
Multiplexed signal, 4-10, 4-11...antogame
), 4-12...OR 1 gate, 6-1...Bit multiplex decomposition unit, 6-2...
...Signal identification section, 6-3...Switching section, 6-4
...Multiple signal, 6-6...Clock,
5-6.5-7...°゛Bit multiplex demultiplexer output, 5-
8, 5-9...Switching section output, 7-1.7-2
...Frame configuration of first and second signals, 7-
3.7-4... Frame signal of first and second signals, 8-1.8-2... Frame structure of first and second signals, 8-3.8- 4... Frame signals of the first and second signals. Name of agent: Patent attorney Toshio Nakao and 1 other person11
IV4 Figure 2 Figure 3 Shi1 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] It is characterized by bit-multiplexing multiple digital signals including respective synchronization signals and identification signals without adding multiplexing information, and distinguishing each signal by an identification signal after bit-multiplexing during demultiplexing. Digital signal multiplexing method.