JPS58199543A - 半導体装置のパツケ−ジ - Google Patents

半導体装置のパツケ−ジ

Info

Publication number
JPS58199543A
JPS58199543A JP57082810A JP8281082A JPS58199543A JP S58199543 A JPS58199543 A JP S58199543A JP 57082810 A JP57082810 A JP 57082810A JP 8281082 A JP8281082 A JP 8281082A JP S58199543 A JPS58199543 A JP S58199543A
Authority
JP
Japan
Prior art keywords
package
film
plastic
nickel
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57082810A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0235467B2 (2
Inventor
Koichi Mase
間瀬　康一
Masayasu Abe
正泰 安部
Masaharu Aoyama
青山　正治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57082810A priority Critical patent/JPS58199543A/ja
Publication of JPS58199543A publication Critical patent/JPS58199543A/ja
Publication of JPH0235467B2 publication Critical patent/JPH0235467B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP57082810A 1982-05-17 1982-05-17 半導体装置のパツケ−ジ Granted JPS58199543A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57082810A JPS58199543A (ja) 1982-05-17 1982-05-17 半導体装置のパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57082810A JPS58199543A (ja) 1982-05-17 1982-05-17 半導体装置のパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS58199543A true JPS58199543A (ja) 1983-11-19
JPH0235467B2 JPH0235467B2 (2) 1990-08-10

Family

ID=13784764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57082810A Granted JPS58199543A (ja) 1982-05-17 1982-05-17 半導体装置のパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS58199543A (2)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633573A (en) * 1982-10-12 1987-01-06 Aegis, Inc. Microcircuit package and sealing method
JPS6212953U (2) * 1985-07-09 1987-01-26
JPH0260150A (ja) * 1988-08-26 1990-02-28 Semiconductor Energy Lab Co Ltd 電子装置およびその作製方法
US6756670B1 (en) 1988-08-26 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
JPWO2006100768A1 (ja) * 2005-03-23 2008-08-28 富士通株式会社 半導体装置及びその製造方法
JP2017034086A (ja) * 2015-07-31 2017-02-09 株式会社東芝 半導体装置および半導体装置の製造方法
JP2017168701A (ja) * 2016-03-17 2017-09-21 東芝メモリ株式会社 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5223248U (2) * 1975-08-08 1977-02-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5223248U (2) * 1975-08-08 1977-02-18

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633573A (en) * 1982-10-12 1987-01-06 Aegis, Inc. Microcircuit package and sealing method
JPS6212953U (2) * 1985-07-09 1987-01-26
JPH0260150A (ja) * 1988-08-26 1990-02-28 Semiconductor Energy Lab Co Ltd 電子装置およびその作製方法
US6756670B1 (en) 1988-08-26 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
JPWO2006100768A1 (ja) * 2005-03-23 2008-08-28 富士通株式会社 半導体装置及びその製造方法
JP2017034086A (ja) * 2015-07-31 2017-02-09 株式会社東芝 半導体装置および半導体装置の製造方法
JP2017168701A (ja) * 2016-03-17 2017-09-21 東芝メモリ株式会社 半導体装置

Also Published As

Publication number Publication date
JPH0235467B2 (2) 1990-08-10

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