JPS5819965A - Recording device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device, and more particularly to a storage device in which subordinate information in addition to one word can be accessed.

Generally, in a computer system, when a central processing unit (CPU) J accesses memory 2 as shown in FIG. 1, information is normally read and written in units of one word.

Therefore, when adding subordinate information to a specific word PK, conventionally the Kl word is divided as shown in Fig. 2(a) K and the original information and dependent information are stored in the word PK. Store them together in the message 1, and when accessing, C
Either divide these on the PIJJ side and execute round line compositing processing, or store the subordinate information by allocating another 1 word to the subordinate information as shown in the 2nd color). The circle is taken.

However, when the above-mentioned dependent information has no particular meaning for the calculation process itself, such as when it is information indicating the attributes of the stored content, the above method is as follows. Jin and K have such shortcomings. In other words, in the case of (second intermediate color), information other than necessary must be processed by the central processing unit, which increases the burden on the software. In the case of the second (intermediate color), the memory space becomes smaller in terms of cost since the extra l words are allocated.

The present invention has been made in view of the above circumstances, and in order to store subordinate information added to one word, one
Extend the word length to a specified one-word length that can be accessed by the CPU power, allocate the dependent information to this expanded part, store this dependent information, and create a register that can be read and written independently of the memory. It is very effective to reduce the burden on the software and reduce the memory space by creating a circuit configuration that controls the transfer of dependent information between these registers and memory when accessed by the CPUK. The purpose is to provide a storage device that can be used for

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. 3, 1 is the same central processing unit (cptt) as described above.
, z is a message in which the cpv word length of each address of the normal memory is extended to create a new extension word so that dependent information can be written in this extension part, and S is an extension of the word in memory 2 mentioned above. A write register 4 stores in advance dependent information to be written in the word extension section, and stores the dependent information written in the word extension section when information is read from the memory 2, and also stores this dependent information. The read register 1 that is transferred to the CPU1 side decodes the address information sent from CPU J through address bus 1 and transfers it to memory 2.
, the write register S, and the read register 4.

Information is transmitted between the CPU 1, memory 2, and registers 3 and 4 using a data bus, and address information is transmitted using a 7 address path 1. In addition, the register 8.
4F1 are each assigned a specific address, and are configured so that they can be written and read independently from the memory 2.

In the storage device configured as described above, information transfer with the CPU 1 is executed as follows.

First, the CPUJ sends the address information of the address to be accessed to the address bus 1, and selects a specific address in the memory z by a step. At this point, a specific address in memory 1 is specified, and the address decoder 5 decodes the address input and sends a selection signal to the message 2, write register 1, and read register 4. If the access to the memory 2 is for writing, Ilc Co., CPI
J 1 d As shown in FIG. 4, the main body information in the expanded memory word is sent to the data bus 6, and a write signal is also sent. In response to this write signal, pre-stored dependent information is transferred from write register 1 to data bus C.
Therefore, the memory 2 stores a memory word as shown in FIG. 4, which includes the contents of the main information and the subordinate information, using the same write signal.

In addition, in the case of reading, according to the read signal sent from the CPU J, the memory 2 also sends the memory word information of the specified address to the data bus 6,
The main information is transferred to cPUl, and the dependent information is transferred to read register 4. If QIU J requires this dependent information, it may read the dependent information stored in the read register 4 after a normal read operation.

The apparatus of the above embodiment has the following advantages. In other words, (1) 11 CP! when dependent information does not need to be changed frequently; J (The burden on the software is greatly reduced. (2) If the CPU does not particularly need to read dependent information, the burden on the software is eliminated. (3) It does not affect the storage space controlled by CPIJ. (4) There is no limit to the length of dependent information. (5) If there is no need to store dependent information in the entire physical storage space, implementation is possible for only a portion of the storage space.

Note that the read register 4 may be omitted if unnecessary. In the above embodiment, dependent information is stored in the CPU.
Read register 4KMjLJ according to the read signal of
), but this may also be done by a write signal from the CPU, however, in this case, some additional hardware is required.

FIG. 5 shows a case where the present invention is applied to a color character display device. In this case, color information is treated as subordinate information. This color information is cpv
Since it is not referenced on the side, the pre-read register mentioned above is omitted.

When the CPU side sends address information and Eirin information to each bus 1.6 and outputs a write signal, the memo
o The designated address Ka video information and the color information added to the video information from the write register 3 stored in advance are stored in the same write signal. At the time of reading, video information is transferred from the designated address of the memory 20 by cpvllK by the read signal.

FIG. 6 shows nine cases in which the present invention is applied to a write protection circuit for a storage device. In this example, the Mori write prohibition flag is treated as subordinate information. A memory protection flag register 8, an impedance register 9, and AND circuits 10 to 12 are provided in order to generate a read signal, a write signal, and a memory protection exception interrupt signal for the memo 9JK using this write inhibit flag. Flag information is stored in advance in this seven-way register 8, similar to the write register 3, and the flag information corresponding to the writing signal is read out by the timing of the write signal, and the AND circuit 11 sends a write signal to the memo 9JK. ], and a read signal is generated by an AND circuit 1o. Further, the flag information read from the memory 2, the 7 lag information of the 7 ladder register 8 via the inverter 9, and the cyand circuit JJK are used to generate a memory protection exception interrupt signal. Flag information d Since the CPU side does not need it, the above-mentioned read register is omitted, and the 0 circuit also has the O effect as described above.

As explained above, according to the present invention, in order to store subordinate information added to one word, the length of one word is made into a memory word length which is expanded by 4 times than the specified CPU word length, and this expansion Part JLJ: allocates dependent information, stores this dependent information, reads it out independently of memory, and provides a writable register device to
The circuit is configured to simultaneously control the transfer of subordinate information between these register devices and memory in one line when U0 is accessed, reducing the software load and reducing the memory space. can be provided.

[Brief explanation of drawings]

Figure 1: A configuration diagram for explaining a conventional storage device; Figure 2:
3 is a diagram for explaining the information format handled by a conventional storage device, FIG. 3 is a block circuit diagram of a storage device according to an embodiment of the present invention, and FIG. FIG. 5 is a rounded diagram illustrating the information format handled, and FIGS. 5 and 6 are circuit configuration diagrams each showing an application example of the present invention. 1-CPU,! - Memory, 8- Write register, 4-
read register, 5-address decoder, 6-data bus, 1-address bus, s-memory protection flag register,
#-...Inverter, 10-12...AND circuit.

Claims (1)

[Claims] (1) Optionally expanded to store subordinate information in addition to the one-word main information that the central processing unit can access! The central l&
Controls the transfer of subordinate information between the register device, memory, and 0 when accessing the memory of the physical device.When writing the main body information to 49, additional information corresponding to this main body information is stored in advance. The apparatus further comprises a write register for storing the dependent information from the readout nine predetermined information when reading the predetermined information from the memory. A storage device according to claim 2.