JPS582043A - Formation of multilayer wiring layer - Google Patents

Abstract

PURPOSE:To avoid the generation of step defects on the upper side wiring by performing etching treatment which is approximately equallizing the etching speed for an inter-layer insulating layer to that for the lower side wiring. CONSTITUTION:A through hole 15 to connect the lower side wiring 13 with the upper one 16 is provided on the layer insulating layer 14 form the multilayer wiring of a semiconductor device including etching treatment. Thereat, the etching treatment is performed in etching which approximately equalizes the etching speed for the insulating layer 14 to that for the wiring 13. When the wiring 13 is made of Al and insulating layer 14 of PSG, etching treatment is performed by sputter etching or plasma etching used with the mixed gas of chloride and fluoride gasses.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a multilayer wiring layer of a semiconductor device.

The multilayer wiring layer of a semiconductor device is the lower (first) layer on the semiconductor substrate.
Wiring, interlayer insulation! And from the upper (second) wiring, through holes (called contact holes or electrode windows) are provided in the interlayer insulating layer as necessary.
and second) the wiring is connected. This through-hole formation is performed by selective etching using a photoetching method.

Conventionally, for example, the wiring was made of AI and the interlayer insulation layer was made of PS.
G (If ph・shusili@yamagramsn is used, if one-selector v-ching is performed with dryer and ching, P2
Only the O interlayer insulating layer is etched and removed to form the At layer.
In addition, the dryer and chi/g at this time are, for example, the work, the chigka
41 T11 Pc1.5 * BCl2 t Use shift In particular, if it is a fine wiring Δ turn, it is likely to be misaligned, causing defective parts (deterioration parts of the upper wiring that will be formed later), and in some cases, disconnection. be.

When a through hole 2 is formed in the K PsG layer 1 by dry etching as shown in FIG. 1. In addition, in Figure 1 and Figure #I2, At
T side wiring M5 is 0 on semiconductor substrate 6 (8102M)
It is formed on top of 7.

In addition, in the above case, the selection process and chinda are used.8. If etching and etching are used, the result will be 5 as shown in No. 3-.In addition, the etching solution at this time may contain, for example, H3P0J+
7. Ammonium chloride or 7. Ammonium chloride and hydrofluoric acid aqueous solutions are used. The etching solution penetrates into the interface between the PSG layer 17Aj and the lower wiring 5, reducing the etching rate to 5%. The etching progresses, and the etching solution FiAt in the parentheses is also slightly etched, causing roughness on the At wiring surface. Then, when the Aj upper wiring 3 is formed, as shown in FIG. Defect 4 may occur, and in some cases, the upper wiring may be disconnected.

In order to prevent the above-mentioned step and f defects, the lower wiring corresponding to the through-hole formation location is made larger and larger/)-
〇Even if there is a shearing force of 1, it may be possible to expose only the upper surface of the lower wiring on the side surface, but this does not allow for high integration of the semiconductor device.

A method for forming a multilayer wiring layer that can avoid the occurrence of step and f defects in the upper wiring when the through holes provided in the glabella insulating layer are formed without going up to the lower wiring. It is to propose.

The present invention forms a multilayer wiring of a semiconductor device that includes a process of installing a through thread in a layer-to-layer insulation layer for connecting a lower wiring and an overlapping wiring, and a trenching process. A multilayer wiring layer characterized in that according to the method, the etching process is performed on the balls of the insulating layer between the eyebrows, and the etching speed is approximately equal to the speed of the lower wiring. This is the formation method.゛'The lower wiring is At and the wire between the legs is Pg.
G'7 and turtle contain chloride gas (e.g. CCl4
; pcz3 #BClt, preferably Pc15
) and dead gas (e.g. CF4).

c2F5c=', cmr3 fpreferably tIC'F
n) It is preferable to perform the above-mentioned etching process by plasma etching using a mixed tjx solution, such as dry etching solution instead of tinder, HsPO4, Fu, ammon.

It is also possible to carry out the process in a wet-temperature furnace using HNO3.

The invention will be explained below by means of embodiment examples in conjunction with the accompanying drawings.

A predetermined "functional area" (for example, collector, paste, emitter, or MO8 for Pairatotsunzostar, base, drain for Lanzostar) is formed, and heat is applied to the "surface" of the semiconductor (silicon) substrate 11. Oxidation by oxidation or CVD Ill (5to2jl) 12 Type IJl
(FIG. 5), and on this oxide film 12, a late conductive layer (Aj #a:ts
t, AtCu.

〒1', MO or W) form 13, - normal hotoe.

By using the Cinder technique WK, the lower wiring 13 of the predetermined pattern is made. Next, the glabellar insulating layer 14 is made of, for example, PaG,
8102: ll1jN4, d li'! t
Y resin 1h Rui lt Shiroki 9: CVD of Y resin
(eh fist m1eal vapord@pesmouth1・-)
If the conductive layer 1' 3 is formed of -At and the glabellar insulating layer 14 is formed of PSG, then the vertical etching process using a mixed gas of blood gas yc pct5 and CF4 is performed. A -t'' through hole 15 is formed in. With this dry etching, hpa
Not only the insulating layer a but also the film is etched at approximately the same etching speed as that of the lower layer 14PliG. By the way, this dryer.

In Chinda, the proportion of CF4tf in the mixed gas is preferably 30 to 50 moj %.

Next, a conductor layer (A4
, AjSl, AjCu, TI, Mo or W) 161 is formed on the insulating layer 14 and the exposed lower wiring 13 (FIG. 6), and is processed at the same time as through-hole formation.

Since the shape of the soldered lower wiring is similar to the outer shape of the insulating layer 14 and has a smooth slope, it is possible to obtain the upper wiring 16 with almost no disconnections or step defects. Of course, the upper and side wirings are made by photo-etching the conductive layer into a predetermined I4 turn shape.

According to the present invention, in order to make the processing speeds of the lower wiring and the interlayer insulating layer the same, it is necessary to combine the materials constituting each (for example, AA81 wiring and 5to2 insulation layer, M(1 wiring and The composition of the etching gas or etching solution is appropriate depending on the Si!N4 insulating layer).

[Brief explanation of drawings]

1 and 2 are schematic partial cross-sectional views of a semiconductor device illustrating a method of forming a multilayer wiring layer using conventional dry etching. FIGS. 5 and 6 are schematic partial cross-sectional views of a semiconductor device illustrating a method for forming a multilayer interconnection layer according to the present invention, and FIGS. FIG. j-= interlayer insulating layer, 2... through hole, S-h side arrangement, 4-... step, f defect, 5... lower wiring, 6...
. . . Semiconductor substrate, 11 . . . Semiconductor substrate, 13-. Lower wiring, 14 . Patent Applicant: Fujitsu Limited Patent Attorney: Akira Aoki, Patent Attorney: Kazuyuki Nishidate, Patent Attorney: Yukio Uchida, Patent Attorney: Shoyuki Yamaguchi Figure 1 Figure 2 Figure 30 5 Semi-4th

Claims (1)

[Scope of Claims] 1. A method for forming a multilayer interconnection layer of a semiconductor device, which includes forming a rounded through hole connecting a lower wiring and an upper wiring in an insulating layer between the eyebrows, and tinkering. The etching gas is applied to the interlayer insulating layer, the etching speed and the lower! A method for forming a multilayer wiring layer, characterized in that the etching speed of the wiring is approximately equal to #1, and the formation method is performed using a chinder, 52. The lower wiring is thick and thick, and the interlayer insulating layer is P2O. Sometimes 95. 7. Add chloride gas to etching gas. Nine dryers using mixed gas with compound gas,
2. The method according to claim 1, wherein the tinging treatment is performed to remove buttock mold. 3. The chloride gas is PCl3, and the chloride gas is
The compound gas is CF4 and its ratio is 10 to 90
Claims characterized in that mot-gg
The method described in Section 2. 4. The lower wiring is wrong! , when f is P and the interlayer insulating layer is P2O, 1, phosphoric acid,
1. The method according to claim 1, wherein a weight etching process is carried out using a mixed solution of ammonium oxide and nitric acid.