JPS58218092A - Information processor - Google Patents

Abstract

PURPOSE:To attain correct reflection of a reference bit and to reduce the access load to a reference/revision bit, by providing a reference bit access address array storing an effective indicating bit whether an address accessing the reference bit is effective or ineffective corresponding to each of entry. CONSTITUTION:A reference bit revise request flip-flop 12 is brought to ''1'' in case of access to a main storage page of new referencing, even if the effective display flag in the entry read out from an addressed address array is ''0'' or ''1'', when the comparison between a high-order bit of an address array index address register 9 and a page address high-order bit in the entry is dissident, and the reference bit revise page address is set to a register 13 at the same time and transmitted to a reference bit control section 14. Further, a low-order bit of the register 13 is addressed at a selection circuit 10, the content of the high-order bit of the register 13 is brought to the effective display flag ''1'', preparing for the same page access succeeding to wirte.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information processing apparatus with improved paging operation in a virtual storage system.

Conventional technology In a conventional information processing device that employs a virtual memory method, a reference bit is provided in the main memory or other storage devices, and
When accessing these storage devices, the reference bit is set to “1”.
” to indicate that it was accessed.

Therefore, the performance of the reference bit deteriorates due to increased access to the main memory and the upper memory.

Also, if the reference bit resides in another storage device,
This method has the disadvantage that expensive memory must be used because the reference bits must be updated at high speed.

Another method is to stop updating the reference bits corresponding to the area if there are reference bits in the high-speed buffer memory, and update the reference bits only when loading data from the main memory to the high-speed buffer memory. be. In this method, when a reference hit clear command is issued to the area at the edge of loading data into the high-speed buffer memory, the corresponding reference bit becomes "0". However, since the area is registered in the high-speed buffer memory, the reference bits are not updated when the area is referenced, and the main memory reference status is not correctly reflected in the reference bits, resulting in an increase in paging overhead.

OBJECTS OF THE INVENTION □-□ An object of the present invention is to provide an information processing device that eliminates the above-mentioned drawbacks.

Configuring the Invention The device of the present invention is an information processing device having reference bits corresponding to page storage areas of a main storage device having a configuration in which the storage area is divided into a plurality of pages. a reference bit access address array that has a plurality of entries prepared for each entry and stores addresses for accessing the reference bits corresponding to each of these entries and a validity indicating bit indicating whether each of these addresses is valid or invalid; It is characterized by having the following.

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a central processing unit 1. Request light device 4. and connected to the main storage device 5,
High-speed buffer memory control unit 2. Main' 1. Memory access address register 3. Main memory access address stack 6, selection circuit 7. Address array index address register 99 selection circuit 10. Reference bit access address array8. Comparison circuit 11° Reference bit update request flip-flop 12. Register 13. Flip-flop15. and a reference bit management section 14. Details of the high-speed buffer memory control unit 2 can be found in the VO of the publication "Information Processing" published by the Information Processing Society of Japan in 1980.
L.

You can refer to the paper published under the title "Cache Memory" on pages 332 to 340 of page 21 of page 4.

Next, the operation of this embodiment will be explained in detail.

The main memory access address from the central processing unit 1 is given to the high speed buffer memory control section 2 and the main memory access address register 3. If there is a hit in the high-speed buffer memory, the data is returned to the request source 4, and if there is a miss, a block load request is issued to the main storage device 5.

A main memory paging unit address (byte address 2 or byte address 4) is set in the main memory access address register 3 and stacked on the main memory access address stack 6. Selection circuit 75 A circuit that selects addresses from the main memory access address register 3 and the main memory address stack 6. Only when the main memory address stack 6 is empty, the address from the main memory address register 3 is bypassed and referenced. Set in address array index address register 9 for indexing bit access address array 8. The reference bit access address array 8 is composed of a set-unchanged address array, and the lower bits of the address array index address register 9 are used as the reference bit access array 8 .

is addressed through the selection circuit 10. The reference bit access address array 8 has a plurality of entries, and each entry has the upper bits of the reference page address and a flag bit indicating whether or not the page reference address is valid.

First, the case of accessing the main memory page of the reference cylinder will be explained. As described above, the main memory access page address is selected by the selection circuit 7 from either the main memory access register 3 or the main memory access address stack 6.
The address array index address register 9 is set through the address array index address register 9. The lower bits of the core address register 9 address the reference bit access address array 8 through the selection circuit 1°. The intra-entry valid display flag successively output from the address array is "1", and a comparison circuit 11 compares the upper bits of the address array index address register 9 with the upper bits of the intra-entry page address. When a match is detected, the reference bit update request flip-flop 12 is set to "0#" and no reference bit update request is generated.

Next, the case of accessing the main memory page for new reference will be explained. The operation until the reference bit access address array 8 is indexed is the same as in the above case, and the valid display flag in the read entry in the addressed address array is "0" but is not "1"f47". If the result of the comparison between the high-order bits of the star 9 and the high-order bits of the internal page address does not match, the reference bit update request flip-flop 12 is set to "1#" and at the same time the reference bit update page is set to "1#". The address is set in the register 13 and sent to the reference bit management section 14. After that, in order to register the new reference main memory page address of the register 3 in the reference bit access address array 8, the lower bit of the register 3 is addressed by the selection circuit 10, and the contents of the upper bit of the register 3 are set to the valid display flag. 1
” to prepare for subsequent access to the same page.

Next, the execution of the reference bit clear instruction will be explained. The index of the reference bit access address array 8 is the same as in the above two examples, but in the case of a reference bit clear instruction, each address register 3.6, 7.9 and 13 has a flag bit that is a clear address. The clear flag bit indicating that this is different from normal reference is set to "1". The index result of the reference bit access address array 8 is registered in a valid database:
・.

and flip-flop 1''5 are set, the address array 8 is addressed through the same path as for registering a new main memory page, and the entry in the address array 8 is cleared by the flip-flop 15 (resetting the valid display flag bit). Instruct to invalidate the entry, and
A reference bit clear request is issued to the reference bit management unit 14.

In the embodiment of the present invention, Lebel's set anonymous method is used for the reference bit access address array, but it is also possible to similarly increase the level or use a full anti-event method. The included examples do not contradict the essence of the present invention.

Effects of the Invention The present invention has the effect of correctly reflecting the reference bits that play an important role in paging in a virtual storage system and reducing the load of accessing the reference/update bits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1... central processing unit, 2...
...High-speed buffer memory control unit, 3... Main memory access address register, 4... Group/request source, 5...
Main memory device, 6...Main memory access address stack, 7゜10...Selection circuit, 8.Old...
・-Target pit access 7th array, 9... Address array index address register, 11... Hole plate, 12. Old... Reference bit update request flip-flop,
13... Reference bit update/clear page address register, 14... Reference bit management section, 15
...Reference bit clear request flip-flop.

Claims (1)

[Claims] 1. In an information processing device having a reference bit corresponding to a page storage area of a main storage device having a configuration in which the storage area is divided into a plurality of pages, A reference bit access address array having a plurality of prepared entries and storing an address for accessing the reference bit corresponding to each of these entries and a validity indicating bit indicating whether each of these addresses is valid or invalid. An information processing device characterized by: 2. Instructing the execution of an instruction to reset the reference bit to reset the reference bit, and matching the reference bit access address given from the outside with the address stored in the reference bit access address array. 2. The information processing apparatus according to claim 1, wherein a validity indicating bit stored in said entry is displayed as invalid.