JPS58219657A - Storage device - Google Patents

Abstract

PURPOSE:To shorten the duration of a wait state and to improve ability in processing, by reducing the contention occurring to a storage device requested for read and write by plural processors. CONSTITUTION:When the processors 10, 20, and 30 send requests to write to storage modules 13, 23, and 33, the contents of storage modules 21, 32, 12, and 11 permitted only to be read are rewritten into the same value through control circuits 16, 26, and 36. Then, the contents of all addresses of the storage modules are set to an initial value. Then, the processors 10, 20, and 30 carry on individual processing. If a request to write is generated during the processing, the modules 13, 23, and 33 permitted to be written and the modules 21, 32, 12, and 11 permitted only to be written have the same contents. Consequently, the processor 10 sends a request to read to the module 12 to request a read of the storage device 23 of the processor 20 without causing any contention.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device that allows a plurality of processing units to be relatively tightly coupled in order to improve overall processing performance.

Conventional techniques for relatively tightly coupling a processing device and a storage device include the following.

(1) As shown in Figure 1 (,) of the channel connector, processing units H, ,
1M1. The set of M, is the channel C)l, , CH.

This is a method that is combined by When a processing device H1 or Hl reads or writes to its own storage device M1 or M2, it uses channels CH1 or CH.

or other processing devices or storage devices. When a certain processing device H1 or H1 reads or writes to a storage device belonging to another processing device, it does so indirectly via the channel CH or CH by an input/output command.

The disadvantage of this approach is that coupling multiple processing units and storage devices creates contention for the channels and storage devices with their own and other processing devices' read and write operations.

(2) Bus-coupled type As shown in FIG. 1(b), a plurality of processing units flH,,H, and a single or plural storage device M are provided on a single or multiple buses B.
, , M, are combined. Processing equipment [H,,H
, reads and writes to and from storage devices M and +Ml via bus B.

The disadvantage of this method is that there are multiple processing devices H,,H.

This results in contention on the bus date and storage device M, , M, due to.

(3) Multi-Boat Connection Type As shown in Fig. 1(c), a method in which a plurality of entry/exit ports (boats) P for reading/writing the processing units H, , H and storage devices M, , , M are interconnected. It is.

This method is physically and economically limited in the number of bauds, and is not suitable for combining a large number of processing units and storage devices. Also, contention occurs in the storage device by multiple processing devices.

A co-proceeding drawback of each of the coupling schemes described above is that read and write requests from competing requests by multiple processing units on a storage device create a queue. The processing device waits until the storage device accepts the request and completes its operation.

If the number of waiting states increases, the overall processing capacity cannot be improved even if multiple processing devices are combined.

As a method for reducing contention in storage devices, there is an improved multi-board memory using the combination method (3) above. This storage device has a plurality of ports that accept requests, and consists of storage modules equal in number to the number of ports whose contents are always kept the same. For read requests, each storage module operates independently, so no contention occurs. However, in response to a write request, a write operation is performed on all storage modules at once in order to ensure that the contents of all storage modules match. When write requests are issued by a plurality of processing devices, there is a disadvantage that contention occurs in the storage device.

The present invention has been made in view of the above-mentioned points, and by reducing contention that occurs in a storage device where read and write operations are required from a plurality of processing units,
This is intended to improve the overall processing capacity by reducing the rate at which the processing device falls into a waiting state. This invention will be explained below.

FIG. 2 is a block diagram for explaining the invention in detail. In FIG. 2, reference numerals 10, 20, and 30 are processing units, and IL 12, 21, 22, and 31° 32 are storage modules that accept only requests for read operations from each of the processing units 10, 29, and 30, respectively. , 13.23, and 33 are storage modules that accept requests for read and write operations from each of the processing units 10, 20, and 30; 15
．． 24.25.34.35 are storage module control circuits paired with the storage monolayers 11.12.21.22.31.32, respectively; 16. 26. 3''6 are storage module control circuits paired with the storage modules 13, 23, and 33, respectively.

As described above, the present invention includes a storage module 13 that receives requests for read and write operations from a processing device 110.
and a storage module control circuit 16 that sends out information corresponding to the write operation request, and a plurality of storage modules 1 that only accept read operation requests from the processing device 10.
1.12 and the storage module control circuits 14 and 15 that rewrite the contents of the storage module 11.12 based on information sent from other storage module control circuits, and prepare as many of these as required. The memory module control circuits are interconnected to each other. Here, the information corresponding to the write operation request mainly includes the memory address and the content to be written.

In the storage device of the present invention, for example, a storage module 13, which accepts requests for read and write operations, and a storage module control circuit 16, which sends out information corresponding to requests for write operations, are paired together. Furthermore, a storage module 11.12 that accepts only requests for read operations and a storage module I11 control circuit 14.15 that rewrites the contents of the storage module 11.12d are also paired. There may be any number of storage modules, such as 11, 12, etc., to which one processing device 10 can directly issue a request for a read operation.

Next, regarding the operation of each part of each storage device, the processing device 1
The relationship of 0 will be mainly explained.

The processing device 10 sends a request for a read operation to the storage module 1.
It can be issued against 1.12.13. On the other hand, a request for a write operation can be issued only to the storage module 13. When the processing device 10 requests a write operation to the storage module 13, the storage module control circuit 16 of the processing device 10 unilaterally writes information in conjunction with the request, regardless of the state of the storage module control circuit 24.35. Send. Storage module control circuit 14゜1
5 receives information from a storage module control circuit 36.26 connected to a storage module that is permitted to accept requests for write operations belonging to other processing devices, and uses the information to control the contents of the storage module LL12. rewrite.

The storage device as a whole operates as follows.

All parts of the storage device start operating all at once from a stopped state, and immediately after the start of operation, each processing device 10, 20.30 stores a storage module 13, 23.33 to which write operations are permitted from that processing device. Assume that the initial values at all addresses are written.

Since this operation is a request for a write operation to the storage module 13.23.33, the storage module control circuit 16.28.36 (16-24°16→35,26
→15. Via 36 → 14), processing equipment 1G, 20
．． 30, the storage module 21.30 is allowed only read operations. The contents of si:12.11 are also rewritten to the same value.

When the write operation to all addresses of each processing device 10, 20""', 30 is completed, the contents of all addresses of all storage modules are set to initial values. After that, each processing device 10°20.3
Each 0 continues its own processing, but if there is a request for a write operation to the storage device during that processing, the storage device is connected to a processing device that is connected to a storage module that is allowed to write through the storage module control circuit. The contents of storage modules for which only read operations are permitted are also rewritten to the same value. That is, there is a storage module 13.23.33 that is allowed to write, and a storage module that is connected to it through the storage module control circuit 16.26.36 and that is only allowed to read.
21 and 32 for 13, 12 for 23, and 11) for 33 have exactly the same contents.

With such a configuration, when the processing device 10 needs information written in the storage module 23 of the processing device 20, it can achieve the purpose by issuing the request to the storage module 12 without requesting the storage module 23 to perform a read operation. can be achieved.

In this case, since the processing device 10 is the only device that requests a read operation from the storage module 12, no conflict occurs due to requests for read operations. Further, since the operation of the storage module control circuit 16 is influenced only by the request for a write operation to the storage module 13 of the processing device 10, the requests for read and write operations to the storage module 13 of the processing device 10 are affected by other processing devices. 20.3
Accepted regardless of 0 requests. That is, no contention occurs due to requests for read and write operations.

Another type of conflict is a conflict between a request for a rewrite operation on the storage module 11 by the storage module control circuit 14 and a request for a read operation on the storage module 11 from the processing device 10 . To deal with this, it is only necessary to arbitrate between the two requests from the storage module control circuit 14 and the resident device 10, so by increasing the operating speed of the storage module 11 to a certain extent based on statistical considerations, the influence of contention can be reduced. It is possible to reduce the

FIG. 3 is a boot rack showing an embodiment of the present invention.

In this figure, 40 is a processing device, 41 is a storage module that only accepts requests for read operations from the processing device 40, and 42 is a storage module that does not accept requests for read and write operations from the processing device 4. These 40.41°42 are storage modules, for example 10.ICl3 in FIG.
corresponds to

43.44 is a first-in first-out (FIFO) register, 4
5.46 is a serial/parallel conversion register, and 47 is a communication path connected to a storage control circuit of a storage module that accepts requests for write operations belonging to other processing devices. Then, the serial data from the communication path 47 is transferred to the serial/parallel conversion register 45.
46 and stored in registers 43 and 44.

48 and 49 are FIFO type registers, 50 and 51 are parallel-to-serial conversion registers that convert parallel data from the registers 48 and 49 into serial, and 52 is a memory that accepts only requests for read operations and operations belonging to other processing devices. Communication paths connected to the storage module control circuit of the module include an address bus 53 and a data bus 54. and address bus 53. Information from data bus 54 is transferred to register 48.
The parallel gator stored in 49 and read out therefrom is converted into serial data by parallel/serial conversion registers 50 and 51 and output to the communication path 52.

A multiplexer 55 switches the contents of the address bus 53 and the contents of the register 43.

Next, the operation will be explained.

The processing device 40 puts an address on the 7-dress bus 53 when requesting a read operation to the storage device, and puts the address on the 7-dress bus 53 and data on the data bus 54 when requesting a write operation. When the address requested for a read operation indicates the storage module 42, the storage module 42 outputs the contents of the corresponding address to the data bus 54. When an address requested for a read operation is pointing to storage module 41, if registers 43 and 44 are empty, storage module 41 outputs the contents of the corresponding address to data bus 54. If the registers 43 and 44 are empty, the storage module 41 suspends the read operation request and performs the rewriting operation until the registers 43 and 44 become empty. The address and contents of the register 44 are rewritten as data in the storage module 41.

When processing unit 40 issues a write operation to storage module 42, storage module 42
The contents of address bus 53 and data bus 54 are respectively stored in registers 48 and 49 at the same time. Parallel serial conversion registers 50 and 51 are register 4
If there is information in 8.49, it is converted into serial data and sent to the communication path 52. On the other hand, the serial/parallel conversion register 45
46 converts the serial data from the communication path 4γ into parallel data and stores them in registers 43 and 44, respectively.

The communication capacity of the communication paths 47 and 52 may be smaller than the value commensurate with the processing speed of the processing device 40. Because processing device 4
This is because 0 is a write operation to the storage device; it does not continue to request access. This means that communication channel 47.5
2. This means that it can be realized by physically and economically easy means, and is advantageous for combining a large number of processing devices. By connecting the necessary number of each element shown in FIG. 3, it is possible to create a compound computer with less contention in the storage device.

As described above in detail, the present invention provides a storage device having a plurality of processing devices, including a storage module that accepts (receives) requests for read and write operations for each processing device, and
A storage module control circuit that controls this, a plurality of storage modules that accept only requests for read operations, and a storage module control circuit that controls these are set as a set, and requests for read and write operations in a certain group are slightly postponed. Since the storage module control circuit of the storage module that accepts only requests for read operations in other groups is connected to each other, a plurality of processing devices and storage devices can be connected to each other. In this case, there is an advantage that the rate at which requests for read and write operations by the processing device compete with each other in the storage device can be reduced to a level that does not pose a practical problem, and the processing capacity of the processing device can be efficiently utilized.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (c) show various coupling methods between conventional processing devices and storage devices, FIG. 2 is a block diagram showing the principle of the present invention, and FIG. FIG. 1 is a configuration diagram showing an embodiment of the invention. In the figure, 10.20.30 is a processing device, 11.12°21
．． 22.31.32 is a storage module that accepts only read operation requests; 13.23.33 is a storage module that accepts read and write operation requests; 14-
16.24-26.34-36 are storage module control circuits.

Claims (1)

[Claims] In a storage device in which read and write operations are requested from a plurality of processing devices, a storage module that accepts requests for read and write operations from the processing devices and sends information corresponding to requests for write operations to this storage module. A storage module control circuit for controlling a plurality of storage modules, a plurality of storage modules that accept only requests for read operations from the processing device, and a storage module control circuit for controlling these plurality of storage modules are set as one set, and the number of storage modules is equal to the number of processing devices. further comprising interconnecting a storage module control circuit of a storage module that accepts requests for read and write operations in one group and a storage module control circuit of a storage module that accepts only requests for read operations in another group. Characteristic storage device.