JPS5827285A - Pattern outputting system - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a pattern generating circuit by providing a printer controlling device with a pattern generating circuit and enabling the pattern generating circuit to be used by plural printers. CONSTITUTION:A printer controlling device 50 is provided with an I/O interface part 51, a serial interface controlling part 52, a character pattern generating circuit 53, and serial interface parts 54, 55. The serial interface controlling part 52 controls the selection of the serial interface parts 54, 55 and the reading of the character pattern generating circuit 53 and transmits with the printer 60. The character pattern generating circuit 53 is a memory storing all character patterns used for the printing by a printer 60. The serial interface part 54 is an interface between the printer controlling device 50 and the printer 60 and converts parallel data into serial ones. The serial interface part 55 is an interface with other output devices and operates in the same manner as the serial interface part 54.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern output method, and more specifically, converts code data such as a character code supplied from a host device into pattern data such as a character pattern,
The present invention relates to a pattern output method for outputting a pattern using an output device such as a printer.

Figure 1 is a block diagram of the conventional pattern output method.
In the figure, 10 is a host device, 11 is a data bus of the host device, 1 is a printer control device, and 1 is a printer device.

The host device 10 is a device that encodes and supplies character data and control data to the printer control bag f20 via the data bus 11.

The printer control device side includes an I10 interface section 21 and a serial ink face section 22.

The I10 interface section 21 is an interface with the host device 10, and performs input/output data buffering, timing control, etc.

The serial interface section n is an interface with the printer device (g) and converts parallel data into serial data.

The printer device (to) has a serial interface 7/8 section 31,
It is equipped with a CPiJ 32, a control memory 33, a character code buffer, a character pattern generation circuit 35, a print control section 36, an internal bus 37, and a printing mechanism section side.

The serial interface section 31 is an interface with the printer control device, and is configured to hold serial data supplied from the printer control device and output it as parallel data.

The CPU 32 controls the printer device (9).

The control memory 33 is a memory in which a program for controlling printer devices is stored.

Character code buffer A is a buffer that holds one line of character code supplied from the printer control device side.

The character pattern generation circuit 35 is a memory in which all character patterns that can be printed by the printer 4fc station 30 are stored, and is accessed by character codes stored in the character code buffer 34.

The character pattern generation circuit may be configured with a read-only memory or a read/write memory.

The print control section performs line feed control and other controls for the printing mechanism section 38.

A dot printer is installed between the printing mechanisms.

Next, the operation will be explained.

A character code for one character is supplied from the post device 10 to the I10 interface unit 21 via the data bus 11.

This character code is converted into a digital serial code by the serial interface section 22 and supplied to the serial interface section.

The character code supplied as a serial code to the serial ink face section 33 is held in the serial interface section 33 in a parallel state.

The character code held in the serial interface section is read by the CPU 32 and stored at the leading address of the character code buffer.

Subsequently, the CPU 32 sends the receiving operation completion status to the host device 10 via the serial interface section 3, serial interface section 22-I10 interface section 21, and data bus 11.

The host device 10 learns from the receiving operation completion status that the first character code has been received by the printer device (g), and as a result, the next character code is output from the host device 10 to the data bus 11, and the following Similarly, character codes for one line are sequentially stored in a character code buffer.

Also, each time a character code is stored in the character code buffer 34, a receiving operation completion status is supplied to the host device 1().

When the host device 10 learns from the receiving operation end status that all character codes for one line have been accepted by the printer device (9), the host device 10 outputs a print start command.

This print start command is also coded and supplied to the printer device 30 in the same manner as the previous character code.

When the CPU 30 reads out the print start command from the serial interface section 1, it starts executing the print operation.

First, a character code is read from the first address of the character code buffer, and a character pattern is read from the character pattern generation circuit 35 using this character code as an address.

The read character pattern is supplied between the print control units via the internal bus 37.

The print control unit 36 controls the print mechanism unit 37 to output a character pattern.

However, such a pattern output method has the following drawbacks.

First, it is well known that when dealing with kanji patterns, the number of bits per character is extremely large and there are many types of characters, so the pattern generation circuit becomes large and expensive.

In the case of the conventional method, in order for the host device to control many printer devices, a character pattern generation circuit must be prepared for each printer device, which increases costs.

(2) Furthermore, if the character pattern generation circuit is configured with a read/write memory, the load on the post device increases because the host device supports the replacement of the contents of the same number of character pattern generation circuits as the number of printer devices.

The present invention has been made in view of these shortcomings, and is capable of generating patterns by providing a pattern generation circuit in a printer control device and making it possible for a plurality of printer devices to share this pattern generation circuit. The first objective is to improve circuit usage efficiency and thereby reduce costs. Furthermore, a second object of the present invention is to reduce the burden on the host device in managing the pattern generation circuit when the pattern generation circuit is configured with a read/write memory.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention, in which reference numeral 40 indicates a host device, 41 indicates a data bus of the post device 4o, reference numeral indicates a printer control device, and numeral 60 indicates a printer device.

The host device 140 is a device that supplies encoded character data and control data to the printer control unit w5o via the data bus 41.

The printer control device 5) has an I10 interface section 51,
It includes a serial interface control section 52, a character pattern generation circuit 53, and a serial ink face section 55.

The I10 interface unit 51 is an interface with the host device [40], and performs input/output data buffering, timing control, etc.

7- The serial interface control section 52 is for controlling the selection of the serial interface sections 54 and 55, controlling the reading of the character pattern generation circuit 53, and communicating with the printer device.

The character pattern generation circuit 53 is a memory that stores all the character patterns that can be printed by the printer device 60, and may be configured with a read-only memory or a read/write memory. Note that if the character pattern generation circuit 53 is constituted by a read/write memory, its contents must be prepared in advance by the host device 4°.

The serial interface section is an interface with the printer device 60 and converts parallel data into serial data.

The serial interface section 55 is an interface with another output device (not shown), and is similar to the serial interface section 54.

The printer W60 has a serial ink face section 61, C.
PU62, control memory 63, character code buffer 64,
It is equipped with a character pattern buffer 65, a print control section, an internal bus 67, and a print mechanism section 68.

The serial ink face section 61 is an ink face between printer control devices, and is configured to hold serial data supplied from the printer control device and output it as parallel data.

The CPU 62 controls the printer device (a).

The control memory is a memory in which 63 programs for controlling the printer device are stored.

The character code buffer 64 is a buffer that holds one line of character codes supplied from between printer control devices.

The character pattern buffer 65 is a buffer that holds one line of character patterns supplied from the printer control device 50, and the address of the character pattern buffer 65 corresponds to the address of the character code buffer 65 on a one-to-one basis.

The print control unit 66 performs line feed control and other controls for the print mechanism unit 68.

The printing mechanism section 68 is equipped with a dot printer.

Next, the operation will be explained.

A character code for one character is supplied from the host device 40 to the I10 interface section 51 via the data bus 41.

This character code is read by the serial interface control section 52, converted into a serial pen by the serial ink face section 61
is supplied to

The character code supplied as a serial code to the serial interface section 61 is held in the serial interface section 61 in a parallel state.

The character code held in the serial interface unit 61 is read out by the CPU 62 and stored at the leading address of the 5-character code buffer 64.

Next, a character pattern transfer request is issued from the CPU 62,
This character pattern transfer request is supplied to the printer control device 50 via the serial interface unit 61.

As a result, the character pattern corresponding to the character code currently supplied to the printer device ω is read out from the character pattern generation circuit 53.

This character pattern is converted into a serial pattern by the serial interface section 61 and supplied to the serial interface section 61.

The character pattern supplied to the serial interface section 61 as a serial pattern is held in the serial interface section 61 in a parallel state.

The character pattern held in the serial interface section 61 is read out by the CPU 62 and stored at the leading address of the character pattern buffer 65.

Next, the CPU 62 outputs the receiving operation completion status, and
The receiving operation completion status is transmitted to the host device via the printer control unit.

The host device 10 then begins the next character code transfer operation.

Similarly, the character code for one line is set to post device 40.
The character code for one line is sequentially supplied to the I10 control unit 50, and the character code for one line is sequentially stored in the character code buffer 64, and the character pattern for one line is sequentially stored in the character pattern buffer rhyme.

When the last character pattern for one line was stored in the character pattern buffer, all character codes and character patterns for one line were given to the printer according to the receiving operation completion status sent from the printer. When the host device 40 learns of this, a print start command is output from the host device button.

This print start command is also supplied to the printer device mark in the same manner as the previous character code.

The CPU 62 sends a print start command to the serial interface 6.
When reading from 1, execution of the printing operation starts.

First, a character code is read from the first address of character code buffer B.

Some pits in the character code are defined as control pits, and control information indicated by the control pits is given to the print control unit 66 via the internal bus 67.

Next, a character pattern is read from the top address of the character pattern buffer 65, and the read character pattern is supplied to the print control unit 66 via the internal bus 67.

The print control section 66 controls the printing mechanism section based on the control information in the character code to output a character pattern.

Thereafter, character patterns for one line are output in the same manner.

When all character patterns for one line have been output, a print operation end status is output from the CPU 62, and the host device starts outputting the character code for the second line.

Note that although the example in which only one printer device is connected is shown above, the internal bus 5 (5) of the printer control unit Nt50 is
By connecting n serial interface units to the printer, it becomes possible to connect n printer devices.

Further, although the above example uses a printer device as an example of the output device, it is possible to connect any device other than the printer device as long as it uses a similar character pattern.

Further, although an example in which only character patterns are handled has been described above, it is natural that other patterns can be handled as well.

Furthermore, although the above description has been made on the assumption that the post device monitors the status of the printer device, an interrupt method may also be used.

As explained above, according to the present invention, the pattern generation circuit provided in the printer control device, that is, the output control device, can be shared by a plurality of output devices. This will result in significant cost reductions.

Furthermore, when the pattern generation circuit is composed of read/write memory, the host device only needs to support the contents of the second pattern generation circuit regardless of the number of output devices, so the burden on the host device is greatly reduced. Ru.

In addition, in the case of the present invention, although the transmission efficiency between the output control device and the output device decreases, it is sufficiently fast when compared with the speed of mechanical parts such as the printing mechanism section, so it is There is no influence at all.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional pattern output method. FIG. 2 is a block diagram of the pattern output method of the present invention. 40...Host device 50...Printer control device 51...I10 interface section 52...Serial interface control section 53...Character pattern generation circuit word 055.61...Serial interface ω.・・・
Printer device 62...CP U63...Control memory 64...Character code buffer 65...Character pattern buffer Close...Print control section...Printing mechanism Patent applicant Tokyo Shibaura Electric Co., Ltd. Agent Person Patent Attorney Noriyuki Chika (11! 1 person)

Claims (1)

[Scope of Claims] (]) Consisting of a host device, an output control device to which parallel data is supplied from the post device, and an output device to which serial data is supplied from the output control device, the output control from the host device In a pattern output method that converts code data supplied to the device into pattern data and outputs a pattern, the output control device includes a pattern generation circuit from which pattern data corresponding to the supplied code data is read out, and the host A pattern output method characterized in that pattern data read out from the pattern generation circuit is supplied to the output device according to code data supplied from the device. (2. The pattern output method according to claim 1, wherein the pattern generation circuit is constituted by a read/write memory that can be rewritten by the host device. (3) ) A pattern output method according to claim 1 or 2, characterized in that a plurality of output devices are interfaced to the output control device.