JPS5827698B2 - Multilevel signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilevel signal generating device that generates a signal having a plurality of potential levels.

In recent years, low power consumption liquid crystal display elements have been used in display parts of electronic calculators, electronic watches, and the like.

There are two ways to drive the liquid crystal: a direct current drive method and an alternating current drive method.However, although the drive circuit is simple in the direct current drive method, the lifespan of the liquid crystal is short at approximately 100 to 1000 hours, and for this reason, conventional An alternating current drive method is generally used, which can extend the life of liquid crystals by about 10 times or more than a direct current drive method.

When a liquid crystal is driven by this AC 1 driving method, a signal having multiple potential levels of three or more values is used as a digit pulse for selecting each display digit, as shown in FIG. 1a or 2a, for example. A multilevel signal is required.

When using the digit pulse shown in FIG. 1a above, suppose that the liquid crystal lights up when a potential difference of 3 cm is applied between the electrodes, but does not light up when a potential difference of 1 cm is applied between the electrodes.
+V is applied to the non-selected segment of the liquid crystal as shown in Figure 1.
Give a rectangular wave signal that changes between ~-■.

As a result, the potential difference between the non-selected electrodes changes between +V and -■ as shown in FIG. 1C, assuming that the non-selected segment potential in FIG. 1 is used as a reference.

On the other hand, the selected segment is given a rectangular wave signal shown in FIG. 1d that changes between +■ and ■.

As a result, the potential difference between the selected electrodes is +3V to -3V, as shown in Figure 1e, considering the potential of the selected segment as a reference.
It changes between ■, and the wave height value +3■ and -3■
At this point, the selected segment becomes lit.

When using the digit pulse shown in FIG. 2a, a rectangular wave signal varying between the ground potential (GND) and 3cm is applied to the unselected segment of the liquid crystal, for example, as shown in FIG.

As a result, the potential difference between the non-selected electrodes changes between +V and -■ as shown in FIG. 2C, and the non-selected segments are not lit.

Then, a signal varying between the ground potential and 3cm is applied to the selected segment, as shown in FIG. 2d, for example.

As a result, the potential difference between the selection electrodes is +
The voltage changes between 3V and -3■, and the selected segment becomes lit at the peak values of +3■ and -3■.

Figures 1 and 2 show, as an example, a signal waveform for one of the three digits displayed.

As described above, a display device using a liquid crystal requires a multi-value signal, but in the past, the multi-value signal could not be easily obtained and required a very complicated circuit.

The present invention has been made in view of the above points, and is a multi-value signal generator capable of obtaining an arbitrary multi-value signal with a simple circuit configuration that switches different potentials that are periodically and repeatedly output at a predetermined timing. The purpose is to provide

The present invention will be described in detail below with reference to the drawings.

To explain an embodiment in which the digit pulse shown in FIG. 1a is obtained without switching, in FIG. 3, 11 is an NPN type switching transistor, 12 is a PNP type switching transistor, and both transistors ，
The 12 paces are collectively connected to the input terminal 13.

A control signal A shown in FIG. 4g is applied to this input terminal 13.

The collector of the transistor 11 is connected to the load resistor 1.
The collector of the transistor 12 is connected to the +2cm DC power supply via the load resistor 14b.
■Connected to the DC power supply.

In addition, the terminals of transistors 11 and 12 are connected together, and this collective connection point a is connected to load resistances 15, 16 and 16, respectively.
MO8 type FET (field effect transistor) through 17
Connected to drain electrodes 18, 19, and 20.

And the above FET18. The source electrodes of 19 and 20 are grounded, and each gate electrode is connected to input terminals 21 and 2, respectively.
Connected to 2 and 23.

The control signal B1 shown in FIG. 4C is input to the input terminal 21.
A control signal B2 shown in FIG. 4e is applied to the input terminal 22, and a control signal B3 shown in FIG. 4g is applied to the input terminal 23.

Further, the drain electrodes of the FETs 18, 19, and 20 are connected to output terminals 24, 25, and 26, respectively.

In the above configuration, when the control signal A shown in FIG. The OFF operation is repeated, and the output potential of the emitter changes between +2V and -2V as shown in FIG.

That is, when the potential of the control signal A is +2■, the transistor 11 is turned on and the transistor 12 is turned off, and the emitter bulk connection point a receives the +2■ power supply voltage +2■! appear.

Further, when the control signal A is 12 V, the transistor 11 is turned off and the transistor 12 is turned on, and the voltage of the power source -2■ appears at the point a.

Then, the control signal B shown in FIG. 4C is applied to the input terminal 21 while the potential at the point a is +2■.
If the potential of 1 is at the ground level, the FET 18 is turned off, and the output terminal 24 has + as shown in FIG. 4d.
A potential of 2■ appears.

Further, when the control signal B1 goes to the ground level and the FETI 8 is turned off while the potential at point a is 12cm, a potential of 12cm appears at the output terminal 24 as shown in FIG. 4d.

When the potential of the control signal B0 is equal to the threshold level 1vthl of the FET 18, the FET 18
is turned on, and the output terminal 24 becomes the ground potential regardless of the potential at point a.

Therefore, the signal output from the output terminal 24 ranges from +2V to -
The signal changes as shown in FIG. 4(d) between 2 and 3, and a waveform similar to that shown in FIG. 1(g) is obtained.

Further, the signals output from the output terminals 25 and 26 are also output in accordance with the control signals B2 and B3 as in the above case, and as shown in Fig. 4 f and h, the signals in Fig. 4 d are The waveforms are similar, only the phases are different.

That is, the signals output from the output terminals 24, 25, and 26 become digit pulses when the number of displayed digits is three.

In the above embodiment, the output section shown within the broken line in FIG.
, 16, 17 and FETs 18, 19, 20, but using an MO8 load, a pair of N-channel MO8 type FETs 31, 32 are connected in series as shown in FIG. Control signal B is applied directly to the other FET 32, and control signal B is applied to the inverter 33.
, and the output signal may be taken from the common connection point of FETs 31 and 32.

In addition, the output section is composed of a P-channel MO8 type EET34 and an N-channel MO8 type FET, as shown in Fig. 5.
The same purpose can also be achieved by using a so-called CMO8 in which 35 are connected in a complementary symmetrical manner.

Next, an embodiment in which the digit pulse shown in FIG. 2g is obtained will be described.

In FIG. 6, 41 and 42 are NPN type switching transistors, 43 and 44 are PNP type switching transistors, the bases of transistors 4143 are collectively connected to input terminal 45, and transistors 42 and 44 are connected to input terminal 45.
The paces are collectively connected to the input terminal 46.

A control signal A0 shown in FIG. 1A is applied to the input terminal 45, and a control signal A2 shown in FIG. 7A is applied to the input terminal 46.
is added.

The collector of the transistor 41 is connected to the load resistor 4.
It is connected to the +■ DC power supply through the transistor 4.
The collector of No. 3 is connected to a +2V DC power supply via a load resistor 48.

The collector of the disconnected transistor 42 is connected to a +3cm DC power supply via a load resistor 49, and the collector of the transistor 44 is grounded via a load resistor 50.

Therefore, the terminals of the transistors 41, 43 are connected together, and the MO8 type FETs 51, 52, 5 are connected at this connection point.
No. 3 drain electrodes are connected.

Further, the emitters of transistors 42 and 44 are connected together, and the source electrodes of FETs 51, 52 and 53 are connected to this connection point C via resistors 54, 55 and 56, respectively.

Control signals B1, B2, and B3 having different phases are applied to the gates of the FETs 51, 52, and 53, respectively, and source electrodes are connected to output terminals 57, 58, and 59, respectively.

In the above configuration, the transistors 41 and 43 are turned on and off in response to the control signal A1 shown in FIG.
As shown in Figure C, a potential equal to control signal A1 is generated.

The transistors 42 and 44 are turned on and off in response to the control signal A2 shown in FIG. 7A applied to the input terminal 46, and the control signal A2 shown in FIG. produces a potential equal to A2.

Now, as shown in Figure 7c and d, the potential at point b is
, in a state where the potential at point C is 3■, the FET
When the ground potential of the control signal B1 shown in FIG.

In addition, the control signal Bl becomes the Ivth potential, and the FET51
When turned on, the potential ■ at point b appears at the output terminal 57.

In this way, the potential at point b or point C appears at the output terminal 57 depending on the on/off operation of the FET 51.

Therefore, if the control signals A1 and A2 change next and the potential at point b becomes 2■ and the potential at point C becomes ground potential, the FET
51 is off, the potential of the output terminal 57 is ■
, and when the FET 51 is on, the output terminal 5
The potential at 7 is the ground potential.

In this way, the signal output from the output terminal 57 changes in a plurality of stages between the ground potential and 3■ in accordance with the control signals Al, A2, B, and the digit pulse shown in FIG. 2a. The waveform will be the same.

In addition, the signals output from the output terminals 58 and 59 are also output in accordance with the control signals B2 and B3 in the same way as in the above case, and have similar waveforms with respect to the signals shown in FIG. 7f, only with different phases. becomes.

The present invention is not limited to the above embodiments, and any multilevel signal can be obtained by changing the control signal.

Additionally, although the present invention has been described with respect to the case where a digit pulse is obtained as a driving signal for a liquid crystal, it can also be used when obtaining a segment signal, and the present invention can be used not only for liquid crystals but also in cases where multi-level signals are required. Of course, it can be implemented without departing from the gist of the invention.

Furthermore, the structure of the transistor in the embodiments of FIGS. 3 and 6 may be a MOSFET, or the structure of the MOSFET may be a transistor.

Furthermore, it goes without saying that the MOSFET and transistor may be of P type or N type.

As described above, according to the present invention, at least one of the first and second color values is selected and outputted one by one in accordance with a control signal having a constant cycle, and furthermore, the first color value and the second color value are selected and outputted at a time of a predetermined cycle. 1. Since a multi-value signal having a potential between the second potential values is obtained, it is possible to provide a multi-value signal generating device that can generate a desired multi-value signal with an extremely simple circuit configuration. be.

Furthermore, since the multi-level signal generating device uses MOS-FETs as transistors, it can be realized with a simple circuit configuration and is suitable for being incorporated into an LSI.

[Brief explanation of drawings]

1 and 2 are signal waveform diagrams for driving the liquid crystal 1, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is an operating signal waveform diagram for explaining the operation of the embodiment. , FIGS. 5a and 5b are circuit diagrams showing main parts of other embodiments of the present invention, and FIG.
The figure is a circuit diagram showing still another embodiment of the present invention, and FIG. 7 is an operation signal waveform diagram for explaining the operation of the embodiment. 11.12...Transistor, 13,21-2
3...Input terminal, 18-20...MO
8 type FET, 24-26...output terminal, 31.3
234.35,55...MO8 type FET, 41
゜44...transistor, 45,46...
...Input terminal, 57-59...Output terminal.

Claims (1)

[Claims] 1 Formed by at least one MOS-FET, connected to at least a first and second potential source, and selectively outputs potential values obtained from the potential sources one by one in response to a control signal having a constant period. and means formed of a MOS-FET for switching the potential value obtained by the means at a predetermined cycle timing to obtain a multi-value signal having a potential between the first and second potential values. A multilevel signal generator characterized by: