JPS582941A - Code generator - Google Patents

Abstract

PURPOSE:To take out a required code with a simple constitution, by storing plural bit random codes and etc. in a ROM and selecting outputs of the ROM. CONSTITUTION:A ROM2 where bit random codes different in bit and repeat period marks are stored is driven by the output of an address counter 1. A selector 3 selects outputs of the ROM2 and selects the signal of the n-th bit of the counter 1, and the output of the ROM2 and the output of the selector 3 are inputted to an AND gate 4. A timing signal which operates the counter 1 periodically is taken out from the gate 4 and is applied to the counter to take out code data stored in the ROM2. Thus, an optional code is taken out by the exchange of ROMs, and a testing pattern of data transmission lines is switched without a switching circuit.

Description

[Detailed Description of the Invention] This invention was originally published by 1Il1, multiple bit random codes, etc.
Kx9 stores the code in OM and selects the ROM output, which is related to the code generation circuit that extracts the required code.

For testing data transmission lines, a 511-bit test pattern tw! is required according to CCITT Recommendation V52. In addition to using 2
Several types of random codes such as 047 bits are often used.

The 511-bit test pattern uses a 9-stage shift register, as shown in the circuit example in Figure 1, and the 5th and 9th stages are
It is obtained by adding the outputs of the stages to an exclusive OR circuit and feeding the result back to the input of the first stage.

Other random code patterns can be obtained with a similar configuration, but in this case the position of the feedback output to be expanded is different from that for 511 bits, so if a shift register is shared, a switching circuit is required.Table 9. There is a problem that the configuration becomes complicated.

In this invention, these O random codes etc. are
These codes are written in the OM and read out, allowing the user to learn the types of random codes simply by changing the contents of the ROM.

A configuration diagram of an embodiment based on this issuing WAK is shown in FIG.

In the figure, 1 is the address counter, 2 is the address counter 1
3 is a selector that selects the output of ROM 2 and also selects the n-th bit signal of address counter 1. 4 is a selector that uses the output of selector 30 and the output of ROM 2 as input, and periodically controls address counter 1. This is a gate that takes out a timing signal to operate the device.

The ROM 2 stores, for example, the following codes.

0 bit = 2047 bit random code (first half) 1 bit = 2047 bit random code (il half) 2 bits = 511 bits random code 5 bits = repeated periodic symbol This inventor writes a random code for each bit like this Select the output of ROM2 and press the desired code tab
It was designed to be released. , storage in ROM2 is to store the generated code on the data line and the repetition period t of the generated code.
Allocate one piece of data IIK. By storing the generation code and the repetition period code in separate ROMs, any pattern can be generated.

This relationship 1 is shown in FIG. S. FIG. 5, 7, is a clock pulse to the address counter 1, and FIG.

In the third diagram, the data outputs Do to D of the ROM2 enter the selector 3 (9), and in the fifth diagram, the output D4 of the ROM2 enters the gate 4. That is, only one bit of the output of the ROM2 is stored as shown in Figure 5 in the data tube for repetition period, and the gate 4t is operated by the switching signal to the selector 5.
The outputs Do to D5 are taken out as output signals.

As described above, according to the present invention, any code can be retrieved by exchanging the ROM. As a result, test patterns for data transmission lines can be replaced without a switching circuit.

[Brief explanation of the drawing]

Figure 1 shows a conventional 511 test pattern generator, Figure 2 is a block diagram of an embodiment of the present invention, and Figure 3 shows a
An explanatory diagram of each part of the figure. 1...Address counter, 2...RO
M, 3...Serebuta, 4...Kate. Agent: Patent Attorney Kinji Omata Diagram 1 Procedural Amendment (Method) December 7, 1980 Haruki Shimada, Commissioner of the Japan Patent Office 1, Indication of the Case 1980 Patent Application No. 100992 2, Invention Name Code Generator 3 , Relationship with the case of the person making the amendment Patent Applicant Address: 4-19-7 Kamata, Ota-ku, Tokyo Name: Ando Electric Co., Ltd. Representative: Shun Oshiro - 4, Agent: 144 Address: 4, Kamata, Ota-ku, Tokyo No. 19-7 No. 6, number of inventions increased by amendment 0a Contents of the amendment (11 [Title of the invention: Code generator] on the second line of the first page of the specification. "Title of the invention: Code generator") Correct. <2) Change “Generation circuit” in the third line of the second page of the specification to “
Generator”.

Claims (1)

[Scope of Claims] t: an address counter; a ROM that operates with the output of this address counter; a selector that selects the ROM output and also selects the n-th bit signal of the address counter; a gate that takes the ROM output as an input and outputs a tying signal for periodically operating the address counter;
The code relaxer stores code data in the other bits of M, and the code data stored in the ROM is activated by a switching signal to the selector.