JPS583009A - Electric power supply controller of data processor - Google Patents
Electric power supply controller of data processorInfo
- Publication number
- JPS583009A JPS583009A JP56101931A JP10193181A JPS583009A JP S583009 A JPS583009 A JP S583009A JP 56101931 A JP56101931 A JP 56101931A JP 10193181 A JP10193181 A JP 10193181A JP S583009 A JPS583009 A JP S583009A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- electric power
- processing
- power
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は消費電力の低減を図るコンビ、−タ。[Detailed description of the invention] The present invention is a combination device that reduces power consumption.
制御回路、シーケンサ等における電力制御装置に関する
ものである。The present invention relates to power control devices in control circuits, sequencers, etc.
−ffに、コンビ、−夕等においては、常時10011
の処理負荷が加わることはなく、通常のリアルタイム処
理(即時的処理)では平均負荷が5〜30%程度となっ
ている。この処理負荷が1001で危いことを利用して
、その残りのアイドル時(待合せ時)に不用な時間の電
源を断として低電力化を図るパワーストローブ方式があ
る。-ff, combination, -evening, etc., always 10011
There is no additional processing load, and in normal real-time processing (immediate processing), the average load is about 5 to 30%. There is a power strobe method that takes advantage of the fact that the processing load is dangerous at 1001 and cuts off the power during unnecessary times during the remaining idle time (meeting time) to reduce power consumption.
従来、この種の低電力化方式としては、アイドル時の消
費電力を削減するためにインターバルタイマ信号により
電源t−0N10FF L、て低電力化を計ゐ方式が
用いられている。しかし、この場合電源tON10FF
する時間はタイマーの外部信号周期で固定されてい
たので、全ての処理をその周期内に終了しなければなら
ないというソフトウェアに対する時間的制約が大きく、
また、ランダムに処理要求が発生するように、処理時間
が同一でない非同期的な処理形態t−敗扱うことができ
なかった。すなわち、この方式はある一定の処1シーケ
ンスを!IAI/c追って行く様な定形的処理にのみ適
用され、処理要求が発生した時点でその優先度に応じた
処mt−行なうような複雑な即時処理には適用できなか
りた。Conventionally, as this type of power saving method, a method has been used in which power is reduced by using an interval timer signal to reduce power consumption during idle time. However, in this case, the power supply tON10FF
Since the time to do this was fixed by the timer's external signal cycle, there was a big time constraint on the software that all processing had to be completed within that cycle.
Furthermore, it is not possible to handle an asynchronous processing format in which processing times are not the same, such that processing requests are generated randomly. In other words, this method requires a certain sequence of operations! It is applicable only to regular processing such as following IAI/c, and cannot be applied to complex immediate processing such as performing processing according to the priority level when a processing request is generated.
xi図は、処理A、 Bが20m5に1回毎に順番に処
理されるタイムチャートを示している。まず、Qmsで
電源がONになり、その後初期設定処理入、処理Bと毎
回順序良く処j!され、約9msで全ての処理が終わり
、そこで電源が断(OFF)となる。これから2Qms
後に再度電源がONになり、次のサイクルが始まる例で
ある。Figure xi shows a time chart in which processes A and B are sequentially processed every 20 m5. First, the power is turned on with Qms, and then the initial setting process starts, then process B, and so on in the correct order every time! All processing is completed in approximately 9 ms, and the power is then turned off. 2Qms from now
In this example, the power is turned on again later and the next cycle starts.
第2図は従来の電源制御装置のブロック図である。この
中で斜線部分は、電源のU N10 F F制御が行な
われず、常時ONになっている部分であり、1は中央処
理部(CPU)、2はメモリ部(MEM)、3Fi入l
fi力制御ff1(Ilo)、4は電源側mmtyc)
、5はインターバルタイマ(TIM)である、この実施
例の電源0N10FF 制御はインターバルタイマ5
で行なうものである。また、別の方法としてタイマによ
り電源をONとし、工10命令等で電源’(HOFFと
する方式も用いられている。FIG. 2 is a block diagram of a conventional power supply control device. The shaded areas are the parts that are always ON without U N10 F F control of the power supply, 1 is the central processing unit (CPU), 2 is the memory unit (MEM), and 3Fi inputs.
fi force control ff1 (Ilo), 4 is power supply side mmtyc)
, 5 is an interval timer (TIM), the power supply in this embodiment is 0N10FF, and the interval timer 5 controls
This is done in Another method is to turn on the power using a timer and turn off the power using a 10 command or the like.
これらの方式は、タイマーによシミ源がONとなる九め
、定期的にしかCPUI k利用することができず、更
に電源ON後の処理順序をあらかじめ決めておく必要が
あった。また、その−周期内の処理量に限界があるため
、ソフトウェアへの処理時間の制約が大きく、各処理時
間の合計は一周期管越えられなかった。すなわち、従来
の方法は一周期内に極く限定された固定処理のみt対象
とすることしかできなかった。従りて、ランダムに処理
要求が発生する場合、これを優先度順や発生時点順に管
理したり、その処理量も大小多種ある様なリアルタイム
マルチタスク等の用途では有効に省電力ができなかつ次
。In these methods, the CPUI can only be used periodically when the stain source is turned on by a timer, and furthermore, it is necessary to decide in advance the processing order after the power is turned on. Furthermore, since there is a limit to the amount of processing within one cycle, the processing time for the software is severely restricted, and the total processing time for each cycle cannot exceed one cycle. That is, the conventional method could only target fixed processing that is extremely limited within one cycle. Therefore, when processing requests occur randomly, it is not possible to effectively save power in applications such as real-time multitasking where processing requests are managed in order of priority or time of occurrence, and the amount of processing varies in size. .
本発明の目的は、これらの欠点を除去し、ユーザーから
のランダムな処理要求を割込で受付け、これによって電
源t−ONとして費求された処理を即時的に行ない、そ
の後処理するものがなくなりアイドル状態になると電源
1OFFとすることにより、低電力化を計っ九データ処
理装置の電源制御装置を提供することにある。The purpose of the present invention is to eliminate these drawbacks, accept random processing requests from the user by interrupt, and thereby immediately perform the processing required when the power is turned on, so that there is nothing to process after that. An object of the present invention is to provide a power supply control device for a data processing device that reduces power consumption by turning off the power when the device is in an idle state.
本発明によれば、外部で発生゛するランダムな処理要求
に対して即時に対応でき、その優先度に応じた優先順で
処理して行くことが可能となるデータ処理装置を構成で
き、ランダムな処理要求に即時的に対応しながらもその
中のアイドル時間の無駄な電力を削減し、低消費電力化
を計ることができる。According to the present invention, it is possible to configure a data processing device that can immediately respond to random processing requests generated externally and process them in a priority order according to their priority. While responding immediately to processing requests, it is possible to reduce wasted power during idle time, resulting in lower power consumption.
第3図は本発明の実施例のブロック図であり、lFi中
央処理部s 2fiメモリ部、3Ifi人出方制御部、
4Fi電源制御部、6は割込受付部(INT)である、
この実施例は、アイドル時CPUIが停止して電源がO
FFとなってhるとき、l103等の電源もOFFとな
っている。但し、メモリ部2に対しては電源がOFF時
でもその情報が失なわれず、かつ消費電力が小さい様な
メモリ素子や回路を用するとする。これ以外の電源制御
部4、割込受付部6は、常時電源が入っているが、c−
yos素子等を用いることにょ9その消費電力を極ゎめ
て小さくすることが可能である。FIG. 3 is a block diagram of an embodiment of the present invention, in which the IFi central processing unit s, the 2fi memory unit, the 3Ifi people control unit,
4Fi power supply control unit, 6 is an interrupt reception unit (INT),
In this embodiment, when the CPU is idle, the CPU is stopped and the power is turned off.
When it becomes FF, the power supply of l103 etc. is also turned off. However, for the memory section 2, a memory element or circuit that does not lose its information even when the power is turned off and has low power consumption is used. The power control unit 4 and the interrupt reception unit 6 other than this are always powered on, but c-
By using a YOS element or the like, the power consumption can be extremely reduced.
この電源のOFF状態において、処理要求が発生し危場
合、外部機器からの割込信号として割込受付部6に信号
が送られる。これにより割込受付N6は、CPU都1に
割込受付信号を送ると共に電源制御部4に対しても電源
ON信号を送る。この電源制御部4に送られた電源ON
信号により、電源制御部4はCPUI とl103の
電源をONとする。この電源ONにより、CPU1はリ
スタートも、内部状態を電源OFFの前の状態に復元す
る。これが終ると制御プログラム(O8)により割込信
号を識別してその割込チャンネルに対応したプログラム
を実行する。このO8の動作は、基本的に従来の動作と
変わる所はなく、はぼ従来のO8と同じもの全使用可能
である。In this power OFF state, if a processing request occurs and there is an emergency, a signal is sent to the interrupt reception unit 6 as an interrupt signal from an external device. As a result, the interrupt reception N6 sends an interrupt reception signal to the CPU 1 and also sends a power ON signal to the power supply control unit 4. Power ON sent to this power supply control unit 4
In response to the signal, the power control unit 4 turns on the power to the CPUI and l103. By turning on the power, the CPU 1 restores its internal state to the state before the power was turned off, even when restarted. When this is completed, the control program (O8) identifies the interrupt signal and executes the program corresponding to that interrupt channel. The operation of this O8 is basically the same as the conventional operation, and almost all the same components as the conventional O8 can be used.
tた、多数の割込信号が発生しているときでも電源制御
ISAは、一度割込受付部6からのON信号を検出する
と、次にCPU1からのOFF信号を検出するまで、C
PUI の電源をONに保持するR/8フリップフロッ
プを備えているのでこれが0FF1!号金受取るまでC
PUの電源YtOFFとしない様にしている。In addition, even when a large number of interrupt signals are generated, once the power control ISA detects an ON signal from the interrupt reception unit 6, the power supply control ISA continues to control the CPU until it detects an OFF signal from the CPU 1.
It is equipped with an R/8 flip-flop that keeps the PUI power ON, so this is 0FF1! C until you receive the amount
The PU power is not turned off at YtOFF.
第4図は多重割込処理例として処理A、Bがランダムに
処理要求を出した場合のタイムチャートで、電源のON
10 F F とosによる即時的優先処理との関係
を示している。これにょp処理要求が出たときには電源
がONになってがらosに制御が渡り、その後はosで
制御されて行くことがわかる。処理安来されたプログラ
ムが全て終了し、処理すべきものがなくなった場合、o
sは停止命令を出し、CPUI はこれを実行し電源制
御s4に電源OFF信号を出し、これにょシミ源制御部
4は電源をOFFとし初めの状態にもどる。この場合処
理Bの優先度が処理部の優先度より高いとしている。Figure 4 is a time chart when processes A and B issue processing requests randomly as an example of multiple interrupt processing.
10 shows the relationship between F F and immediate priority processing by the OS. It can be seen that when a processing request is issued, control is passed to the OS while the power is turned on, and thereafter the OS controls the system. When all the programs that have been processed have finished and there is nothing left to process, o
s issues a stop command, the CPUI executes this and issues a power OFF signal to the power control s4, and the stain source control unit 4 turns off the power and returns to the initial state. In this case, the priority of process B is higher than the priority of the processing unit.
この際電源がOFFとなるとCPU1内の情報が失なわ
れる事に注意する必要がある。もしCPU内のステータ
ス情報等のうちに再開後必要な情報があれば、停止命令
実行前に電源がOFFとなってもその情報が消光なりメ
そりに退避させておき、その後処理要求が発生し、電源
がONになったときにこれらの情報を復元すれば良い。At this time, it must be noted that the information in the CPU 1 will be lost if the power is turned off. If there is information that is necessary after restarting, such as status information in the CPU, even if the power is turned off before executing the stop command, that information will be extinguished and saved in the memory, and a processing request will be generated after that. , these information can be restored when the power is turned on.
なお、08にはこれらの退避復元や再開時の初期設定等
の機能を追加しなければならないが、これらの部分は機
械餠命令で実行するよりもファームウェアを用いる方が
オーバーへ、ドや消費電力削減の点から望ましい。In addition, in 08, it is necessary to add functions such as saving and restoring these functions and initial settings when restarting, but it is better to use firmware than to execute these parts with machine instructions. Desirable from the point of view of reduction.
以上の様に、従来の電源0N10FF による低電力化
は固定のシーケンスでのみ可能であり友ため、ランダム
に処理要求が発生するものや、即時処理が必要なものに
は適用できず、又プログラムの作成変更の柔軟性が小さ
かつ次が、本発明によれば処理要求に合わせて、友とえ
ランダムであっても′それに即時的に対応できるため、
低電力化と共にリアルタイムな多重処理が容易に実現可
能である。As mentioned above, power reduction using the conventional 0N10FF power supply is only possible in a fixed sequence, so it cannot be applied to things where processing requests occur randomly or things that require immediate processing, and it cannot be applied to things where processing requests occur randomly or things that require immediate processing. The flexibility of creating and changing is small, and according to the present invention, it is possible to instantly respond to processing requests, even if they are random.
Real-time multiprocessing can be easily achieved with low power consumption.
例えば、約100m1毎に1回1msの処理量があシ、
そのON10 F F 時のオーバーへ、ドが1回に
約64m5である場合、その電源08時のデユーティは
15%であり、従って消費電力は連続動作時10’OW
の機器でも平均1.5Wとなり、大幅に低電力化が図れ
る。この低電力化によp電源による発熱量が減少するの
で、放熱器中冷却器等が部品化され小i、軽量化も図ら
れる。For example, the processing amount is 1 ms once every 100 m1,
If the power supply is about 64 m5 at a time, the duty at 08 of the power supply is 15%, so the power consumption is 10'OW during continuous operation.
The average power consumption for this device is 1.5W, making it possible to significantly reduce power consumption. This reduction in power consumption reduces the amount of heat generated by the p-power source, so the radiator, middle cooler, etc. can be made into components, making it possible to reduce the size and weight of the device.
この発明の適用範囲は、可搬用機器や車両、航空機、ロ
ケット、人工衛星等に搭載するコンビ。The scope of application of this invention is combinations mounted on portable equipment, vehicles, aircraft, rockets, artificial satellites, etc.
−タ、制御装置、シーケンサ等が考えられる。- controllers, control devices, sequencers, etc.
第1図は従来の固定された処理シーケンスのタイムチャ
ート、第2図は従来の処理シーケンスをもつデータ処理
装置のプロ、り図、第3図は本発明の実施例のプ四ツク
図、第4因鴬は本発明におけるランダムな処理要求が発
生した場合のタイムチャートである0図において、
1・・・・・・中央処理部、2・・・・・・メモリ部、
3・・・・・・入出力制御部、4・・・・・・電源制御
部、5・・・・・・インターバルタイマ、6・・・・・
・割込受付回路である。FIG. 1 is a time chart of a conventional fixed processing sequence, FIG. 2 is a professional diagram of a data processing apparatus having a conventional processing sequence, and FIG. 3 is a four-dimensional diagram of an embodiment of the present invention. The four factors are as follows in Figure 0, which is a time chart when a random processing request occurs in the present invention: 1...Central processing unit, 2...Memory unit,
3... Input/output control unit, 4... Power control unit, 5... Interval timer, 6...
・This is an interrupt reception circuit.
Claims (1)
込信号を検知し処理を制御する信号を形成する割込受付
回路と、前記停止命令により前記割込受付回路以外の回
路の電源を切断しかつ前記割込受付回路の制御出力によ
シ全回路の電源を投入、 して処理t−開始させる電
源制御回路とを含むデータ処理の電源制御装置。[Claims] An interrupt that detects a stop command in step 4 when all processing is completed and there is no longer a processing target, detects an interrupt signal input when a processing target occurs, and forms a signal to control the processing. a reception circuit; and a power supply control circuit that turns off power to circuits other than the interrupt reception circuit according to the stop command, turns on power to all circuits according to the control output of the interrupt reception circuit, and starts processing. and a power control device for data processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101931A JPS583009A (en) | 1981-06-30 | 1981-06-30 | Electric power supply controller of data processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101931A JPS583009A (en) | 1981-06-30 | 1981-06-30 | Electric power supply controller of data processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS583009A true JPS583009A (en) | 1983-01-08 |
Family
ID=14313651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56101931A Pending JPS583009A (en) | 1981-06-30 | 1981-06-30 | Electric power supply controller of data processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583009A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59206920A (en) * | 1983-05-10 | 1984-11-22 | Sharp Corp | Controlling system of time processing |
| JPS59220574A (en) * | 1983-05-31 | 1984-12-12 | 松下電工株式会社 | Cpu speeding preventing system in electronic lock system |
| JPS6016756A (en) * | 1984-05-31 | 1985-01-28 | Tamura Electric Works Ltd | Processing control system of device |
| JPS6019220A (en) * | 1983-07-13 | 1985-01-31 | Fujitsu Ltd | Microcomputer |
| JPS62103766A (en) * | 1985-10-30 | 1987-05-14 | Omron Tateisi Electronics Co | Card certifying terminal device |
| JPS62150416A (en) * | 1985-12-24 | 1987-07-04 | Nec Corp | Transition system to low power consumption state |
-
1981
- 1981-06-30 JP JP56101931A patent/JPS583009A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59206920A (en) * | 1983-05-10 | 1984-11-22 | Sharp Corp | Controlling system of time processing |
| JPS59220574A (en) * | 1983-05-31 | 1984-12-12 | 松下電工株式会社 | Cpu speeding preventing system in electronic lock system |
| JPS6019220A (en) * | 1983-07-13 | 1985-01-31 | Fujitsu Ltd | Microcomputer |
| JPS6016756A (en) * | 1984-05-31 | 1985-01-28 | Tamura Electric Works Ltd | Processing control system of device |
| JPS62103766A (en) * | 1985-10-30 | 1987-05-14 | Omron Tateisi Electronics Co | Card certifying terminal device |
| JPS62150416A (en) * | 1985-12-24 | 1987-07-04 | Nec Corp | Transition system to low power consumption state |
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