JPS583070A - Analog multiplier and its driving method - Google Patents

Abstract

PURPOSE:To reduce power consumption and to make an IC small-sized, by using a switched capacitor circuit consisting of 2 MOSFETs having the same characteristic, and operational amplifier, a switch and a capacitor. CONSTITUTION:An MOSFET 1 and 2 constitute a 4 quadrant analog multiplier. The first capacitor 43 and switch 44 are connected between an inverted input terminal 45 of an operational amplifier 42 and an output terminal 46, and constitute the first integrator. The second capacitor 48 and switch 49 are connected between an inverted input terminal 51 of an operational amplifier 47 and an output terminal 52, and constitute the second integrator. Between the output terminal of the first integrator and the output terminal of the second integrator, the third capacitor 50 having a capacity value which is equal to the first capacitor 43 of the first integrator is connected. The output terminal 52 of the operational amplifier 47 is connected to an output terminal 60 of the analog multiplier.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a configuration of an output circuit of an analog multiplier using two MO8FB'1's and a method of driving the same.

The analog multiplier using the MO811'ET of 2 bonds has a simple 4-cycle configuration, and the weighting of transversal filters that can vary the filter characteristics using charge transfer elements, etc. have been commonly used in circuits, etc. It is being

FIG. 1 is a diagram for explaining the operating principle of an analog multiplier using MO8FB'l' of 21[a.

MO8FETs 1 and 2 are two MOS transistors that constitute the analog multiplier, and these two MO8FB
'l' ] and 2 have the same properties. The MO8FET 1
The gate of is connected to the terminal 18, and the diffusion layer on one side and the diffusion layer on the other side are connected to the wirings 10 and 1, respectively.
1 is connected. On the other hand, the gate of the MO8 light 2 is connected to the first element 19, and wirings 12 and 13 are connected to one diffusion layer and the other diffusion layer, respectively. Arrangements 11110 and 12 have terminal 1 in common.
The wiring 11 is connected to the positive phase input terminal of the output circuit 3 of the four-quadrant analog multiplier, and the wiring 13 is connected to the negative phase input terminal of the output circuit 3. Also, the output circuit 3
is provided with a reference '-pressure input terminal 17,
The output of the output circuit 3 serves as an output terminal of an analog multiplier. The output circuit 3 maintains the voltage of the wiring 11.13 at the first bias voltage applied from the fourth terminal 17, and also maintains the drain current flowing through the 10M08FhT1 and the second wire 8FNT2. It also has the function of outputting an output voltage proportional to the difference between the drain current flowing through the output terminal and the output terminal.

Now, the voltage applied to the terminal 16 of @1 is the first input signal voltage superimposed on the first bias voltage -, and the voltage applied to the second terminal 18 is the second bias voltage. The voltage applied from the third terminal 19 is the second input signal 'voltage V8, which is applied from the third terminal 19 to the second bias voltage 1, and these terminals 16.1 & 16.
19.17 Always keep the voltage applied to the first MO
Set S to gT 1 and the second MOS to operate in the triode region. If the first input signal voltage V, is positive, the drain current flowing through the first MO8FnT2 is the drain current flowing through the first MO8FnT2. l” 1
and tom 2 OMOf! (l'FmT2)-value'
Assuming that the stone dimension from ILEIVya construction 1 dimension is B, and the '#Lm flowing from the terminal 16 in the direction of the output circuit 3 is positive, it is 4t-b ((VB+V* -Va-vl)Vt 2z)
(1) Equation 2=H ((% 'm-foodv, %笥)(2)
The formula becomes Therefore, in the output circuit 3, the difference between the above current values is determined, and the first-class voltage conversion coefficient of the output circuit 3 is set as K.
When the difference between the above -current values is converted into a voltage, the output voltage Vout of the terminal 20 is VoutmK(II x,)4ωv,ay, (
It will be a 3 piece type. That is, the output voltage You t is proportional to the calculation result of the first input signal voltage v1 and the second input signal minus the voltages v and O. On the other hand, if the first input signal voltage is negative, the first original) ETl and the 20th M) 8FhT2
The direction of the current flowing in Ayu 1 is opposite to that when the input signal voltage V is positive, and its itftm is 4t =
-B(('B+v2-X-v1Qv, -Kei< ) (1
') Formula 'ag=-B((Vn VK "s %) vl2
<), formula (2') is obtained. However, it can be seen that if the difference between these current values is determined, the output voltage Vout becomes as shown above, resulting in a four-way analog multiplier.

FIG. 2 shows a specific example of the conventional four-quadrant analog multiplier shown in FIG. Area 3 surrounded by a forest is the Pro! This is a four-quadrant analog multiplier output circuit. Components other than the portion 3 surrounded by the broken line are the same as in FIG. 1, and therefore are given the same numbers as in FIG. 1.

It is also assumed that voltages similar to those shown in FIG. 1 are applied to terminals 16, 18, 19, and 17. The inside of the output circuit 3 will be explained.

A first current-voltage converter composed of an operational amplifier 21 and a resistor n, and a second current-voltage converter composed of an operational amplifier n and a resistor are connected to the wiring 17 and the wiring 13, respectively.
0゛- voltage is set to the bias voltage applied from the terminal 17, and a voltage value proportional to the current flowing through the F) Mαl FET 1 and the current flowing through the second MOSFET 2 is set. Output.

W, 10 MO8 to 'ET 1 Drain current ID
1 is given by the equation (]) or the equation (0, but the drain current Io all flows into the resistance n. Therefore, the resistance n
When the resistance value of is , a voltage of (%'n-Iat.R?) is outputted to the output terminal of the operational amplifier 21.

Similarly, the drain current ■□ flowing through the second MO8 sheet ET2 is given by the equation (2) or (2'), and if the resistance value of the resistor U is U, then the output terminal of the operational amplifier 1) is A voltage of s (Va'ox~) is output.

On the other hand, there is an operational amplifier 25 and a resistor ll1)tD.

27, 28, and 29 constitute a gain 10 subtracter, the output terminal of the operational amplifier logger is connected to the negative phase input terminal 31 of the subtracter via the wiring 14, and the output terminal of the operational amplifier n is connected to the negative phase input terminal 31 of the subtracter via the wiring 15. It is connected to the positive phase input terminal 30 of the subtracter. The output terminal of the subtracter is connected to the output terminal +9 of the four-quadrant analog multiplier. The output terminal +9 outputs the difference between the voltage input from the terminal and the voltage input manually from the terminal 31, so the output/voltage Vout is ("Dl 'ox)"r -B9"Bvl/v2
Then, the sum of the first input signal voltage (1) and the second input signal voltage (v2) is obtained.

The conventional analog multiplier shown above can be easily realized using Hill's MOiMFkT with the same characteristics, three operational amplifiers, and six resistors, but using this conventional configuration,
Many problems arise in order to obtain a four-quadrant analog multiplier integrated into an IC with low power consumption. First, since it is a prototype process or an MO8 process, uniform and large values (
> Creating a resistance of 1KQ) is a problem. Also,
When an impurity diffusion layer, impurity-doped polysilicon, or the like is used as a resistance element, nonlinearity occurs in the resistance in which the resistance value changes depending on the value of the flowing current. Furthermore, since resistors are used, current constantly flows through each resistor, increasing power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog multiplier that eliminates these conventional drawbacks, has low power consumption, and can easily be made into a compact IC, and a method for driving the same.

According to the present invention, one diffusion layer of the first MO8F counterfeit and the second MO8FgT having the same characteristics is shared.
+ is connected to the first terminal, and the first MO8FI! vll
& Him 2nd f) MO8kWr (D other) Diffusion N, respectively, the 1st consisting of an operational amplifier, a switch, and a capacitor.
of the integrator, is connected to the integral input terminal of the second integrator, and the above $ 1, ノMO8fg'l'o'r' -) and C
The gates of the second M)8FkiT are connected to a second terminal and a third terminal, respectively, of the first integrator.

The terminals are commonly connected to a fourth terminal, and further between the output terminal of the first integrator and the integration input terminal of the second integrator, a terminal used for the first @divider is connected. A weighing scale having a capacity ffjl: which is the same as the integral capacity of the second integrator is provided, and the output terminal of the second integrator is connected to the terminal of WJ5. The first practice with nt='g'i' and the second ~osb"1!
One diffusion layer of each of i'i' is commonly connected to the first terminal, and the first MO8FNT and the second MO8FM'l
Connect the other diffusion layer of ' to one terminal of the first switch and the second switch, respectively, and
' The gate of the gate and the MO8FgTO gate of [2] are
are connected to the second terminal and the third terminal, respectively, and are connected to the first terminal.
switch and the 2i! ! The other terminal of the second switch is connected to the integration input terminal of the first integrator and the second integrator, each of which is composed of an operational amplifier, a switch, and a capacitor. The reference voltage input terminals provided in the integrators are commonly connected to the fourth terminal, and further,
The output terminal of the integrator i41 and the division input terminal of the second integrator are connected by a weighing device having the same capacitance value as the integral capacitance used in the first integrator. An analog multiplier 1x is obtained, characterized in that the output terminal of the second integrator is connected to the fifth terminal.

According to the present invention, the first (1
) MO8FET 2nd (8M08 to':t'i'
(D sotL sotLf) Connect one of the diffusion layers to the first terminal in common and connect the first diffusion layer g'i' and the second MO8r.
'ET's other diffusion layer to the first switch, one terminal of the noodle 2 switch, &fiL, the first MO
The gate of the first switch and the gate of the second Mω are connected to a second terminal and a third terminal, respectively, and are connected to the other of the first switch and the second switch. Is that the terminal? L is connected to the integral input terminal of the first integrator and the second integrator, each consisting of an operational amplifier, a switch, and a casing; and the III quasi-voltage input terminal provided in the second integrator are commonly jlI4
connected to the terminal of , and the output terminal of the integrator of stripe 1,
#, M1 between the integration input terminal of the second integrator
A capacitor having the same capacitance value as the integrating capacitor used in the integrator is provided, and the analog multiplier connected to the output terminal of the second integrator or the fifth terminal is The terminal has a first voltage superimposed on a bias voltage of %M1.
An input signal voltage is applied to the second terminal, a second input signal voltage applied to the second bias voltage is applied to the second terminal, and a second bias voltage is applied to the third terminal. Apply the voltage and the fourth
A first bias voltage is applied to the terminal of the first MO8Fg1, the first integrator and the second integrator are reset, and the first switch and the second switch are made conductive. ' and iσ second constant 08Il'E'l'
The potential of the other diffusion layer of MO8Fh
'The @1 current flowing through T is integrated in the first integrator, and the second current flowing through the second MO8Fl lamp is connected between the output terminal of the first CI integrator and the integration input of the second integrator. The capacitance connected between the output terminal of the first (09) divider and the integration input terminal of the second integrator is integrated by the first integrator. [Since the charge due to the current of 1 is inspected,
The second integrator integrates a quantity proportional to the difference between the first % flow and the second 11c flow, and connects the first input to the output terminal, that is, the fifth terminal, of the second integrator. A voltage proportional to the product of the signal voltage and the 20th person's Cairo voltage is generated, and then the first switch and the second switch are made non-conductive, and #! An analog multiplier driving method is obtained in which the percentage value is to stop the integration of the detector #1 and the detector #I2, and repeat the above steps until the next sampling period. The present invention will now be described in detail.

FIG. 3 is an embodiment according to the present invention. MO8Fff1
, &bi2 is 4I! 2 constituting a limited analog multiplier
gljo yWJ8E'MT te,Crera2 im(D
The characteristics of MO8k"h'l' 1, , & 2 are the same. The diffusion layers of one of the wire fibers Sk'filfr 1. and 2 are shared in common via the wiring 10.12, and the diffusion layer of the other is They are connected to the inverting input terminal 45 of the operational amplifier 420 and the inverting input terminal 51 of the operational amplifier 47 via wires 11 and 13, respectively.The gate of MO8\T1 is connected to the terminal 18, and the gate of MO8\T1 is connected to the terminal 18. terminal 19
It is connected to the. Further, the first capacitor 43 switch I° is connected between the inverting input terminal 45 and the output terminal 46 of the operational amplifier 4420, and the operational amplifier 42
．． all capacitors 43. and switch I/I'i constitute a first integrator. On the other hand, the second capacitor switch 49 is connected between the inverting input terminal 51 and the output terminal of the operational amplifier 47. Second capacitor mallet and switch 49
constitutes the integrator #I2.

Furthermore, an operational amplifier 42. The non-inverting input terminals of the operational amplifiers 47 are commonly connected to a terminal SIc as a reference voltage internal input terminal. Between the output terminal of the operational amplifier 47, that is, the output terminal of the integrator of agl, and the output terminal of the operational amplifier 47, that is, the output terminal of the integral of g2,
The first capacitor used in the tol1 divider
A third group of capacitors with a value equal to d is connected to the output terminal of the operational amplifier 47 and is connected to the output terminal ω of the analog multiplier.

FIG. 4 shows #! which is an embodiment of the present invention. This is to explain one of the works in Figure 3. 201 is a second signal voltage that is superimposed on the second bias voltage applied from the terminal 18. Here, in order to simplify the explanation, the second signal voltage is assumed to be equivalent to a DC voltage.

202 is a first signal voltage superimposed on the first bias voltage 4 applied from the terminal 16. Here, in order to simplify the explanation, the 10th signal voltage is
Let it be a positive and negative pulse-pressure of amplitude W.

Reference numeral 203 is a pulse for opening and closing the switch I of the integrator 49, and when the pulse is at a high level, the switch is in a conductive state, and when it is at a low level, the switch is in a non-conductive state.

The flag is a schematic diagram of the output waveform of the first integrator, that is, the output terminal 46 of the operational amplifier 42, and 205 is a schematic diagram of the output waveform of the output terminal of the analog multiplier. Furthermore, the bias voltage 1 of terminal 191 and 142 is
A tenth bias voltage is applied to these terminals 16.
The voltage applied to 18.19.53 is $ 1 (D
'M'J' l and @ 2 OMO8Pf in M2S
! Set it to always operate in the yr2 or triode region.

First, consider the period 210 of tm. In this period 210,
Since the switch terminal 49 is in a conductive state, the charges on the capacitors 43 and 48 are cleared, and the terminals 46 and 52 are in a conductive state.
The voltage of is set to -. Therefore, the voltage across the third capacitor group is equal, and the charge on the third capacitor group is also cleared. Next, during the - period 211, when the switch 49 becomes non-conductive, the wiring 11111 is still set to -, so the current value ID1 shown in equation (1) flows through the MO8i''ET14. This current is integrated by the capacitor 43 made of lead 1. If the time from the beginning of the period 211 is ta C < tm), the charge accumulated in the capacitor is -□〇-, and the charge accumulated in the first capacitor l When the capacitance value of
Therefore, the output voltage at the terminal section becomes a linear @number of time and has a ring-shaped waveform like a bubble. On the other hand, for MO8FBTz (2)
A current value expressed by the equation flows, and this current is integrated in the second capacitor ω and the third capacitor ω.

Since the voltage on both sides of the capacitor group in building 3 is -(chi,・td/c) in time, if the capacitance value of the third capacitor group is C, then the charge accumulated in the third capacitor group is becomes s ”ot・td.

The charge flowing in from MO8Fgl' 2 is -・(
Therefore, the charge accumulated in the second capacitor 48 is (Iri!・−Iot・Lee(ID2−I,)・−
becomes.

If the capacitance of the second capacitor is C, then the output terminal 52 of the operational amplifier 47, that is, the output terminal 60 of the analog multiplier 4C41, (-(Im-"oJ" td/C+
V, B) - ((Lot-IoJ・td/C14). Since the signal is the DC component at the first bias voltage, the signal component becomes ((lot-IoJ・td/c). , M.O.
Current IDI flowing in 811'h7T1 and MO8ffr
2 is proportional to the difference in the current IDm flowing between the two terminals. That is,
The output voltage Vout is proportional to the product of the first input signal voltage and the second input signal voltage.

However, the output voltage in the case of Fig. 3 is 205 in Fig. 4.
The output waveform becomes a hook-shaped waveform, and the analog output cannot be output as it is. However, in a system where a non-sampling analog element such as a sample hologram is connected to the next stage, accurate multiplication results can be obtained by setting the sampling timing of the next stage to the - period 211. I can do it. Therefore, the invention shown in FIG. 3 is an effective and excellent analog multiplier when used as a functional element in a system composed of sampling analog circuits.

Figure 1g5 is an example of a case where a function to hold the output voltage is incorporated in order to use the present invention as a single analog multiplier. The configuration of each part is almost the same as in Fig. 3, including switch 1 for hold, switch a for $Z, and switch 41 for $Z.
are provided between the wiring 1I111 and the inverting input terminal 450 of the operational amplifier 12, and between the wiring 13 and the inverting input terminal 610 of the operational term -947, respectively.

FIG. 6 is a diagram for explaining an example of the driving method of the present invention in FIG. 5. 101 is a second signal voltage superimposed on the second bias voltage v applied from the terminal 18. Here, in order to simplify the explanation, the second signal voltage is assumed to be a DC voltage.

102 is the signal voltage of the signal superimposed on the first voltage v1 applied from the terminal 16. Here,
To simplify the explanation, let us assume that the first signal voltage is 4 and 7 pulse voltages of positive and negative amplitudes of Vt as shown in the figure.

103 is a pulse for opening and closing the switch material and 49; 104 is a pulse for opening and closing the switch lead and 41; these switches 4G, 41, 44, and 49 are conductive when the pulse is at a high level; 4. It is assumed that the signal becomes non-conductive when the pulse is at a low level. 105 is the first integral @0 output, that is, the output terminal of the first operational amplifier 42; 106G is the output of the second integrator, that is, the output terminal of the second operational amplifier 47; FIG. 3 is a schematic diagram of the output voltage VOut of the output terminal button of the analog multiplier.

At the same time, the second bias voltage is also applied to terminal 19.
A first bias voltage 4 is applied to terminal 53 φζ, and these terminals 16°18, 1G, and 534C are applied.
% pressure 4 [10M08j'fl' 1 and 2nd MO8
Set FNT 2 to always operate in the triode region.

First, consider a period 110 of t. During this period 110, the switch weak and the switch 49 are in a conductive state, and the switch 49 and the switch 41 are in a non-conducting state. Therefore, the first operational amplifier 42 and the second operational amplifier 47 both act as voltage followers. , first operational amplifier 42
0 inversion input terminal6. Output terminal casting.

and second operational amplifier 470 inverting input terminal 51 . The output terminal 52 is a tenth bias voltage applied from the terminal group. Therefore, capacitor 4 of lif
For the key capacitor of 1412 and the capacitor of @3,
It is in a so-called reset state in which there is no charge.

At this time, the wiring potentials 1111 and 130 are hID8F of fabric 1.
Since no drain current flows, the voltage applied from terminal 16 (
V, +v1) K.Next, in the period 111 of ts, if the switch 49 and the switch 49 are in a conductive state and the switch 41 is in a conductive state, the wiring 11° and the wiring 13 are as follows. 1st D respectively
Nose amplifier 420rjL input terminal, second operation increase @
! i! Connect with the inverting input terminal 5J of 47, $
10M08F nail 1. 2nd MO8Fh'T 20
/− source (or drain) voltage is equal to the first bias voltage −, and MO8F of stripe 1 shown by equation (1)
Drain current of fart 1 -1 (the second MO shown in the rumored formula
8FIT! drain current - flows through the second switch I and the fourth switch 49, respectively. However, since the switch @2 and the fourth switch 49 are still in a conductive state, the output voltage of the first operational amplifier 42 is 10.
5. The voltage 106 at the output terminal 52 of the second operational amplifier 47 is -, like the 110g function 110.

Next, during the period 112 of t, the switch 41 and the switch 41 remain in a conductive state, and the switch 49 and the switch 49 remain in a conductive state.
When becomes non-conductive, since the inverting input terminal Qi of the first operational amplifier @42 is always set to the voltage v1, the current flowing through the switch Xu becomes t.

It is integrated by one capacitor 43. If the time from the start of period 1120 is td (<tρ, then the amount of time accumulated in Xie 10 Kikipacita 43 is Iolla,
Assuming that the capacitance of the tenth capacitor 43 is C, the voltage at the output terminal 46 of the first operational amplifier @42 is (%-(I
nt”d/C) ) (!: Suh o On the other hand, Su(
The current flowing through the capacitor 41 is also the same as the period 111 of t, and the current is %@2 between the capacitor 48 and the capacitor 3.
It is integrated by the capacitor value. The voltage across the third capacitor is the inverting input terminal 5 of the 20th operational amplifier 470.
1o-voltage v1 and the voltage (Vl-('DI・td/C)) at the output terminal of the operational amplifier 42 of irises 1 (!D)
l@td/C). Therefore, the 30th capacitor 50
If the 0 capacitance is equal to the capacitance of the 1st capacitor and is C, then the charge stored in the BSto capacitor is (chi □・ri).The total amount of charge stored in the #! 2 o capacitor and the 30 capacitor is , is the integral value of the current flowing through the switch 414C, so it is (Im-).

Therefore, the amount of charge accumulated in the 20th capacitor hammer is (
If Im-1ρ・td and the capacitance of the capacitor hammer of 5rltz is C, then the output terminal 52 of the operational amplifier of m2
That is, the -voltage Vout of the output terminal shaft of the analog multiplier becomes ((IDI - Its)·ta/C+VB). 4 is the bias voltage of #41 [+51! component, the signal component is (ID□-1)・td/C,
This value is proportional to the difference between the drain current ID□ flowing through the first hljUsk゛ET1 and the drain current flowing through the second MOS transistor HT2. That is, the output voltage Vout is proportional to the product of the first input signal voltage v1 and the second input voltage.

After a long time, in period 113 of t4, the switch is turned on and 41 non-conducting AKL, m1t) hK) 8 is set to 'JIT1 and C11.
The current flowing to 11LC1111L2(1) is stopped and the output voltage You t is held. This held output voltage VouHD signal component depends on the period 112 of [3, and its value is %('DI-t27C)
13, the period 110 of tl is repeated again.

In addition, in the present invention, the capacitances of the first capacitor, the second capacitor, and the third capacitor are as follows:
In the description of the embodiment, it has been explained that they are all equal, but if the capacitances of the first capacitor 4 and the third capacitor 4 are equal, the analog multiplier according to the present invention operates normally.

As described above, according to the present invention, there are two -SF integrators and two reset integrators having the same characteristics.

A high performance analog multiplier can be obtained with a 2ml switch and one capacitor. Also, the process allows capacitors to be easily made, and furthermore, the ratio of these capacitors can be controlled very precisely. Therefore, by using the present invention, it is possible to integrate all analog multipliers into ICs. Furthermore, compared to the conventional O and OK, the number of operational amplifiers is smaller, making it possible to reduce power consumption in a much smaller part.

In the above explanation, the integrator has a structure consisting of an operational amplifier, a 1@ capacitor, and one reset switch, but this is just an example and if the integrator has the same function, It can be anything. Also %I1
1 bias voltage - 1 second bias voltage - the voltage value of the first input signal voltage v1. The second input signal voltage V, applied tt,"c is also fKKIO3MO81'l
fl' 1, @ 2 OMO81Mr 2 is one 21
It suffices if the conditions are met so that it can operate at the pole.

Although the case has been described in which a pulsed signal is used as the input signal voltage □ of *<5tiAl and a direct current is used as the second input signal voltage 4, a general alternating current signal voltage may be used. Also, the continuity of the switch.

Regarding the timing of non-conduction, switch 41 changes from non-conductive to conductive, then switch 0.41 changes from non-conductive to conductive, then switches 44 and 49 change from conductive to non-conductive, and the switch 41 changes from non-conductive to conductive. In the above, we explained the case where switches 0 and 41 change from conduction to non-conduction, but the condition is satisfied when switch 49 changes from conduction to non-conduction, and then switch 41 changes from conduction to non-conduction. As long as you do, any timing is fine.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the operating principle of an analog multiplier using two OM2S)b-, and Figure 1.2 is a diagram for explaining the operating principle of an analog multiplier using two OM2S)b-.
8F wires, 3 is an output (b) path, 16 is III, an input terminal for the first input signal voltage multiplied by the bias voltage Kin of 1;
18 is the input terminal of the second input signal voltage superimposed on the second bias voltage, 19 is the bias voltage input terminal of M2, 17 is the bias-pressure input terminal of @1, and addition is the analog multiplier. Figure 2 shows an example of the submultiply of an analog multiplier using two FWI's, and the area 3 surrounded by the broken line is the
This is the output circuit in the figure. Operator term − unit 2 and resistance n,
The operational term -625 and the resistors 26.27 and 3.29 constitute a subtracter, respectively. Figure jlI3 shows a 6-operational term width filter 42. which is an example of an analog multiplication ◆O# structure using 2111 MOS F devices according to the present invention. A capacitor 6, a switch, and an arithmetic intensifier 47. FIG. 4 is a schematic diagram for explaining one embodiment of the present invention shown in FIG. 3, and 2Dl is the input signal of j12. voltage, 202 is the first input signal voltage, and 202 is the switch 4
4. The pulses that open and close a are the output voltage of the integrator of ]@1, and 205 is the output voltage of the analog multiplier. 21
0.211 is the time interval used for explanation, and 2
10,211 indicates one clock station period. #I5 diagram is an analog multiplier with a hold function according to the present invention @Q) 1 embodiment, in which a hold switch ν4G,
41 is included. FIG. 6 is a diagram for explaining one embodiment of the analog multiplier driving method according to the present invention, in which 101 is a 420 input signal voltage, 102 is a gt input signal voltage, and 103 is a switch. 44. Pulse for opening and closing 49, 104 is switch 4
0.41 is the opening/closing pulse, 105 is the output voltage of the first reset type anti@integrator, and 106 is the output voltage of the analog multiplier. 110 to 11B are time divisions used for explanation, and 110 to 113 indicate one clock cycle. #! J1 Figure Z Item 3 Figure Broom 4 Figure Pavilion 5 Item 6 Garden

Claims (1)

[Claims] 1. The first MO8t edition and the 20th M with the same characteristics + MT
(] One diffusion layer of each of FkT is commonly connected to the first oj
i114C*/IN, L, cough stripe 1 (OMObF)j,
'r, and m-th 20k (J8 and 'nT' other diffusion layer, respectively, are connected to the integral input terminals of the first integrator and the second integrator, which are formed by the operational term, the switch, and the connection n1. connection,
−1 lth M (gate of 'h'i' in J8 and said second
The gates of Mωywr are respectively second terminals. A reference voltage input terminal connected to a third terminal and provided with the first integrator and the second integrator is co-traceably connected to a fourth terminal and further provided with a Jill integrator. s between the output terminal of the second integrator and the integration input terminal of the second integrator.
A fourth integrator having the same capacitance value as the integrator used in the integrator of vK1 is provided, and the output terminal of the second integrator is connected to the fifth terminal. An analog multiplier with 2. The first MO8FE'l' and the second MO8FE'l' having the same characteristics
One diffusion layer of each of MO8Fk and 'T is commonly connected to the l-th terminal, and the other diffusion layer of V-first bttO8ywr and second MO8Fh'T is connected to the @1 switch and the second MO8Fh'T, respectively. is connected to one terminal of the switch of #!, the gate of the first MO8iI'HT, and the #! 2 M
The gates of O8FnT are connected to the terminal and the third terminal of 'M2, respectively, and the other terminals of the first switch and the second switch are connected to the third terminal, which is composed of an operational amplifier, a switch, and a capacitor, respectively. The reference voltage input terminals provided in the first integrator and the integrator AK2 are connected to the integration input terminals of the first integrator and the second integrator, and the reference voltage input terminal provided in the first integrator and the integrator AK2 is commonly
, and between the output terminal of the first integrator and the integration input terminal of the 42 integrators, there is a capacitance that is the same as the integration capacitance used in the first integrator. A capacitor having a value is provided, and the output terminal of the integrator of @2 is connected to the fifth terminal.
Pain organ. 3. The first MO8FiflT and the second MO8FiflT have the same characteristics.
One diffusion layer of each of MO8Fb'ET is commonly blown to the first terminal, and the first 5tO8j'ET and the second
The other enlargement of N08FW'l'! L- respectively,
The first switch is connected to one terminal of the second switch, and the gate of the first MOS tI'E1' and the gate of the second MOSFET are connected to the N2 terminal and the third terminal, respectively. The other terminals of the first switch and the second switch are connected to a first integral gain terminal and an integral input terminal of a second integrator, each of which is composed of a 7'-point operational amplifier, a switch, and a capacitor. and the first integrator. and the reference voltage input quadrupole ζ provided in the second and integrators are commonly connected to the fourth terminal, and further connected to the output terminal of the first integrator and the first Ik! A capacitor having the same value as the integral capacitor used for the integral serial number of tIrJ1 is provided between the integral input terminal of the second integrator and the integral serial number of the second integrator. In an analog multiplier connected to the output terminal of the integrator or the fifth terminal, the first terminal has a second bias voltage superimposed on the first bias voltage and a second bias voltage superimposed on the second bias voltage. An input signal voltage is applied, a second bias voltage is applied to the #g3 terminal, a first bias voltage is applied to the fourth terminal, and the first C1 integrator and the second autumnal divider along with resetting the first switch. and IK2 switches to the 4-way state, and the first MO
8FB'l' and the potential of the other diffusion layer of the second MO8FIT are set to the first bias pressure applied to the fourth integrator, and then the first integrator and tl
Release the reset of the integrator of lIJ2, and
The first current flowing through kT is separated in the integrator IIf & 1, and the second current flowing through the second MOSFET 4 (@) is connected between the output terminal of the area separator 1 and the integral input terminal of the second integrator. #It is integrated in the integrator connected between #It and N2, or between the output terminal of the first integrator and N2,
Since the capacitor connected between the integral input terminals of the autumn equinox integrates the charge due to the first current product integrated by the first integrator, the second integrator current and second
A voltage proportional to the product of the first input signal voltage and the second human power No. 1g voltage is applied to the output terminal of the second integrator, that is, the fifth terminal. Then, the first switch and the second switch are made non-conducting, the integration of the first integrator and the second integrator is stopped, and the above procedure is repeated until the next sampling period. An analog multiplier pivoting method characterized by holding.