JPS5831423A - Constant-voltage circuit - Google Patents

Constant-voltage circuit

Info

Publication number
JPS5831423A
JPS5831423A JP13052381A JP13052381A JPS5831423A JP S5831423 A JPS5831423 A JP S5831423A JP 13052381 A JP13052381 A JP 13052381A JP 13052381 A JP13052381 A JP 13052381A JP S5831423 A JPS5831423 A JP S5831423A
Authority
JP
Japan
Prior art keywords
voltage
circuit
transistor
output
amplifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13052381A
Other languages
Japanese (ja)
Inventor
Masahiro Tamae
田前 正博
Hideharu Tezuka
手塚 秀春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13052381A priority Critical patent/JPS5831423A/en
Publication of JPS5831423A publication Critical patent/JPS5831423A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is DC
    • G05F3/10Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/18Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using Zener diodes

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PURPOSE:To reduce the voltage loss between I/O terminals and stabilize the operation of a control circuit by preventing the control circuit from the generation of oscillation even if p-n-p type transistors for the supply of constant- voltage are used. CONSTITUTION:A circuit for starting and controlling transistors (TRs) consists of a starting circuit 31, a control circuit 32 and a standard voltage circuit 33. When voltage is applied to an electric power source input terminal VIN in the starting circuit 31, a TR39 is turned on and the voltage of an output terminal is increased. When the voltage of the output terminal reaches a prescribed value, the TR39 is turned off. The control circuit 32 consists of an differential amplifier 43 for inputting the voltage obtained by dividing the output voltage through a resistor and standard voltage and plural steps of inversion type amplifier circuits for amplifying the output of the differential amplifier. The voltage of a terminal 18 is kept at a fixed voltage VCC by turning on/off TRs 51, 52.

Description

【発明の詳細な説明】 本発明は電源ラインの入力端側で電圧変化があっても電
源ラインの出力端側で一定化された電圧が得られるよう
にした定電圧回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant voltage circuit that can obtain a constant voltage at the output end of a power supply line even if there is a voltage change at the input end of the power supply line.

第1図は従来の定電圧回路図であシ、1は電源ラインの
入力電圧V□Nを一定化した電圧V、。。
FIG. 1 is a conventional constant voltage circuit diagram, where 1 is a voltage V that is made constant from the input voltage V□N of the power supply line. .

を得るためのNPN型トランジスタ、2はその制御を行
なうオペアンプである。抵抗3と定電圧ダイオード4か
ら得る定電圧性、オペアンプ2の非反転入力となシ、出
力電圧V。。、を抵抗5゜6で分割した電圧がオペアン
プ2の反転入力となる。
2 is an operational amplifier for controlling the NPN transistor. Constant voltage property obtained from resistor 3 and constant voltage diode 4, non-inverting input of operational amplifier 2, output voltage V. . , divided by a resistor of 5°6 becomes the inverting input of the operational amplifier 2.

上記のように従来の定電圧回路は、定電圧供給用トラン
ジスタ(外付)IKNPN’ll’に用いて□いたため
、電源ラインの入出力地間のロス電圧は一般に:2V以
上になりでしまい、例えばV。。7に5Vt−出したい
時■1)Iは7v以上必要となるものであった。ところ
で上記トランジスタ1にNPN型を用いるのは、ペース
とニオ、タ出力側が互に同位相関係にあるため、発振が
生じにくい構成となるからである。これに対し上記トラ
ンジスタにPNP型を用いると、ペースとコレクタ出力
側が互に逆位相の関係となって発振の原因となシ、これ
をとめるためにはコンデンサ7會大型化するがどの考慮
が必要でありた。
As mentioned above, the conventional constant voltage circuit uses the constant voltage supply transistor (external) IKNPN'll', so the loss voltage between the input and output of the power line is generally 2V or more. , for example V. . When you want to output 5Vt- to 7. ■1) I requires 7v or more. By the way, the reason why an NPN type transistor is used for the transistor 1 is that the output sides of the transistor 1 are in the same phase relationship with each other, so that the configuration is such that oscillation is difficult to occur. On the other hand, if a PNP type transistor is used as the above transistor, the pace and collector output sides will be in an antiphase relationship with each other, which will cause oscillation. It was.

本発明は上記実情に鑑みてなされたもので、定電圧供給
用トランジスタにPNP型を用いても発振が生じないよ
うな該トランジスタの制御回路を得ることによシ、前記
トランジスタの入出力端間電圧ロスを少なくシ、また該
トランジスタの出力側に設けられるコンデンサを小型化
でき、また前記制御回路の電源を前記トランジスタの出
力端側から得ることによシ、前記制御回路の安定動作が
可能となる定電圧回路を提供しようとするものである。
The present invention has been made in view of the above circumstances, and by providing a control circuit for a constant voltage supply transistor that does not cause oscillation even if a PNP type transistor is used, it is possible to By reducing voltage loss, by downsizing the capacitor provided on the output side of the transistor, and by obtaining power for the control circuit from the output end of the transistor, stable operation of the control circuit is possible. The purpose of this invention is to provide a constant voltage circuit.

以下図面を参照して本発明の一実施例を説明する。第2
図において11は電源ツインの入力′電圧vxMt−一
定化した電圧V。。?を得るためのPNP′fJト、ラ
ンジスタであり、12は該トランジスタ11の起動及び
制御回路であり、この回路12は集積回路で構成される
。上記トランジスタ11のエミッタ側は、抵抗13を介
して集積回路12の端子14と接続される。トランジス
タ11のエミッタ、ペース間は抵抗15を介して接続さ
れ、トランジスタ11のペースは、抵抗16を介して集
積回路12の端子17と接続される。トランジスタ11
のコレクタは集積回路12の端子18と接続され、骸端
子18と端子19は発振防止用コンデンサ10(介して
接続され、またトランジスタ11のコレクタはコンデン
サ21を介して接地されるC 第3図は集積回路12の詳細図であ)、これは起動回路
31、制御回路32、基準電圧回路33で構成されてい
る。起動回路31では、端子18と接地端子34関に抵
抗3!i、36が直列接続され、この抵抗35.16間
はトランジスタ310ベースに接続される。このトラン
ジスタ37の工之、夕は接地され、コレクタは抵抗S8
を介して端子14に接続される。またトランジスタJ1
のコレクタはトランジスタ390ペースに接続され、該
トランジスタ39のエミッタは接地される。
An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, 11 is the input voltage vxMt of the power supply twin - the constant voltage V. . ? 12 is a starting and controlling circuit for the transistor 11, and this circuit 12 is constructed of an integrated circuit. The emitter side of the transistor 11 is connected to a terminal 14 of the integrated circuit 12 via a resistor 13. The emitter of the transistor 11 and the paste are connected through a resistor 15, and the paste of the transistor 11 is connected to a terminal 17 of the integrated circuit 12 through a resistor 16. transistor 11
The collector of the transistor 11 is connected to the terminal 18 of the integrated circuit 12, the terminal 18 and the terminal 19 are connected via the oscillation prevention capacitor 10, and the collector of the transistor 11 is grounded via the capacitor 21. This is a detailed diagram of the integrated circuit 12), which is composed of a starting circuit 31, a control circuit 32, and a reference voltage circuit 33. In the starting circuit 31, a resistor 3! is connected between the terminal 18 and the ground terminal 34! i, 36 are connected in series, and the resistor 35.16 is connected to the base of the transistor 310. The terminal of this transistor 37 is grounded, and the collector is connected to a resistor S8.
It is connected to the terminal 14 via. Also, transistor J1
The collector of transistor 390 is connected to the base of transistor 390, and the emitter of transistor 39 is grounded.

制御回路32では、端子r it s j 4間に抵抗
3s e 40 カIiE 列接続され、また抵抗41
と定電圧ダイオード42が直列接続される。抵抗39゜
40間は差動増幅回路43の入力段素子44゜450入
力端に接続され、抵抗41を定電圧ダイオード42間は
差動入力段素子4 it e 4Fの入力端に接続され
る。差動入力段素子44.45のエミ、り、ペースは、
定電流源48t−介して端子18に接続され、入5力段
索子46e47のエミ、り、ペースは、定電流源49を
介して端子IIに接続され、入力段素子45.4’/の
共通エミ、りは定電流源50を介して端子18に接続さ
れる。入力段素子44.46のコレクタ。
In the control circuit 32, a resistor 3s e 40 is connected in a column between the terminals r it s j 4, and a resistor 41
and a constant voltage diode 42 are connected in series. The resistors 39 and 40 are connected to the input terminals of the input stage elements 44 and 450 of the differential amplifier circuit 43, and the resistor 41 and the constant voltage diode 42 are connected to the input terminal of the differential input stage element 4 it e 4F. The emitters, ri, and pace of the differential input stage elements 44 and 45 are:
It is connected to the terminal 18 through the constant current source 48t, and the output terminals of the input stage element 46e47 are connected to the terminal II through the constant current source 49, and the input stage element 45.4'/ The common emitter is connected to the terminal 18 via a constant current source 50. Collector of input stage element 44.46.

は接地され、入力段素子46 t 47のコレクタa−
’ttL−t’tL ) ”)7−)スl 61 、6
10−sVオクタ11l!される。該トランジスタJj
J 、 111のエミッタは接地され、該トランジスタ
の各ペース及びトランジスタ51のコレクタは共通接続
される・トランジスタ47.52のコレクタ間は非反転
増幅素子530ペース及び端子19に接続され、該素子
53のニオツタは非反転増幅素子54のペースに接続さ
れ、該素子53.54のコレクタ轢接地される。
is grounded, and the collector a- of the input stage element 46 t 47
'ttL-t'tL) ”)7-)sl 61,6
10-sV octa 11l! be done. The transistor Jj
The emitters of the transistors 47 and 111 are grounded, and the collectors of the transistors 53 and 51 are connected in common. The NIOTS is connected to the pace of the non-inverting amplification element 54, and the collectors of the elements 53 and 54 are grounded.

素子53.!54のエミッタ、ペース間は定電流源5・
5を介して端子18にamされ、素子54のニオツタは
定電流源5Cを介して端子xtnc*絖される・ トラ
ンジスタ51はそO工<y夕とトランジスタ54のエミ
ッタのノードaの電位を下げるための%のであり、該ト
ランジスタ610ペースは、端子11.34間に直列接
続され九抵抗i1.ダイオード59〜62の抵抗its
、ダイオード59間に接続されておシ、′トツンゾスタ
t;to:2レクタは端子11、また抵抗63を介して
トラ゛ン□ ジスタ39のコレクタIIC接続されてい
る。
Element 53. ! Between the emitter of 54 and the pace is a constant current source 5.
5 to the terminal 18, and the voltage of the element 54 is connected to the terminal xtnc* via the constant current source 5C. %, and the transistor 610 is connected in series between terminals 11.34 and 9 resistors i1. Diode 59-62 resistanceits
, and the diode 59, and the collector of the transistor 39 is connected to the terminal 11 and the collector IIC of the transistor 39 via a resistor 63.

このように構成された定電圧回路において、起動回路J
1では、電源入力端V□つに電圧がかかると、抵抗13
と抵抗38を介してトランジスタ19がオンする。する
と抵抗63.16を介して外付トランジスタ11がオン
し、出力端電圧V。□が上昇していく。このV。。、っ
ま〕集積回路12の電源vccが、抵抗ss、xttの
比で決t−)た電圧になると、トランジスタ11がオン
してトランジスタ39をオフさせる。即ち起動回路31
はI集積回路電源vcct成る程度上げるためのもので
、この電源vccが成る程度上がったら、トランジスタ
39がオフで切れてしまうが、電源Vccが未だ低なの
で、後述の制御回路動作によシ外付トランジスタ11t
−よ〕オン状態とするから、電圧V。IJ?=VCeは
一定電圧 ゛(例えば5v)4で上昇しつづける。上記
トランジスタS9がオフした際には、トランジスタ11
は制御回路32によってのみ制御される。
In the constant voltage circuit configured in this way, the starting circuit J
1, when a voltage is applied to the power input terminal V□, the resistor 13
The transistor 19 is turned on via the resistor 38. Then, the external transistor 11 is turned on via the resistor 63.16, and the output terminal voltage V. □ is rising. This V. . When the power supply vcc of the integrated circuit 12 reaches a voltage determined by the ratio of the resistors ss and xtt (t-), the transistor 11 is turned on and the transistor 39 is turned off. That is, the starting circuit 31
is used to raise the integrated circuit power supply Vcct, and when this power supply Vcc rises to the level that it reaches Vcct, the transistor 39 will turn off, but since the power supply Vcc is still low, an external transistor 11t
-) Since it is in the on state, the voltage is V. IJ? =VCe continues to rise at a constant voltage (for example, 5V)4. When the transistor S9 is turned off, the transistor 11
is controlled only by control circuit 32.

この制御回路32は、Vcc’に抵抗分割した電圧と基
準電圧とt入力とする差動増幅回路43と、咳回路43
の出力を増幅する複数段の非反転型増幅素子とからなる
オペアンプで構成されているlのためトランジスタ44
.46の(−スハ、オイアンプ動作にょシ同電位となる
。っまシダイオード42による基準電圧と、抵抗39゜
400比によって決まる電圧で、電圧vccが安定する
0例えば′端子18の電圧が上がろうとすると、トラン
ジスタ44,45のベース電圧が上がシ、トランジスタ
51.52がオフし、トランジスタ530ペース電圧、
トランジスタ63゜54の各エミッタ電圧、トランジス
タ51のコレクタ電圧が共に上昇し、端子18の電圧を
下げる。一方端子18の電圧が下がろうとすると、トラ
ンジスタ44.41;のペース電圧が下がシ、トランジ
スタ51.52がオンし、トランジスタ53のぺ一7ス
電圧、トランジスタ53.54の各エンツタ電圧、トラ
ンジスタ51のコレクタ電圧が下降し、端子18の電圧
を上げる。このようにして端子18は一定電圧vccで
安定するものである。
This control circuit 32 includes a differential amplifier circuit 43 which uses a voltage divided by resistance to Vcc', a reference voltage, and t input, and a cough circuit 43.
The transistor 44 consists of an operational amplifier consisting of multiple stages of non-inverting amplification elements that amplify the output of the transistor 44.
.. 46 (-sha, the same potential is used when the amplifier operates.) The voltage Vcc is stabilized by the reference voltage from the diode 42 and the voltage determined by the resistor 39°400 ratio. For example, when the voltage at terminal 18 rises, When the base voltage of transistors 44 and 45 rises, transistors 51 and 52 turn off, and the base voltage of transistor 530 increases.
The emitter voltages of the transistors 63 and 54 and the collector voltage of the transistor 51 both rise, lowering the voltage at the terminal 18. On the other hand, when the voltage at terminal 18 is about to drop, the pace voltage of transistors 44, 41; turns on, transistors 51, 52 turn on, and the pace voltage of transistor 53, the voltage of each terminal of transistors 53, 54, The collector voltage of transistor 51 decreases, increasing the voltage at terminal 18. In this way, terminal 18 is stabilized at a constant voltage vcc.

上記構成でなる定電圧回路は、制御回路s2の増幅回路
で位相が反転し々いようにしたから、発振が生じ[<く
なる。これによシ定電圧供給用トランジスタ11にPN
P型のものを用いることができ、電源ラインの入力端電
圧vル、出力端電圧■。。7間の電圧ロスを極少にでき
、例えばこの電圧ロスを、トランジスタ11の飽和電圧
分つまり O,i v程度と非常に小さくすることがで
きる。またこQ回路は発振しにくい構成だから、コンデ
ンサ21を小型化でき、従9て集積回路内に内蔵させる
ことも可能゛となる。また制御回路32の電源電圧ヲ主
記電源ラインの出力端側からとる構成で、電源電圧vc
cは入力端電圧v4に係わらず一定化されるから、制御
回路52t−安定した状態で動作させることができ−る
。−なお本発明は上記実施例のみに限定されるものでは
なく、例えば定電圧供給用トランジスタ11f集積回路
内に設けたシ、非反転増幅回路も、素子53.54の2
段にこだわらない等、種々の応用が可能である。
In the constant voltage circuit having the above configuration, since the phase is often inverted in the amplifier circuit of the control circuit s2, oscillation occurs. As a result, the constant voltage supply transistor 11 has a PN
A P-type type can be used, and the input end voltage of the power supply line is ν, and the output end voltage is . . The voltage loss between the transistors 7 and 7 can be minimized, and for example, this voltage loss can be made very small to about the saturation voltage of the transistor 11, that is, about O,iv. Furthermore, since this Q circuit has a structure that is difficult to oscillate, the capacitor 21 can be made smaller and can also be built into an integrated circuit. In addition, the power supply voltage of the control circuit 32 is taken from the output end side of the main power supply line, and the power supply voltage vc
Since c is kept constant regardless of the input terminal voltage v4, the control circuit 52t can be operated in a stable state. - Note that the present invention is not limited to the above-mentioned embodiments; for example, the non-inverting amplifier circuit provided in the constant voltage supply transistor 11f integrated circuit may also be used as a non-inverting amplifier circuit.
Various applications are possible, such as regardless of the stage.

以上説明した如く本発明によれば、定電圧供給廟ゝ−ラ
ンジスタにPNPWOもの音用いても発振が生じない制
御回路としたから、前記トランジスタの入出力端間電圧
のロスが少なくできると共に、出力端側コンデンサを小
型化でき、また前記制御回路の電源を前記トランジスタ
の出力端側から得るようにしたので、制御回路の安定動
作が可能となる等の利点を有した定電圧回路が提供でき
るものである。
As explained above, according to the present invention, since the control circuit does not cause oscillation even if PNPWO is used for the constant voltage supply transistor, the voltage loss between the input and output terminals of the transistor can be reduced, and the output It is possible to provide a constant voltage circuit which has advantages such as the capacitor on the end side can be miniaturized and the power supply for the control circuit is obtained from the output end side of the transistor, so that stable operation of the control circuit is possible. It is.

【図面の簡単な説明】[Brief explanation of drawings]

編1図は従来の定電圧回路図、謳2図は本発明の一実施
例の回路図、第3図は開回路O一部詳細図である。 11・・・PNP ! )ランジスタ、31・−起動回
路、32−制御回路、33・・・基準電圧回路、39゜
40・・・電圧分割用抵抗ζ 43・・・差動増幅回路
、53.54・・・非反転型増幅素子。
Figure 1 is a conventional constant voltage circuit diagram, Figure 2 is a circuit diagram of an embodiment of the present invention, and Figure 3 is a partially detailed diagram of an open circuit. 11...PNP! ) Transistor, 31 - Startup circuit, 32 - Control circuit, 33 - Reference voltage circuit, 39° 40... Voltage division resistor ζ 43 - Differential amplifier circuit, 53.54 - Non-inverting type amplification element.

Claims (2)

【特許請求の範囲】[Claims] (1)電源ツインの入出力端間に介挿されるPNP型ト
ランジスタと、前記出力端電圧に応じた電圧と基準電圧
を入力とし前記トランジスタのペースを制御する差動増
幅回路と、該増幅回路の出力端と前記トランジスタのベ
ース間に介挿され前記差動増幅回路C・出力を増幅する
非反転製増幅回路とを具備したことを特徴とする定電圧
回路。
(1) A PNP transistor inserted between the input and output terminals of the power supply twin, a differential amplifier circuit that inputs a voltage corresponding to the output terminal voltage and a reference voltage and controls the pace of the transistor, and the amplifier circuit. A constant voltage circuit comprising: a non-inverting amplifier circuit inserted between an output terminal and the base of the transistor to amplify the differential amplifier circuit C and the output.
(2)電源ラインの入出力端間に介挿されるPNP、[
)ランジスタと、前記出力端電圧に応じた電圧と基準電
圧を入力とし前記トランジス、りのペース會制御する差
動増幅回路と、該増幅回路の出力端とf前記トランジス
タのペース間に介挿され前記差動増幅回路の出力を増幅
する非反転製増幅回路と、該増幅回路及び前記差動増幅
回路の電源電圧を前記電源ラインの出力端から得る手段
と、前記電源ラインの起動時に前記トランジスタを駆動
して前記電源ツインの出力電圧を上げる起動回路とを具
備したことを特徴とする定電圧回路。
(2) PNP inserted between the input and output ends of the power supply line, [
) a differential amplifier circuit that receives a voltage corresponding to the output terminal voltage and a reference voltage as input and controls the pace of the transistor; and a differential amplifier circuit that is inserted between the output terminal of the amplifier circuit and the pace of the transistor. a non-inverting amplifier circuit for amplifying the output of the differential amplifier circuit; means for obtaining a power supply voltage for the amplifier circuit and the differential amplifier circuit from an output end of the power supply line; A constant voltage circuit comprising: a starting circuit that drives to increase the output voltage of the power supply twin.
JP13052381A 1981-08-20 1981-08-20 Constant-voltage circuit Pending JPS5831423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13052381A JPS5831423A (en) 1981-08-20 1981-08-20 Constant-voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13052381A JPS5831423A (en) 1981-08-20 1981-08-20 Constant-voltage circuit

Publications (1)

Publication Number Publication Date
JPS5831423A true JPS5831423A (en) 1983-02-24

Family

ID=15036327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13052381A Pending JPS5831423A (en) 1981-08-20 1981-08-20 Constant-voltage circuit

Country Status (1)

Country Link
JP (1) JPS5831423A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50136654A (en) * 1974-04-19 1975-10-30
JPS553339B2 (en) * 1976-06-10 1980-01-24

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50136654A (en) * 1974-04-19 1975-10-30
JPS553339B2 (en) * 1976-06-10 1980-01-24

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