JPS5831465A - Processor controlling system - Google Patents

Abstract

PURPOSE:To easily execute execution start and stop control between mutual processors even in case of those which have fixed their circuits, by providing a common memory of a main control processor and a processor to be controlled, and a controlling circuit for sending out a control signal to the processor to be controlled, in accordance with a control order from the main control processor. CONSTITUTION:This system is provided with a common memory 31 to which a main control processor (MPU) 1 and MPUs 2, 3 to be controlled are capable of accessing, and a controlling circuit 33 for decoding a control order of the MPU 1 and applying an interruption signal and a reset signal to the MPUs 2, 3. This controlling circuit 33 generates a reset signal to the MPUs 2, 3 in accordance with a start order of the MPU 1, the MPUs 2, 3 execute start processing from a specific address, read out information of a specific area of the memory 31 at the time of stop, set it as an internal state at the time of start, and shift to an execution state. Also, the controlling circuit 33 generates an interruption which cannot be inhibited, to the MPUs 2, 3 in accordance with a stop order of the MPU 1, and the MPUs 2, 3 execute stop processing, write an internal state at the time of the interruption in a specific area of the memory 31, and shift to a stop state after it has been accumulated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processor control method, and more specifically, a multiprocessor system is configured using processors (such as microprocessors) that do not have multiprocessor functions, and a controlled processor is controlled from a main control processor. This relates to a processor control method.

Conventionally, multiprocessor systems have been configured using processors having functions such as start and stop control between processors and direct transfer between registers, and channels for communication between processors. However, recently, low-cost small processors, or microprocessors, have been used in circuits that were conventionally configured with wired logic to perform signal processing and preprocessing as signal processors or front-end processors, which has improved economic efficiency and system flexibility. Multiprocessor systems, which aim to reduce processing speed and main processor load, have been attracting attention as a promising method.

However, since microprocessors do not have a control function between processors, these systems have loose coupling between individual processors and take over information necessary for processing by data transfer between memories.

However, in systems that require high reliability, such as switching systems, when a failure occurs, it is difficult to stop processing, execute failure handling,
Alternatively, it is necessary to quickly switch to a redundant system. Therefore, even in processors and microprocessors that do not have multiprocessor control functions, it is desirable to be able to perform start and stop control and direct transfer between registers between processors, but since the circuits are usually fixed, It is impossible for the user to change the circuit +
be. Furthermore, the start/stop control system using a processor having a processor control function and channel control requires a large amount of hardware, is expensive, and has the drawback of requiring complicated control.

In order to eliminate such drawbacks, the purpose of the present invention is to enable easy start and stop control between processors even in processors with fixed circuits, and to provide a concrete implementation thereof. The objective is to provide an economical method.

In the following, a method for controlling a microprocessor from a main control processor will be described as a typical example of controlling one processor. Generally, a μP has interrupts and resets as functions that can be used to externally control a microprocessor (hereinafter abbreviated as μP). Interrupts include maskable interrupts (hereinafter referred to as maskable interrupts) that can be controlled by a microprocessor program.
In many cases, these interrupts have a main maskable interrupt (hereinafter referred to as NMI), which cannot be disabled in the program. In addition, the reset function is to clear the internal registers of the μP using a reset signal and perform initial settings, and then start executing the program from a specific address (for example, address "0"). The present invention realizes start and stop control using these functions.

FIG. 1 is a block diagram of an embodiment of the present invention, where l is a main control processor, 2 and 3 are non-inhibitable interrupts (NMI and RESET), and μP111 is a memory that stores the program of the main control processor l. , 12 and 13 are memories that store programs for μP2 and 3, respectively, 31 is a common memory that can be accessed from each of the main control processors 11μP2 and 3, 32 is a common memory access control circuit, and 21, 22, and 23Fi are main control processors, respectively. 1
Memory 11, 12 by control information from 1μP2, 3
．． 13 is a memory access control circuit that branches and controls access to the common memory 31, and 33 is a μP control circuit that sends control signals to μPs 2 and 3 according to control orders from the main control processor l.

In the common memory 31, as shown in FIG. 2(a), a specific area (hereinafter referred to as system area) in which the internal information of the μP is to be set is defined corresponding to the μP. In the system area, after temporarily suspending processing, all information necessary to return to the state immediately before the suspension and continue processing is set. An example of information set in the system area and area allocation is shown in FIG. 2(b).

First, in response to a start order from the main control processor 1, the main control processor 1 performs an operation to start μP2 and 3 before issuing a start order to PP2.
The initial value to be set in the various registers of μP2 and μP3 is set in each system area of the common memory 31.

That is, the main control processor 1 sends a system area address, data to be set in the system area (for example, a start address), and a write signal to the memory access control circuit 21 as a memory access request via the memory bus 101. The memory access control circuit 21 identifies that the access is to the common memory 31 from the address information, and sends the access request address, data, and write signal to the common memory access control circuit 32 via the common memory access line 102. . The common memory access control circuit 32 responds to the access request when no other processor is using the common memory 31 and there is no common memory access request from another processor, or when there is an access request from another processor. However, if the access request from the main control processor 1 is recognized by contention control, the access request from the main control processor 1 is accepted. Note that in cases other than the above, the common memory access is queued, and the access is granted when the use of the common memory by other processors is completed. When the common memory access control circuit 32 receives an access request, the common memory access control circuit 32
A write signal is sent to the common memory 31 via the common memory bus 103. The common memory 31 writes data to the corresponding system area based on the address. The main control processor 1 sequentially repeats common memory access and sequentially sets the start address and initial values of various registers required for μP start in the corresponding system area of the common memory 31.

After completing the information setting to the system area, the main control processor 1 transfers the μP start order to the input/output bus 10.
4 to the μP control circuit 33.

In addition, the μP to be started is included in the μP start order.
number or all μP start instruction information is included. μ
The P control circuit 33 starts μ based on the order.
A reset signal is sent to P2 or P3 for a predetermined timing. For example, when starting μP2, a low level (logic "1") is sent to the reset signal line 11'2, which becomes high level (logic "0") after a predetermined timing. By inputting a low level to the RESBT terminal of μP2, the program counter (PC) of μP2,
The I register and interrupt mask (IFF) are cleared. Furthermore, by inputting a high level after a predetermined timing, μP2 starts execution from address 0'' in memory 12. In other words, the start processing program is stored from address ``!O'' in memory 12, and μP2 Execute the start processing program. The start processing program is as shown in Fig. 3, and μP2 is stored in common memory 3.
After setting the values stored in system area 1 in various registers, storing the start address in the stack area indicated by the stack pointer (SP), and setting based on the value in the IFF area, return (RET). The start address stored in the stack area is transferred to the PC by an instruction.
to jump to the start address. In addition, μP2
Access to the system area of the common memory 31 from
゛The access procedure is the same as that of the main control processor 1 described above. However, in the case of reading, a read signal is sent out instead of a write signal. Further, the start processing program does not need to be stored continuously at address "0" of the memory 12, and the storage area may be determined taking into consideration the convenience of memory usage. However, the beginning of the start processing program is at address "0".

To start μP3, specify μP3 with a μP start order from the main control processor 1, and based on the order, the μP control circuit sends a reset signal to the reset signal line 122. This can be realized using exactly the same procedure as the start of μP2 described above. Note that the system area of the common memory 31 uses the system area associated with μP3.

In addition, in order to start μPs 2 and 3 at the same time, the μP start order from the main control processor 1 specifies simultaneous start, and the μP control circuit simultaneously sends reset signals to the reset signals 112 and 122 based on the order. This can be achieved using the same procedure.

However, in this case, it is necessary for the common memory access control circuit 32 to control conflicts between access requests to the common memory 31 issued independently from μPs 2 and 3.

Next, according to the stop order from the main control processor l,
The operation when stopping μP2 and μP3 will be explained.

The main control processor l sends a μP stop order including the μP number or all μP designation information to the μP control circuit 33 via the input/output bus 104. μP control circuit 33 sends a μPKNMI signal to stop based on the taste kernel order. For example, when a μP2 stop order is received, a low level (logic "1") is sent to the NMI signal line 111. When a low level was input to the NMI terminal, μP2 accepted the NMI interrupt when the currently executed instruction was finished, and stored the contents of the PC in the stack area specified by SP (hereinafter referred to as the stored PC). The value of PCo
After that, set 66H on the PC and jump to address 66H. A stop processing program is stored from address 66H in the memory 12, and μP2 starts at address 66H.
”The stop processing program is executed from the address. The stop processing program is as shown in Figure 4, and μP2 stores the contents of various registers of PCo1 stored in the start square area and the interrupt mask status in the system area. , Hall) (HALT) command to enter the halt state. □ To stop μP3, specify μP3 with the μP stop order from the main control processor l, and then execute the μP control circuit 33 based on the order. is connected to the NMI signal line 121.
By sending the I' signal, stopping of μP2 can be achieved in exactly the same procedure as described above.

To stop μPs 2 and 3 at the same time, specify all μP stops using the μP stop order of the main control processor 1, and then simultaneously send the NMI signal to the μP control circuit or NMI signal lines 111 and 121 based on the order. This can be achieved using the same procedure by sending the data.

Note that stop is often used in emergencies such as handling system failures, so it is appropriate to use NMI interrupts for stop control. For the processor used, the above-mentioned stop control can be realized using an INT interrupt, with the restriction that stop interrupts are always enabled. That is, based on the μP stop order from the main control processor l, the μP control circuit 33 sends an INT interrupt signal for stopping to μP2 or μP3, and μP2 or μP3 sets an interrupt mask using the INT interrupt signal and stacks the PC. After storing it in the area, it jumps to a specific address, executes the stop processing program, and enters a halt state. Next, based on the start order from the main control processor, the controlled processor executes the start processing program, releases the stop interrupt mask in the start processing, that is, makes interrupts possible, and then jumps to the start address. From then on,
It is prohibited to set a stop interrupt mask during processing execution.

However, this prohibition is not specified by the circuit;
Rules regarding processor usage and soil usage.

Next, start control using an INT interrupt without using a reset will be explained. For processors that do not have a reset start function or when using reset for other purposes such as 5-war-on reset, by providing a start interrupt and allowing only the start interrupt to be interrupted by the above-mentioned stop processing program, (2) The above start control can be realized using the NT interrupt. That is, based on the μP stop order from the main control processor 1, μP
2 or μP3 executes the above-mentioned stop processing program, and after canceling the start interrupt mask (that is, allowing only the start interrupt), enters the halt state. Next, based on the start order from the main control processor, the μP control circuit either μP2 or μ
Sends a start interrupt signal to P3. μP2 or μP3 jumps to a specific address in response to the signal, executes the start program/ring program, and jumps to the start address.

Regarding the extension of INT interrupt, stop control K
This can be achieved in the same way as when using an INT interrupt.

Next, restarting from the interruption point will be explained. Generally, in a system using a processor, when a situation requiring emergency control such as troubleshooting occurs, processing is temporarily interrupted, the emergency processing is executed, and then processing is resumed from the point of interruption. With this method, it is possible to easily realize control for restarting the controlled processor from the point of interruption. That is, when an emergency situation occurs, the main control processor l sends out a stop order and stops the controlled processor of μP2 or 3. The controlled processor stores the internal information in the corresponding system area of the common memory 31 based on the order, and then enters the complete state.

The main control processor l confirms that the controlled processor has stopped, moves the internal information stored in the system area of the common memory 31 to the evacuation area, sets the information necessary for emergency processing in the corresponding system destination area, and then issues a start order. Starts the controlled processor by sending . The controlled processor internally sets the information stored in the corresponding system area of the common memory 31 based on the order, and executes the emergency processing program. After completion of execution, the completion is reported to the main control processor l via, for example, the common memory 31, and the CPU enters a halt state either autonomously or by a stone or order from the main control processor l. After confirming the completion of execution and halt of the controlled processor, the main control processor l moves the internal information of the controlled processor stored in the save area of the common memory 31 to the corresponding system area,
A start order is sent to start the controlled processor. Based on the order, the controlled processor reads the internal information at the time of interruption from the system area of the common memory 3, sets it internally, and performs metadata to resume the interruption point.

As explained above, according to the present invention, when configuring a multiprocessor using a processor such as μP that does not have a multiprocessor function, the user can start the processor by simply adding a common memory and a simple circuit. , stop control and interruption point restart control are possible, so there is an advantage that even in systems that require high reliability, a multiprocessor can be easily configured using μP or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) and Φ) are diagrams showing an example of the system area set in the common memory in FIG. 1, FIG. 3 is a flowchart showing an example of a start processing program, and FIG. 4 is a flowchart showing an example of a stop processing program. . 1... Main control processor, 2, 3... Microprocessor, 11, 12.13... Memory, 21, 22
．． 23...Memory access control circuit, 31...Common memory, 32...Common memory access control circuit, 33
... microprocessor control circuit, lOl... memory bus, lO2... common memory access line, 103.
... Common memory bus, 104 ... Input/output bus, Ill
, 121...Reset signal line. Figure 1 [ 0 [ ) 1 Illusion 2 ('s Figure 3 Figure 4

Claims (1)

[Claims] 1. Consisting of a plurality of processors of the same type or different types that do not have a special multiprocessor control function, the main control processor starts execution of the controlled processor,
In a system that controls a stop, a common memory that can be accessed by both the main control processor and the controlled processor, and a processor control that decodes control orders from the main control processor and provides an interrupt signal or a reset signal to the controlled processor. When the main control processor sends a controlled processor start order to the processor control circuit, the processor control circuit generates a reset signal to the controlled processor based on the order, and the controlled processor Special 1 A start processing program is executed from a fixed location, and when the program is stopped, the internal information stored in advance in a specific area of the common memory or the start information set in advance in a specific area of the common memory by the main control processor is read from the common memory, and the When the main control processor sends a controlled processor stop order to the processor control circuit by setting the information as the internal state at the start and moving from the stop state to the running state, the processor control circuit controls the controlled processor based on the order. generates an interrupt that cannot be prohibited, the controlled processor executes a stop processing program by the interrupt, writes and stores the internal state at the time of the interrupt in a specific area of the common memory, and then changes from the running state to the stopped state. A processor control method characterized by shifting. 2. In the processor control method according to claim 1, when transitioning from an execution state to a stop state based on a stop order from the main control processor, the controlled processor can accept only a start interrupt, A processor control method characterized in that a processor control circuit generates a start interrupt to a controlled processor based on a start order from a main control processor, and the controlled processor executes a start processing program in response to the start interrupt.