JPS61101868A - Masking system of mutual interruption for duplex processor - Google Patents

Abstract

PURPOSE:To enable two systems to operate simultaneously in sharing the processing, to easily mask mutual interruptions and to simplify the control of queuing by enabling two processors to interrupt mutually in a equal condition. CONSTITUTION:Each of the system processors 1A and 1B is connected to a bus change-over 2. By the change-over 2, the processors 1A and 1B are connected, in time division, to the bus, and fetch the instructions stored in a storage 3 and execute. The interruption registers 4A and 4B operated by FFs connected to the bus, apply interruption to the processors 1A and 1B which are supplied to ANDs 6A and 6B. By the first and second interruption mask registers 5A and 5B connected to the bus, the status of the processors 1A and 1B is set, and the signal to suppress the output of the interruption signals from the registers 4A and 4B, is outputted and supplied to the ANDs 6A and 6B. By the outputs from the circuits 6A and 6B, the input terminals 7A and 7B of the processors 1A and 1B are controlled, so that the control of queuing is simplified.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a mutual interrupt mask control method in dual processors, particularly in a system of dual processors, in which each processor can mutually raise interrupts, and each processor can mutually raise interrupts. The present invention relates to a mutual interrupt mask control method in dual processors that can mask interrupt requests of two processors.

[Conventional technology and problems]

For example, a dual processor system is being considered in which two microprocessors use an address bus and a data bus in a time-sharing manner, and these two processors share one function and execute programs at different addresses. . A memory storing a firmware program for controlling this system is connected to a common bus used in the above-mentioned time division.

Conventionally, in a system similar to this one, one processor was the master and the other was the slave, and the slave side raised an interrupt to the master side to notify the master processor of the completion of processing by the slave processor. There is something to do. However, this does not raise interrupts to each other, and therefore it is not possible to operate the two processors equally. Furthermore, when constructing a system in which one processor requests processing to another processor via an interrupt, and the acceptance of the processing request is known via an interrupt from the other processor, a large number of interrupt requests occur at once. In this case, it is necessary to operate a so-called queue, but the control of the queue becomes complicated due to the occurrence of multiple interrupts, which poses a problem in that there is a risk of miscontrolling the queue.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems, and allows two processors to issue interrupts equally to each other using a relatively simple circuit, and also allows each processor to mask interrupts to either of them. To provide a means for easily constructing a system in which two systems share processing and operate simultaneously, each raising an interrupt and requesting processing to the other. That is, in the mutual interrupt mask control method in a dual processor of the present invention, which includes a first processor and a second processor that share a bus, the mutual interrupt mask control method in a dual processor according to the present invention is based on a state setting by the processor. a first interrupt register that instructs the first processor to raise an interrupt; a first interrupt mask register that suppresses output of an interrupt signal by the first interrupt register according to a state setting by the processor; a second interrupt register that instructs the second processor to raise an interrupt based on a state setting; and a second interrupt mask register that suppresses output of an interrupt signal by the second interrupt register based on a state setting by the processor. It is characterized by having the following. An embodiment will be described below with reference to one drawing.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining bus switching, and FIG. 3 shows an example of a channel device to which the present invention is applied.

Processor IA and processor IB are processing devices that sequentially fetch and execute instructions stored in memory 3 according to the values of program counters, which are internal registers. The bus switching circuit 2 is configured as shown in the time chart shown in FIG. 2, for example.

At predetermined time intervals, the processor IA and the bus
, or a multiplexer that alternately switches the connection between the processor IB and the bus BUS. This allows the processors IA and IB to use the buses BUS, such as the data bus and the address bus, without time-sharing conflicts.

The memory 3 is constituted by a read-only memory (ROM) and/or a random access memory (RAM), and has instructions and data stored at predetermined addresses.

Interrupt register 4A is 2, for example processor IB is “1”
This register instructs the processor IA to raise an interrupt by writing , and is composed of a flip-flop to which a predetermined address similar to the address of the memory 3 is assigned in advance. Similarly, 1 interrupt register 4B is 9, for example, processor IA is “1”.
This register instructs the processor IB to raise an interrupt by writing ", and is composed of a flip-flop to which a predetermined address similar to the address of the memory 3 is assigned in advance.

The interrupt mask register 5A is set to 1. For example, since the processor IA is controlling the queue, when attempting to prohibit interrupts to the processor IA, it is set to "0" in advance.
This is a mask register that suppresses the output of an interrupt signal by the second interrupt register 4A by writing. 2 interrupt mask register 5A when the queue operation is completed.
If "1" is written to "1", the 1-interrupt prohibition is canceled, and if the interrupt register 4A is "1" at this time.

Gives an interrupt signal to processor IA. Like the interrupt register 4A, the interrupt mask register 5A is composed of a flip-flop to which a predetermined address is assigned.

The NAND circuit 6A performs the logical sum of the output of the 9-interrupt register 4A and the output of the interrupt mask register 5A, and only when these outputs are both "1", the processor IA
to interrupt input terminal 7A.

Supply a “0” level interrupt signal. As is well known, for example, when a "0" level signal is transmitted to the interrupt input terminal 7A, the so-called vector address stored at a predetermined address in the memory 3 controls the interrupt processing routine corresponding to each of the nine interrupt levels. is now transitioning.

Interrupt mask register 5B is 9 interrupt mask register 5
．． A mask register similar to A and processor IB
Flip j to disable interrupts.

It's a flop. NAND circuit 6B, interrupt input terminal 7B
Also, they are the same as the NAND circuit 6A and the interrupt input terminal 7A, respectively, and function similarly to the processor IB.

The present invention can be applied not only to an independent system but also to a system using a microprocessor within a channel device that performs line control, for example.

FIG. 3 shows an embodiment in which the present invention is applied to a channel device. In FIG. 3, the symbols IA and IB correspond to those in FIG. 10 is the central processing unit (CPU) of the host.
), 11 is a main bus, 12 is a channel device, 13 is a host interface section, 14 is a buffer memory, 15 is a line interface section, and 16 is a communication line using, for example, an R3232C inkface.

The processor 1A, which is a microprocessor, mainly controls the interface with the host CPU 10, and the processor IB mainly controls the line side interface. The line interface section 15 is an input/output LSI equipped with external registers for controlling the 9-time i' line.
It is now possible to control transmission and reception for the line.

For example, when transmitting data, the CPU 10 sets a transmit command in the register of the host interface unit 13 and provides the buffer memory 14 with the transmit data. In response to this transmission request, processor LA writes "1" to interrupt register 4B shown in FIG. 1 to interrupt processor IB and request transmission. In response to this transmission request, processor IB sends the data read from buffer memory 14 to line 16 via two-line interface section 15. When the data in the buffer memory 14 becomes empty, the processor IB.

Write “1” to the illustrated interrupt register 4A in FIG.
Raises an interrupt to processor IA and notifies processor IA of completion of processing.

Similarly, when receiving data, processors IA, IB
Processing requests and completion notifications are made by mutual interruption between the two parties.

Incidentally, since one, for example, four lines are controlled at the same time, a large number of such processing requests may occur at the same time. Therefore, processors IA and IB create a queue of interrupt requests.

Sequentially, requests at the head of the queue cause one interrupt to be raised. When there is an interrupt indicating that the interrupt has been accepted, the request at the head of the queue is removed from the first queue and the interrupt is raised by the second request. At this time, when working with queues, ie when performing so-called queuing or dequeuing operations on requests.

If there is an interrupt from the other processor, it is easy to miscontrol the queue. According to the present invention, when starting queue control, "0" is written only while the queue is being operated using the interrupt mask register 5A or interrupt mask register 5B shown in FIG. Because you can disable interrupts.

Processing can be performed without erroneously controlling the queue.

Traditionally, generally by disabling all interrupts.

In some cases, the queue was controlled, but if interrupts from external sources such as lines are prohibited, errors such as data overruns may occur.

According to the present invention, since it is possible to selectively mask only one interrupt with respect to mutual interrupts between processors, the degree of freedom in two-interrupt control is increased.

〔Effect of the invention〕

As explained above, according to the present invention, two processors can equally issue interrupts to each other.
It is now possible to easily build a system in which two systems share processing and operate simultaneously, each raising interrupts and requesting processing from the other, and each processor can easily mask interrupts from each other. Therefore, it becomes possible to easily control the queue.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining bus switching, and FIG. 3 shows an example of a channel device to which the present invention is applied. In the figure, IA and IB are processors, 2 is a bus switching circuit, 3 is a memory, 4A, 4B are interrupt registers, 5A, 5
B is an interrupt mask register, 6A. 6B represents a NAND circuit, and 7A and 7B represent interrupt input terminals. Patent applicant Panafacom Co., Ltd. Representative Patent Attorney Hiroshi Mori 1) (and 1 other person) Figure 1 Figure 2 Figure 1 ----------÷ Figure 3

Claims (1)

[Claims] In a mutual interrupt mask control method in a duplex processor including a first processor and a second processor that share a bus, a first processor instructs the first processor to raise an interrupt based on a state setting by the processor. an interrupt register; a first interrupt mask register that suppresses output of an interrupt signal by the first interrupt register according to a state setting by the processor; and a first interrupt mask register that suppresses output of an interrupt signal by the first interrupt register according to a state setting by the processor; A mutual interrupt mask in a dual processor, comprising: a second interrupt register for instructing; and a second interrupt mask register for inhibiting output of an interrupt signal by the second interrupt register according to a state setting by the processor. control method.