JPS583184A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent malfunction without losing readout speed, by delaying a readout current flowing to a cell at the transient state reading out the cell of opposite content. CONSTITUTION:A collector of transistors (TR) TR Qg and Qh is connected to a reference power supply line VREF via a load circuit consisting of resistors R1 and R2 and diodes D1 and D2, and a load circuit of the TRQg is connected to the base of a TRQh, and the load circuit of the TRQh is connected to the base of the TRQg respectively. The anode of diodes D3 and D4 is connected to the bit line side between bit lines Bphi and B1 and the emitter of the TRsQg and Qh. At the transient state from a cell C2 having inverting information to a cell C1, since no readout current IR flows to the bit line Bphi, miswriting to the cell C1 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an integrated injector W
RAM (Random Access Memory) K uses RAM (Random Access Memory), which uses RAM (Random Access Memory) with
! The present invention relates to a semiconductor memory device that prevents reading malfunctions by preventing current from flowing through an accessed cell for a certain period of time.

In the I''LL cell, the start-up and fill-in are controlled by the current value IB supplied by the bit width VC. That is, if the write threshold current is Iwth, the following equation is obtained.

・When threading: I, = I□〈Iwth...
・・ ■When writing” ■B='W,>Iwtn
'...... ■1 Normally, the current IO flowing through the cell is Ia when not selected < IO when selected. It is better to have as large an IR as possible from the point of view of increasing the speed of continuous output, but if ■8 is made large, the above-mentioned margin of successive output will deteriorate. Roughly speaking, in a transient state from non-selection to selection, a DC-like current flows and the margin of equation 0 tends to become smaller.

In the conventional circuit, the bit line current flows through the selected cell at the time of access.
It doesn't come close with a large setting. Namely.

There has been a rare problem that there is a risk of malfunction due to continuous printing, in which the cells are reversed in the continuous printing state.

In order to avoid the d-output malfunction, conventionally the readout current has to be reduced, and the reduction in the d-output' current impairs the readout speed.

The purpose of the present invention is to solve the above-mentioned problem of the line setting malfunction in the conventional circuit and the reduction in readout speed, and in a transient state where a cell with the opposite content is lined up, the purpose of the present invention is to: , 14Ifj The time point rl when the line flow to the cell about to be set = tp begins to flow. ! Based on the extended structure + dK, R using I”I,
In AM, the objective is to completely ensure that d-output malfunctions are prevented without slowing down the d-output speed.

In order to achieve the above object, what is inventively provided is an I that maintains two states: 1 "on" and "off".
2L to the bit line to withstand the memory cell and supply the commitment current or Fi continuous N current.

All the current switches for supplying the output current are connected, and this current switch is used to control the bit rate that changes from low to high during the transition of the memory cell address when the contents of the IL memory cell are continuously read out. In this semiconductor memory device, the read potential is not supplied to the bit acid 1 after M time has elapsed since the address switchback.

Hereinafter, embodiments of the present invention will be explained based on the accompanying drawing VC while being assimilated with the conventional example.

FIG. 1 is an equivalent circuit of a memory cell with 4!14Q5t IL. In FIG. 1, W+W- indicate word lines, and Bφ B indicates bit lines. Q, ~Q, indicates a valley transistor r, but it is like one cycle.

QI L=J2 is formed by a conventional PNP transistor.

By using Qs, Q4 VC reverse direction transistors, the bases of LD, QI, and Qt, the collectors of Q3 to Q6, and even W- are connected to the interconnected ridge conducting area (in this example, ri
It is possible to form 4 regions of the N type traditional head.

A memory cell with a non-'l@VciIij level is realized.

The basic operating characteristics of this cell are as follows9.

First of all, information retention is W+ or W-! The current flowing through the transistors Ql, Q! jL Q
It is done by Riko to create a state in which one of Q4 is turned on, and the curved blade is turned off. Holding current is the key to low power RAM.

It is desirable to set the current value to be as small as possible within the range of the current value that is necessary to maintain f'jf information. % large capacity le A114
This is important because the proportion of the total power generated by the holding lit flow becomes large. Next, in order to load desired information into this cell, a loading current Iw is supplied to the 7M bit lines and passed through the transistor QfiI or Q6.
The above-mentioned electric current is supplied to the wt-cell. At this time, the bit line transistor Qs that supplied the sinking current IW
, clause is -4 (for example.

If IW is supplied to bit #Bφ, 6Q, ) becomes 1
The state of the cell is inverted only when it is turned on. This is Qs,'! or (to keep J4t "on", the LAkt current supplied to the base of Q, or Q, is taken away by the base current of the transistor Qa+ or Q6 supplied with IW (Current Ha
Qs ＋
Ma7' (Q4 is no longer 1o/'' state can be maintained l〈na9
1 off" state, resulting in the state of the cell being reversed. By the way, it is necessary to set a current value of a certain threshold current 11yth or more for the embedding IT style (W) such as 0 round. Next, as an example of how to start a news report, use the following method. Namely.

The successive current IR=i is set to F below the threshold current IWtn, and is supplied to the two side pit sparse Bφ, B1, and the transistor Q
If it flows through the cell through s and Qa k, the cell's internal voltage IM
(= Qs, base potential of Q4) is +Qa, Qa
appears in bit S. In this case, the bit on the "on" side is antistatic α (high), and that on the "off" side is low IiL.
If this potential difference is detected by an appropriate circuit, one positive signal of the cell can be obtained.

Figure 2 shows the diagram for I''L type memory cell r.

This figure shows the main parts of a conventional circuit when realizing the system. The cells in FIG. 2 are designated using the same symbols as in FIG. Qa, Qb Id 7 h'
? The Ia driving transistors, Qg, and Qf are transistors that detect the bit line voltage difference. Qfi, Q
h, Q7 is written in the selection column, current work w, threading i flow IR.

and Q, QjK, which are transistors that apply a run-in current Is. Qj and Qk are input/repair transistors, which are taught by L)! Select the bit line to be supplied with Iwt. SA represents an amplification circuit that amplifies the detected pit potential difference. lH is the holding current mentioned above. Diode store, is D2 the current ID for discharging the word line when the word line passes? It is intended to supply

Several methods are known as means for supplying this word magnetic discharge tIIi waterfall.

RAiA VC'&T using IL type memory cells.

Since the ward boat W- is formed in bulk, its parasitic capacitance is large, and a sudden discharge + silence is essential. VBOL
ri? This is a bit line clamp potential that clamps the low level of bit- to a certain constant potential by transistor Qc Qct. Therefore, at the time of reading tC, the IR flowing through the bit line when the cell is in the "on" state flows through the cell, but the IR flowing through the bit line in the "off" state is Q. Also, the flow VB through FiQd
The level is p-clamped by OL, and becomes a low level state lower than the other bit potential.

The conventional circuit VC described above has the following drawbacks.

3a and 3b are diagrams illustrating the drawbacks of the conventional circuit shown in FIG. 2. In other words, Fig. 3a shows the switching of cells in a certain column 4)? r A circuit diagram for explanation, p, Figure 3 bLr
It is a waveform diagram showing the evolution of the voltage and current waveforms when cell CB or cell C8 in FIG.

As mentioned above, for the 1"L cell, the successive addition is based on the threshold current value i wta, and the successive addition aid
and the sink current IW; > Iwth ) IH
It is controlled by the current value set so that

However, if the margin of Iwth and IR is small, the cell will be reversed even when d is released (
IA keep doing this! I will call it a work by iIJ. ) creates a danger. The risk of this d output malfunction is greatest in the transient state in which the cell changes from the non-selected state to the selected state 1. This is because in the transient state, the cell changes from low current level operation (*1) to high current level operation (as shown in Figure 2). [The current IR etc. will be posted to IH. Puhe False 44
Yes.

As is well known, IWtn is directly proportional to the cell 11.

The margin of IR to Iwta becomes narrower at the beginning of this transient state. In addition, in the case of hypercough, when reading different cell 6 valleys, a change in the potential of the bit line occurs, so the capacitance of the pin point H (cB in Figure 3 aK>
The margin for burning I wth becomes narrow because the excessive g voltage VL that charges and discharges at t is absorbed by the d output current IR.

The above-mentioned matters will be explained in more detail using FIGS. 3a and 3b.

'dC3V a, b niorte, VX □,
VX2. VX3 u Valley Figure 3 a I/C
νKeru 9-do IVl! Drive transistors Qa, Qb
, Qc's base input Ilt waveform.

v, ,v, is the base potential of the "on" transistor of valley cell C,,C, (assuming that +Qs is in the "on" state in Figure 1, indicates the base potential of Qs).
4 waveforms, Vk3OL is bit clamp 1
It is ittc. IC1 indicates a current of 1 flowing through cell C1 which is in the selected state when 1 = 0, and as a matter of course, this continues when the steady state is reached and the current IHKJ4
L (Naru. In other words, vBφ is determined by the response waveform of the X response on the bit gland Bφ side. The part where the beveled edges of the valley cells C1°Ct & C8 are all applied is the off side, and the part that is not is the one on side. ” side.

In Fig. 3A, when the selection state moves from cell C6ρ to cell C1, that is, if the cells holding the same data continue to flow, the point at which the bit current starts to flow to cell C1 is cell C1. And C2's 1 [flow switch custom made from next army's 3rd]
As shown in the figure, VC and V. , i.e., t=
It starts near t, tlit.

Also, the potential V8φ of this bit line Bφ changes from a high state to a high state.
The company hardly ever changes.

However, on the other hand, in Figure 3 aKv, from cell C to cell C1
When the selection state changes to , that is, when a cell holding the opposite data is found, the point at which the bit line ``a'' flows to cell C3 is due to the custom-made current switch between cell C1 and the transistor Qd for bit switching level. Since it is determined, as shown in FIG. 3 bVc, VI? It begins at the intersection of l and vHOL, ie, t=td2. In this case, if the potential of @VBOL is set to the position IC as shown in Figure 3, r
In the relationship of Ldg〈1d□9. Moreover, since the potential of the bit drill Bφ also changes from a low state to a high state, it is shown by the dotted line (■) in the figure 3 (a) and the figure 3 (a). , the response cell CI
Even during the start-up process, inversion information is stored in the cell CI.

As can be seen from the above explanation, the one with the greatest risk of malfunction in the d-out state is the transient state that enters the t-layer selective state.
1tCw, the d output voltage υ1eIR is co-phased with the cell at a relatively early point in the transient state/method, and the pitch tsttw
This is a case where a state occurs in which the charging current of the raw capacitor CB flows in a different manner, that is, when a cell with peaks and valleys opposite to the previous cell contents is discharged. In order to avoid repeated ejecting malfunctions, the conventional method was to reduce the ejecting current, and the reduction in the ejecting current resulted in a loss in the number of ejecting sequences.

The present invention eliminates the disadvantages of conventional circuits and is essential for 9. When the readout current IR starts to flow from the cell you are trying to read (IC), by slowing down the flow, the & current and d output t current I□ This was done with the intention of preventing any malfunctions, such as px < d, by requiring a setting speed of di.

Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 4a is a main circuit diagram showing a first embodiment of the present invention. FIG. 4a The part surrounded by one dotted line in ItC is the circuit part according to the present invention. Here, a typical Kokum to which the circuit of the present invention is applied is shown.

In fact, it applies in the same way as the ri tani cocoram. Also, the peripheral circuit V
As for C, is it only the necessary parts to explain the present invention? il
- I will omit the word ``my friend''.

Configuration 1 of the part indicated by the dotted line according to this embodiment in FIG. 4a
It is as follows. The collectors of transistors Q7 and QA are connected to a load circuit consisting of a resistor g+ and a diode DI, and a resistor R2 and a diode D!, respectively. A load circuit consisting of a valve is connected to a reference power source vREFVc. A load circuit consisting of a resistor R3 and a diode D connects a resistor R3 and a diode D to the base of the transistor QA.
The load circuit consisting of transistor Q! They are also connected to the bases of l. A diode D is connected between the bit line Bφ and the emitter of the transistor Q with its anode facing the bit line. A diode D4 is similarly connected between the bit line B and the emitter of the transistor Q. Transistor Q! i and Q
The emitters of h are connected to the serial * current source through the seven transistors Q, s and QL (11-), respectively. This configuration allows the transistor Qy (!: QA
constitutes a flip-flop, and transistor Q,
, diode D3, transistor Qh, and diode D4 each constitute a current switch.

FIG. 4 is a schematic waveform diagram of the voltage type 1jIt response when the selection state changes from cell C6 to cell C1 when 1=0 in FIG. 4a and C. In Figure 4, "REF" is the reference potential supplied to the circuit part of the main circuit, and ΔV indicates the apparent direction from the same direction to the opposite direction when current flows through the diode l) I or D2 in the g4 diagram. It shows a value of 0.7 to 0.8v.The symbols for the ponds are the same as those used in FIG.

When 1=0, the data of the reverse same valley is held, and from cell C7 to cell C
The operation when the selection state is set to 1 is as follows. VR
As shown in FIG. 4, the value of EF is one point higher than the high level of the bit line.

Voltage drop Δ from VREF to diode D1 or
It is set to 1st shift (VR14F-ΔV) minus V (VR14F-ΔV) or the low level of the bit line to 1st shift.

1) 1<0, cell C2 is in the selected state, and the potential of the bit @iB is vB1 or H, and the level of the focus line Bφ is increased v.
Bφ becomes L. Therefore, in the circuit section of the present invention, since the transistor Q, and the diode 1)3 and the transistor QA and the diode D4 constitute a current switch, respectively, Q is "on" and D is "off".
Furthermore, QA is] off.”

D4 becomes "on". In other words, in a flip-flop consisting of Q,, QA, since Q is in the on state,
Q! 10 base iIl crying VB! Iu hoho V REF
To Luher, also QA's base il I rank VBA (Q,
Since the diode D is turned on, the collector potential (collector potential of ) is at the level of VREF - ΔV. Then, the read current R on the bit side B and side flows through diode D4 + bit line B, but the read current R on the bit @Bφ side is Qy
, D+ flows to pit t1111Bφ. That is, in a steady state, ■□ is supplied only to the on-side bit line.

Therefore, when 1=0 and the selection state moves from cell C2 to C1, it becomes like an arrow.

First, the bit line Bφ is not supplied with the starting current IR, and the voltage V3φ at 'lit' rises. Even if VBφ becomes sufficiently high, Q's pace potential VB! Since VaF, which is I, is set to a higher potential value than H of the bit line, diode D is turned off and Q! 1 remains on, beep)? 1
Current ■R still does not flow through M8φ.

On the other hand, bit) MB is bit line B due to continuous current ■4.
, falling while the gestational capacity is fully discharged.

When the potential vB increases to the base potential of QA (vB), inゎchi vREF・-ΔV, Qh is turned on.

D is turned off, and the pace potential VB of the other transistor of the flip 70 tube is turned off. 1t-Togeru. As a result of step 7, Q is turned off and D is turned on, and the warm current ■□ continues to be supplied to the bit line Bφ for the first time.

As described above, in this embodiment, when the cell C2 having 1 inversion information tl- is in an overstretch state, the bit line Bφ that is photo-oxidized from L to H is not connected to the bit line R. Because of the VC, as mentioned above, 10〈, charging current and
It is possible to prevent erroneous writing to the edge of C3.

In addition, current switches Ds, Qy and 04°QA t using the level of the bit line BφB are used as means for this purpose.
- Furthermore, a flip-flop is configured with Q, , QA. Then, in a normal state, the lead-out current R is supplied only to the on-side bit line (H level), and in a transient state, the on-side pit llll1i
I is discharged by IR to L level, and the level νC
Then, invert the flip-flop and apply VC to supply IRk to the other pin.

Originally, the series 1 [Ryuko □ is used for discharging to 1 (→L) of 1 (Pick due to information reversal at the time of d output) &l.Therefore, as in this embodiment, in a transient state L-H
There is no problem even if the read current IR is not supplied to the bit line that is photoelectrically activated and the bit line that is off in the steady state.

5 and 6 are circuit diagrams showing other embodiments according to the invention. Here, only the two essential parts corresponding to the parts indicated by dots in FIG. 4a are shown.

FIG. 5 shows that the response speed of the circuit section of the present invention can be further improved by using Sotky diodes in place of the diodes of the loads Q, QA shown in FIG. 4a.

In FIG. 6, Pf'JP transistors are used as loads for Q, QA. IL-cell also has P as a load.
N)' The circuit of the present invention in which the VC is attached on the same column as the cell has advantages in terms of separation ZN and pattern layout.

As is clear from the above description, according to the invention, read malfunctions can be completely prevented in a RAMK using IL without impairing read speed.

Note that the present invention is not limited to the above-described embodiments, and various modifications can be made.

[Brief explanation of the drawing]

FIG. 1 shows a well-known memory cell configured as 111.
A curved circuit diagram, Figure 2 shows RAMk using fL type memory cells.
Main part circuit diagram of the conventional circuit when realized, Figure 3 aU No. 2
FIG. 3 is a voltage/current diagram of the main part of the circuit in FIG. 3a, and FIG. Fig. 4 is a voltage/current waveform diagram of the main part of the circuit in Fig. 4a, and Fig. 5 is a circuit diagram of part IIi showing the second embodiment of the present invention. , and FIG. 6 is a circuit diagram of the main part showing the third embodiment by Uninvented VC. Patent applicant Fujitsu Co., Ltd. Patent agent Akira Yoki Patent attorney Kazuyuki Nishi Patent attorney 1) Patent attorney Shino Yamaguchi's special patent application 1984-3184 (Riki)

Claims (1)

[Claims] 1. I”L that maintains two states: “on” and “off”
A current switch for supplying a write current or a continuous current is connected to a bit line for supplying a write current or a continuous current to the memory cell. The bit line rC, which changes from a low potential to a high potential during the transition of cell address switching, is set to V so that the continuous current is not supplied to the pin if until a predetermined time has elapsed after the address switching. A semiconductor memory device whose physical image is