JPS5832430A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of a hollow in the groove part of a semiconductor layer which acts as a semiconductor element separator even if an insulating material is deposited at an angle by providing the groove with steps made by selectively forming the first groove then forming the second groove at the first groove bottom part with its inner walls covered with a mask material. CONSTITUTION:A mask film 12 of Si3N4, etc. is applied on a semiconductor layer 11. Other than the part at which a groove is to be formed resist patterns 13a, 13b are applied. Using these patterns as masks the exposed part of the film 12 is removed by etching, and the first groove 14 is formed by etching the layer 11. A thin film 15 for mask formation is deposited to cover not only the surface but also the groove inner walls and bottom part. Then, only the film on the bottom part is removed. Using films 16a, 16b on the inner walls of the groove 14 as masks a deep groove 17 is vertically formed to the bottom part of the groove 14 by applying the anisotropy etching.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device.
(:, It is related to a manufacturing method number that is an improved version of inter-element isolation technology such as LtlC.

Conventionally, semiconductor devices, I! #, bipolar IC.

)'108Ic, a PNN junction isolation single selective oxidation method is generally used as a method for separating elements.

However, such methods have various drawbacks. For example, in the pn junction isolation method, the degree of integration decreases because the lateral diffusion of one isolation diffusion part is large. Furthermore, in the selective oxidation method, stress increases due to penetration of the oxide film at the edge of the field.

This causes crystal defects, and furthermore, this penetration increases the difference in pattern conversion. For this reason.

With this method, there is a limit to how high the degree of integration can be achieved.

For this reason, the applicant has already proposed the following new element isolation method. For example, as shown in FIG. 1, a recessed groove 2 having a width W and a depth DI and having vertical or nearly vertical side surfaces is formed in the semiconductor layer 1. In this case, groove s1
If the ratio of depth (CDI) to width (W, ) is relatively small, then As shown in the figure, when the insulating film 1 is deposited which is sufficiently thicker than half the width W of the trench IB2, the trench s1 is gradually filled in, and the surface of the insulating film 1 becomes flat. Subsequently, the insulating film 1 is etched to expose the main plane of the semiconductor layer l, and an insulating isolation region can be formed in the trench sz.
(not shown). However, in this method, if the groove depth (DI) is made larger than the width (wt) Jζ (D2 > DI), as shown in FIG.

A cavity 4 is created within the insulating film 3 in the groove portion 2'. this is.

The deposited component of the insulator is not necessarily deposited in a direction perpendicular to the principal plane of the semiconductor layer.

There is a component oblique to the main plane of the semiconductor layer.

This is because this diagonal component cannot penetrate deep into the groove 2' and is deposited at the entrance of the groove 2'.

The present invention has been made in view of the above circumstances, and by forming a step-shaped groove portion with a wide opening side in a semiconductor layer, when an isolation material such as an insulator is left in the groove portion, it is deposited from an oblique direction. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a highly reliable element isolation region, which can prevent cavities from forming within the tile portion even when the semiconductor device is used.

Hereinafter, the present invention will be explained in detail with reference to Figures J13 (a) to (h).

First, a mask film 12 is deposited on the semiconductor layer 11 . This mask coating has a thickness of 300G-5.
oooi silicon nitride film, etc., and in some cases, a low-melting insulating film such as a phosphorus silicide glass film or a boron silicide glass film.

Furthermore, a metal film or the like may be used. Also, wear a mask! ll
A film (not shown) thinner than the mask film may be interposed between 15M and the semiconductor layer 11. In this case, the intervening thin film is, for example, a silicon oxide film with a thickness of about 500 mm, and the mask film is a polycrystalline silicon film with a thickness of about 3000 to 500 mm. Subsequently, resist patterns 13m, 1jb, etc. are formed on the mask film 12 other than the areas where the grooves are to be formed by photolithography (as shown in FIG. 3(1)).

Next, the mask film 12 is etched away using the resist pattern 13m and 'IMbf mask, and the semiconductor layer 11 under the resist pattern 13m is etched away to form the first groove 14 (as shown in FIG. 3(b)). In this case, if anisotropic etching such as active ion etching is employed as the etching means, the etched portion of the mask film 12 will have side surfaces that are perpendicular to the image or nearly vertical, and the first groove portion 14 will also have similar vertical sides. Or it will have nearly vertical sides. However, it may be etched to have a reversely tapered side surface using other etching means.

Next, after removing the resist patterns l1m and 13bli, the mask film Xaa including the groove WAxa is formed.

A thin film 15 for forming a mask material having a thickness less than half the width of the groove 14 is deposited on the groove 12b (as shown in FIG. 3(C)).

The thin film 15 used here is a material that has selective etching properties with respect to the semiconductor layer 11.

For example, CVD-8i0t, polycrystalline silicon, metal, etc. may be selected. Next, by anisotropic etching in which etching progresses perpendicularly to the main surface of the semiconductor layer 11, the thickness of the thin film 15 is removed, leaving the thin film on the inner surface of the first groove 14, and the mask material 16a is removed. 1 gb (as shown in FIG. 3(d)).

At this time, the semiconductor layer 11 is exposed at the bottom of the first groove 8t114.

Next, the semiconductor layer 11 on the bottom surface of the first groove part 14 is etched using the mask film z2 and the mask material 168°16b to form a second groove @1'F (see FIG. 3 (61)).
. In this case, if anisotropic etching is used as the etching means, the second
A groove portion 17 can be formed.

Next, the first groove @ 14100 mask material 16 m.

11ib by isotropic etching (as shown in FIG. 3(f)). The masked g
(Fig. 3 (g)).
) Figure 7? ). in this case.

The separation material forming material first buries the second groove WAxr, and then completely buries the first groove portion 14 without creating a cavity. Methods for forming the isolation material forming film 18 include 1, for example, a method of depositing an insulating material by a CVD method, a PVD method, etc., a method of directly oxidizing the semiconductor layer 11 and burying it with an oxide, or a method of 1. Method 1 or the like may be employed in which a film of an oxidizable material such as polycrystalline silicon is formed on the side or bottom surface of the second trench and the film is oxidized to bury the trench. For example, the insulating material may be one.

810, ,8t,N,. Alternatively, 5l*O3 may be used, and in some cases, a low-melting insulating material such as phosphorus silicide glass or boron silicide glass may be used. Note that prior to depositing the insulating material or the conductive material, the entire semiconductor layer or at least a part of the groove is oxidized or nitrided to form a 1r degree oxide film that does not cause the groove to collapse, or
A nitride film may also be formed. The element isolation region obtained by using these methods together was in contact with the semiconductor layer in the trench. 1. It is composed of an oxide film or a nitride film with excellent density, and a conductive material, and can significantly improve the element isolation region compared to a structure made only of an insulating material. Furthermore, after depositing the separation material forming material, the entire or part of the surface layer of the formed film is doped with a low melting substance 1, such as boron, phosphorus, silicon, etc., and the doped layer of the formed film is melted by heat treatment, or Alternatively, a low melting insulating material 1 such as boron silicide glass (88G
), phosphorus silicide glass (P2O), or arsenic silicide glass (A 8G) may be deposited, and this low-melting insulating film may be melted, or any one of the following treatments may be performed. By employing such means, 1. If the part corresponding to the groove part becomes concave depending on the deposition conditions of the separating material forming material.

The concave portion can be filled and flattened.

Then = Suffum coating 1 za,! The separation material forming film 8 is etched and removed from the entire surface until the tza'M'@ is exposed. The isolation material 1fi is left in the second trench 14 and IF to form the element isolation region 10 (third
Figure (h) shown). As the etching means used here, for example, a full surface etching method using a wet etchant or a plasma etchant, a reactive ion etching method, etc. can be adopted. However, these etchants either do not have etching properties on the mask film IJt, or have grooves with little etching property. BI4. 1 g of separation material buried in the IF is removed by etching with an etchant that is difficult to etch. At this time, if there is a thin film under the mask film, this is also removed by etching to expose the surface of the semiconductor layer. At this time, as shown in FIG.

It protrudes from the surface of the semiconductor layer 11, and the side surface of the protrusion has a straight or almost vertical shape. Therefore, since the element isolation region 20 has a shape that protrudes from the surface of the semiconductor layer 11, even if a junction is formed in this part in contact with the element isolation region, the almost perpendicular part of the semiconductor layer
Since lIII is not exposed, deterioration of bonding characteristics can be prevented.

Furthermore, a thin insulating film with a thickness of 2000~5i is deposited on the entire surface of the semiconductor layer having such a protruding element isolation region, and then the thin insulating film is removed by anisotropic adhesive active ion etching. By using the manufacturing method according to the present invention, it is possible to leave only the nearly vertical side surfaces of the semiconductor layer and further prevent the side surfaces of the groove portion of the semiconductor layer from being exposed. It is possible to form a device with good characteristics. Also, by repeating this method, it is easy to form multi-stage grooves.

Next, one aspect of the present invention will be explained in detail.

Example 15 [1] First, an n+ buried layer 10M was selectively formed on a p-type semiconductor substrate Eel, and an evidaxial semiconductor layer 10M of ζnlI was further grown. Continuing.

Silicon nitride film 10 is formed on semiconductor layer 163 by CVD method.
After depositing resist pattern 4, a resist pattern 10 is formed on the silicon nitride film 104 in areas other than the planned device isolation regions by photolithography.
A 1 m-18 IC was formed (as shown in FIG. 4(a)).

[11] Next, resist pattern 7
-rasc as a mask to form a silicon nitride film 104. The semiconductor jfl Z Ox is sequentially etched to form a semiconductor 41o.
1, a first groove portion 106 m, 10 having a width of approximately 277 m;
6b was formed. Next, a thin film for forming a mask material (
! : L/TE') Thickness approx. 5 Q OOX') C
V D-8'Ot 1ili76F was deposited on the entire surface (M4 figure (b) [shown)]. Continuing, the semiconductor layer 101
CVD-5t with six RIli orientations perpendicular to the main surface of.

@101 is etched to form the first groove portion 11) ga.

lot;brD'fNR side CVD-8i0. (? Soft material) fc) Pa-107d remained (Fig. 4 (C)
)@show). At this time, the first groove fil, xott; a, x
The semiconductor layer 101 was exposed on the bottom surface of Ottb.

(iil1 then silicon nitride film 104yr-104
c and remaining CVD-8i"0.10'1a-107rd
Using as a mask, the semiconductor layer 10M at the bottom of the first groove @10'i and 101ib is etched to form the second groove slot.

A second groove portion 108a is formed by forming a second trench portion 108a and then implanting poron ions using a similar mask.

A p-type region XO 109b for channel cutting reaching the p-type substrate 101 was formed on the bottom surface of l6lb (
(Illustrated in FIG. 4(d)). Continuing, as shown in Figure 4 (el), residual CVD-810, r #
Fa-Z6rd was removed.

[1v] Next item, 1st. Second groove @1068, 106b
.

Silicon oxide film 104a-1 containing JO8a and l6lb
CVD-5tO as a separation material forming film with a film thickness sufficiently thicker than the width of the first groove @ 106m, 106bO) on 04C,
A film is deposited, and this StO film is replaced with a silicon nitride film 164.
Etch the entire surface until 1-1fj4G is exposed.
．． Second groove tags.

C as a separation material in IC#b, lama, 1tzlb
VD-810, 1161, I 10b@ remained to form an element isolation region f 11 a e 111 lrk.

Continuing, the exposed silicon nitride f14toa-1
04f was removed by plasma etching or the like (as shown in FIG. 4(f)). After that, although not shown, a layered n-type medium conductor layer
A pm base region is formed in ozb, an n0 type emitter region is formed in the same base region, and a semiconductor layer 1 is formed (an n0 type collector extraction hole is formed in lJb, and further he@17. of the base, emitter, and collector are formed to form a vertical opening. A pn bipolar transistor was used.

Accordingly, the method of the present invention has various effects as listed below.

(1) The grooves that become the element isolation regions 111s and 1llb are the first grooves xo6a, t6gb, CI)
CVD-8 remaining on the side of 11th section 106m, l06b
+0. 107 a Second groove 1fjlla, ■) Jl formed by etching using #I OF d as a mask
It consists of b. In other words, since it is possible to form a groove with a large area on the opening side and a narrow internal area, it is possible to prevent cavities from forming within the groove when forming a separation material forming film in this groove.
Furthermore, by leaving the isolation material in the groove, the device isolation region 111m, Zllb, which has excellent reliability and junction breakdown voltage, can be created.
can be formed.

(2) Element isolation region 1118. The area of l1lb is the area of the first. second groove part J6ga,
f##b, 1088. Since it is determined by the area of the lamb (particularly the first trench WA), by reducing the area of the trench, it is possible to easily form the desired fine element isolation region 1111.1.
11b can be formed.

A highly integrated bipolar transistor can be obtained.

(The depth of the 31st element isolation region Ith N, 1llb is independent of the area of the first trench 106a provided in the semiconductor layer ton,
101b and the second groove type 10!1m, which is determined by the depth of l011b, the depth can be arbitrarily selected, and the current IJ between the elements can be controlled by the element isolation region 11.
1 m, l l lb can be reliably blocked, and a high-performance bipolar transistor can be obtained.

(4) Reinforce the second grooves @1011a and 1011b with the first grooves rein, rotzb@@(D remaining CVD-840, 1
01a to tovd, so that the nil at the bottom of the second grooves 1011a and 1011b
A p+ type region 109a109b for channel cut is formed in the semiconductor layer 102 of the first groove @J, rtJ6s.

Residual CVD-5to against xaib4c, 101a
It is possible to form a self-aligned sieve by the thickness of -rod, and as a result, the n0 buried layer 1-02 and the p0 type region r09
m, 10 mb can be extended by a predetermined distance, and a decrease in junction breakdown voltage can be prevented.

(5) P-type region 1o for channel cutting
After forming ya, 1o9b, a high temperature and long time thermal oxidation process like the conventional selective oxidation method is not required.
Since the p-type regions 1011m and l0lb are re-diffused in the same horizontal direction and do not reach the n-type buried region 110M in the element formation region or the active region of the transistor, it is possible to prevent the effective reduction of the element formation region. In this case, if the impurity is doped by ion implantation, the impurity ion implantation layer can be formed at the bottom of the second grooves x011a and xDMb, and even if the ion implantation layer is re-diffused, the surface layer of the element formation region ( Since it does not extend to the active area of the transistor, it is possible to prevent the effective element formation area from being reduced.

Blockage to the impurity region of the transistor active region can also be prevented.

(6) 1st. Second groove xoea, togy 1m
m.

The isolation material is left in all of 1011b to form the element isolation region 1.
When 11a and 1llb are formed, the semiconductor substrate is flattened, so that it is possible to prevent breakage from occurring during subsequent formation of electrode wires.

Example 2 [1] First, an n-type epitaxial semiconductor layer 2ejM is grown on a conductive substrate taX, and then boron is selectively ion-implanted into the semiconductor layer gos, and then heat-treated and diffused. In this way, a PAL semiconductor region sex was formed. Subsequently, after depositing a silicon nitride film 204 on the entire surface by CVD, a resist pattern: tosa
205d was formed (as shown in FIG. 5(a)).

[Opening 1] Next, using the resist pattern 2m9-2old as a mask, the silicon nitride 1% zoa and the semiconductor layer 202 were sequentially removed by a reactive ion etching method to form first grooves II 206a to 201c. Next, CVD-8 was applied as a thin film for forming a mask material on the entire surface.
The O1 film 206 was deposited to such an extent that the first grooves 205a to 205 were not blocked (FIG. 5 (b1)).

(ili1 then CVD-5lo by RIB,
Etch 1llzoy and 1st groove @20gm #
CVD-5to (not shown) was left on the inner surface of 206d.

Next, using silicon nitride [%204a~20dd and residual CVD-810 as a mask, the first (7)
The semiconductor layer gos on the bottom surface of 1s2osa to 206G is etched to form a second groove portion 268a-2011C.

Further, using a similar mask, arsenic is ion-implanted to form an n-type semiconductor substrate 10 at the bottom of the second groove g41oHa-zoac.
n+ type region 30#a for channel cutting reaching 1
~209c was formed. Continuing.

Residual CVD-810 (not shown) due to ammonium fluoride, etc.
, and further grooves 205a to zos of #gl are removed on the entire surface.
As a separation material forming film with a thickness sufficiently thicker than the width of c (7)
After depositing a CVD-8tO film (not shown), this 8tO
10. The entire surface of the film is etched until the silicon nitride films 204a to 204a to 204a are exposed to form the first and second trenches 1#im,
C as a separating material in 106C, 1611m-26&c
VD-5to, 210a to 210G were left to form element isolation regions 111a to 211C. Thereafter, the exposed silicon nitride films 2048 to 2tj4c were removed by plasma etching (as shown in FIG. 5C).

OV) Next, a thermal oxide film 111 is grown on the exposed semiconductor layer by thermal oxidation treatment, and a polycrystalline silicon film is further deposited on the entire surface, and then patterned using photoetching technology to form a second element isolation region. 211b and the element isolation region z
xtb.

Gate electrodes ffZj, 2, 1. was formed.

Subsequently, after covering the semiconductor regions other than tozb and goz with a resist pattern (not shown), the thermal oxide film MIX is etched using the resist pattern and the gate electrodes ffZj, 2111 as a mask to form the gate oxide film 214.
．． ．． 11-3 was formed. Subsequently, a gate electrode 11s made of polycrystalline silicon is formed by thermal oxidation treatment at a low temperature.
, 111g thick silicon oxide around! I! 21g,,1
16. After growing a thin silicon oxide film (not shown) on the exposed semiconductor layer, the thin silicon oxide film was removed to form openings 5162168-216d. Furthermore, the gate electrode 213. Using a resist film (not shown) as a mask, 10 g of n-type boron is ion-implanted into the n-type semiconductor region, and activated to form p-type source and drain regions 2.
1F,,jJ#, were formed.

Furthermore, the gate electrode 213. and a resist film (not shown) as a mask, arsenic ions are implanted into the p-type semiconductor region 7103, and activated to form n+ type source and drain regions 2J7. ．． 2ZJI was formed (Fig. 5(d)
(Illustrated). After that, one figure is not shown.

A complementary MO8 transistor (CVD8) was manufactured by forming interconnections that contacted each source and drain region through the openings 2t1 to zx4d in accordance with a conventional method.

According to the above method, the element isolation region 111t*
~CVD 8j0.110a- that constitutes l1lc
Since the p-channel MO8FgT and the n-channel h108Fl'r can be separated by 1C, the sp" type source region try, (or drain region z1g1) and the n0 type source region zlF, (or drain region zrg,) It is possible to sufficiently increase the junction breakdown voltage between and obtain a fine CMOli.
pnp transistor, i.e. p+ type source region tr
y (or the drain region 2ig) as the main transmitter, the n-type semiconductor region tomb in contact with the substrate j171 as the base, and the pm semiconductor region 201 as the collector, the element isolation region ztxb and the n-type region 2011.
b to suppress the injection of minority carriers into the emitter.

The current amplification factor of the pnp) transistor can be suppressed.

Furthermore, the latch-up phenomenon caused by Cu2S4I can be prevented.

Note that the method for manufacturing a semiconductor device according to the present invention is as follows.

As in the above embodiment (npn bipolar transistor or CV
The present invention can be applied not only to the production of D8, but also to other bipolar semiconductor devices such as I"L, n-channel and p-channel MO8) transistors, and the like.

As described in detail above, according to one aspect of the present invention, the semiconductor layer has a step-shaped first layer having a wide opening side. By forming a groove consisting of the second groove and leaving the isolation material there, it is possible to form an arbitrary and fine element isolation region without a cavity within the groove, resulting in high integration, high reliability, and high performance. , it has a remarkable effect on the ability to manufacture semiconductor devices.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a sectional view showing a shallow isolation region formed by the method already proposed by the applicant, and FIG. 2 is a sectional view showing a deep isolation region formed by the same method. , Figure 3 (a
) to (i) are steps showing the formation of the element isolation region of the present invention@f
r side view, Figure 4 (at~ffl is a process sectional view showing the manufacturing of the vertical npn bipolar in Example 1 of the present invention, Figure 5 fat ~ (di is Cvo in Example 2 of the present invention)
FIG. 3 is a process cross-sectional view showing the manufacturing of 11...Semiconductor @, 22.104.104JI#10
4c. ! 174.21') 41~yio4d...Silicon nitride film, 14° 106m, 106b, 206m #201
iC--first groove S. r6a, 16h, lo'la, 10rb-residual CVD-
810° (mask material), I'1.1118m, la
mb, 11111 Otori ~ 20 #b...Second groove portion 19, 110a, 110b, 1lla~211G-...
Separation material, Flo, 111a, 1llb, l1ls~21
1G: element isolation region, 101: p-type semiconductor substrate, 102: n-buried layer, was, xosa-'
101c... n-type semiconductor layer, 109 layers, 109b.
...CH = p-type region for yellow nail cutting, 201
...Hall semiconductor substrate, toss~202C...
nfll semiconductor area. 20 j ・P-type semiconductor region, 209m, 20ri1)
,,, fi+ type region, ! 21. ．． ! 13. ...
Gate electrode! IF,. 211, . . . source area, 21g, , 21g, . .
drain area. lli 5 (e) (d) 1/+ Figure 3 (a) (C) ]Ul (b)

Claims (1)

[Claims] (11) a step of selectively forming a first groove in the semiconductor layer; a step of selectively leaving a mask material on the inner surface of the first groove; A method for manufacturing a semiconductor device, comprising the step of etching the bottom surface of the first trench l11 to form a second trench. (2) Forming a mask material on the inner surface of the first trench. The method is characterized in that the knee is etched by depositing a thin film for forming a mask material on the semiconductor layer including the first groove, and anisotropically etching this film in a direction perpendicular to the main surface of the semiconductor layer. A method for manufacturing a semiconductor device according to claim 1. ■ The method according to claim 1, wherein the separation material is left in the first and second grooves after the mask material is removed. A method for manufacturing a semiconductor device. (4) In the previous step of leaving the separation material in the first and second grooves, at least a part of the grooves is oxidized or nitrided to form an oxide film or a nitride film. A method for manufacturing a semiconductor device according to claim 1 or 3. (5) After forming the second groove, doping the groove with an impurity to form a bottom surface while leaving the mask material. A method for manufacturing a semiconductor device according to claim 1, characterized in that: (6) After forming a first groove and forming a mask material on the inner surface of the groove, using the mask material, Manufacture of a semiconductor device according to claim 1, characterized in that when the step of etching the bottom surface of the first groove part to form a first groove part is repeated, a multi-stage groove part is formed. Method.