JPS583254A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS583254A JPS583254A JP56101785A JP10178581A JPS583254A JP S583254 A JPS583254 A JP S583254A JP 56101785 A JP56101785 A JP 56101785A JP 10178581 A JP10178581 A JP 10178581A JP S583254 A JPS583254 A JP S583254A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- semiconductor substrate
- metallic wire
- pattern
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は微細な金属配線パターンを形成するのに好適な
半導体装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor device suitable for forming fine metal wiring patterns.
従来の半導体装置における微細な金属配線パターンの形
成される下地の断面はフラットであった。In conventional semiconductor devices, the cross section of the base on which fine metal wiring patterns are formed is flat.
このため、金属配線パターンの線巾が微細になるにつれ
て、特にフォトエツチング工程においてフォトレジスト
が十分に解像できなくなり、隣接するパターンのフォト
レジスト間に７オトレジストのつながりが生じ、エツチ
ング後には金属配線パターンのシ肩−トという問題が生
じていた。また、上記を防止するために従来はパターン
間寸法を大きくしていた。For this reason, as the line width of the metal wiring pattern becomes finer, the photoresist cannot be sufficiently resolved, especially in the photoetching process, and a 7-photoresist connection occurs between the photoresists of adjacent patterns, and after etching, the metal wiring becomes A problem has arisen with pattern shoulders. Furthermore, in order to prevent the above problem, the distance between patterns has conventionally been increased.
本発明はかかる欠点を除去したもので、その目的は微細
な金属配線パターンを精度よく、さらに品質よく形成す
ることに好適な半導体装置の構造を提供することである
。The present invention eliminates such drawbacks, and its purpose is to provide a structure of a semiconductor device suitable for forming fine metal wiring patterns with high precision and high quality.
・・′１゜ 以下実施例に基づいて本発明の詳細な説明する。・・'1゜ The present invention will be described in detail below based on examples.
第１図は本発明の実施例Ｉである。１は本発明による所
の凹凸状の断面を有す半導体基板下地。FIG. 1 is Embodiment I of the present invention. 1 is a semiconductor substrate base having an uneven cross section according to the present invention.
２は金属配線パターンである。2 is a metal wiring pattern.
このような構造をとれば、隣接する金属配線パターン間
において、特にフォトレジストパターン形成を行なう工
程においてフォトレジストのつながりが生じない。これ
は、半導体基板下地断面がフラットな時と比べ露光光線
が金属配線パターン側に反射してフォトレジストパター
ンが太ることを防止するためであり、現像時においては
現像液によるフォトレジストのｌｌｌｌ１１による隣接
する金属配線パターン間の７オトレジストのつながりを
防止する。また、エツチング工程における金属配線膜の
サイドエツチング量は凹状溝部の方が凸状鞍部に比べ小
さいためにエツチング精度は正確に制御できるためであ
る。With such a structure, no connection occurs in the photoresist between adjacent metal wiring patterns, especially in the step of forming a photoresist pattern. This is to prevent the photoresist pattern from becoming thicker due to the exposure light reflecting toward the metal wiring pattern side compared to when the cross section of the underlying semiconductor substrate is flat. This prevents the connection of the 7-photoresist between the metal wiring patterns. Further, since the amount of side etching of the metal wiring film in the etching process is smaller in the concave groove than in the convex saddle, the etching accuracy can be controlled accurately.
このように本発明は、微細な金属配線パターンを隣接す
る金属配線パターンとシ曹−卜することなく精度よく形
成することができる等のすぐれた効果を有するものであ
る。また、本発明は実施例Ｉのみならず実施例■および
璽においても同様の効果を有するものである。さらに本
発明の効果は金属配線パターンの線巾が金属配線パター
ン間のすき間の寸法に比べ大なる程効果を生ずるもので
ある０以上のように本発明は半導体基板上に微細な金属
配線パターンを形成するときに適用できる。As described above, the present invention has excellent effects such as being able to form fine metal wiring patterns with high precision without interfering with adjacent metal wiring patterns. Further, the present invention has similar effects not only in Example I but also in Example 2 and the seal. Furthermore, the effect of the present invention is such that the larger the line width of the metal wiring pattern is compared to the dimension of the gap between the metal wiring patterns, the more the effect is produced. Can be applied when forming.
特に隣接する金属配線パターン間寸法が微細で金属配線
パターン線巾が大なる時により有効に適用できるもので
ある。In particular, this method can be more effectively applied when the distance between adjacent metal wiring patterns is small and the metal wiring pattern line width is large.
また、この方法によれば、半導体基板上の断面形状をわ
ずかに変えるだけで金属配線を精度よく形成できるので
、隣接する金属配線パターン間寸法を小さくすることが
できるものである。Furthermore, according to this method, metal wiring can be formed with high precision by only slightly changing the cross-sectional shape of the semiconductor substrate, so that the dimension between adjacent metal wiring patterns can be reduced.
図面はいずれも本発明の実施例である。
第１図は実施例■の断面図、第２図は実施例Ｉの断面図
、第３図は実施例■の断面図である。
１・・・・・・酸化物膜
２・・・・・・金属配線膜（パターン）３・・・・・・
酸化物膜 ４・・・・・・半導体基板５・・・・・
・金属配線ＷＩ（パターン）６・・・・・・第２層酸化
物膜
７・・・・・・第１層酸化物膜
８・・・・・・金属配線膜（パターン）以上
出願人 株式金社諏訪精工舎
代理人 弁理士 最上 務The drawings are examples of the present invention. FIG. 1 is a sectional view of Example 2, FIG. 2 is a sectional view of Embodiment I, and FIG. 3 is a sectional view of Example 2. 1... Oxide film 2... Metal wiring film (pattern) 3...
Oxide film 4...Semiconductor substrate 5...
・Metal wiring WI (pattern) 6... Second layer oxide film 7... First layer oxide film 8... Metal wiring film (pattern) and above Applicant Stock Kinsha Suwa Seikosha Agent Patent Attorney Tsutomu Mogami
Claims (1)
の下地の断面が凹凸形状を有し、特に凹状溝部に金属配
線パターンを形成することを特徴とする半導体装置。1. A semiconductor device characterized in that a cross section of a base of a semiconductor substrate in which a fine metal wiring pattern is to be formed has an uneven shape, and in particular, the metal wiring pattern is formed in a concave groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101785A JPS583254A (en) | 1981-06-29 | 1981-06-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101785A JPS583254A (en) | 1981-06-29 | 1981-06-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS583254A true JPS583254A (en) | 1983-01-10 |
Family
ID=14309830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56101785A Pending JPS583254A (en) | 1981-06-29 | 1981-06-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583254A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6269533A (en) * | 1985-09-20 | 1987-03-30 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS495283A (en) * | 1972-04-28 | 1974-01-17 |
-
1981
- 1981-06-29 JP JP56101785A patent/JPS583254A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS495283A (en) * | 1972-04-28 | 1974-01-17 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6269533A (en) * | 1985-09-20 | 1987-03-30 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3454970B2 (en) | Mask pattern correction method, pattern formation method, and photomask | |
| US4690880A (en) | Pattern forming method | |
| JPS583254A (en) | Semiconductor device | |
| JPS6211068B2 (en) | ||
| JPH0795543B2 (en) | Etching method | |
| JPH03203390A (en) | Manufacture of printed board | |
| JPH0548928B2 (en) | ||
| JPS60101931A (en) | Formation of fine pattern | |
| JPS62194628A (en) | Manufacturing method of semiconductor device | |
| KR100265989B1 (en) | Polysilicon Pattern Formation Method of Semiconductor Device | |
| JPH08248618A (en) | Reticle | |
| JPS6240862B2 (en) | ||
| JPS5824020B2 (en) | semiconductor equipment | |
| KR20020046489A (en) | Method for fabricating fine pattern using double exposure | |
| KR100329605B1 (en) | Method for manufacturing metal wiring in semiconductor device | |
| KR0174992B1 (en) | Manufacturing method of semiconductor reticle and manufacturing method of vernier-key | |
| JPS58197849A (en) | Formation of electrode wiring | |
| JPS58166347A (en) | Photomask | |
| JP2737256B2 (en) | Method for manufacturing semiconductor device | |
| JPH07211849A (en) | Lead frame | |
| JPH0258212A (en) | Manufacture of semiconductor device | |
| JPH01126651A (en) | photo mask | |
| JPS60231331A (en) | Formation of lift-off pattern | |
| JPH01256128A (en) | Dry etching method | |
| JPH02148721A (en) | Method of forming resist pattern |