JPS583308A - Offset erasing circuit - Google Patents

Abstract

PURPOSE:To form an offset erasing circuit advantageous for circuit integration, by using an integral network and a subtraction circuit not including a resistor. CONSTITUTION:An integral network 15 and a subtraction circuit 11 are formed respectively without using a resistor. An output of and an input to a deciding device are inputted to a subtraction circuit 13 to pick up an error signal and it is integrated at an integral network 15 to estimate the offset. An estimate value of the offset is subtracted from an input signal having the offset at the subtraction citcuit 11. The output of the integral network 15 is set with this loop so that the average value of an error signal can be zero finally and a signal without offset can be obtained at the output of the deciding device 12. Thus, an offset erasing cirucit advantageous for the circuit integration can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an offset canceling circuit for removing uneasy offset stress from an input signal, and more particularly to an integrable offset canceling circuit for canceling offsets of analog automatic fixtures and the like.

FIG. 1 is a block diagram of an automatic fixture using a well-known transversal filter. In this transversal filter, an input signal is input from the No. 44 input terminal 1 to the tapped delay line 2, and the valley tap output of this delay -2 is connected to the multiplication circuit 3.
4.5 is provided to perform weighting, and after adding the output of each Norii device in an adder/subtractor circuit 6, a signal is outputted as an output 8 via a judger 7.

Since this circuit is composed of analog elements, deviations from the ideal values of each analog element may cause an unnecessary offset in the output signal of the transversal filter. This offset degrades the data discrimination of the automatic equalizer. This is also a property that cannot be removed using conventional adaptive algorithms.

In order to solve all of the above problems, an automatic equalizer with an offset canceling circuit for removing the upper ml offset (patent application filed in 1983) was developed.
5-62936) was considered.

Figure 2 shows the offset cancellation circuit! In Figure 1, which shows the Il configuration as a block diagram, '+1' is a subtraction circuit, 12
is the judge, ]3 is the reduction circuit, 14 is the reduction circuit, 1
5 is an integrating circuit. In this circuit, the output signal of the determiner 12 and the input signal to the determiner 12 are subtracted by the subtracting circuit 1
3 and extracts the difference (referred to as a difference signal), and integrates it in an integrating circuit 15 via an attenuator 14, thereby estimating the offset amount. Then, the subtraction circuit 11 subtracts the estimated value of the offset amount from the output signal of the transversal filter (input signal input to the offset cancellation circuit). Through this loop, the output of the integrating circuit 15 is finally set to a value such that the average value of the error signal becomes zero, and a signal without offset is obtained at the output of the determiner 12.

FIG. 3 shows an example of a circuit configuration conventionally used for the subtraction circuit 11 and the integration circuit 15 of the offset cancellation circuit shown in FIG.

In the figure, the subtraction circuit 11 has a well-known circuit configuration consisting of an operational amplifier and resistors 111, 112, 113, and 114, and the apportioning circuit 15 is a Miller integration circuit equipped with an operational amplifier 21 and a resistor 151°5 capacitor 152. be.

Note that 31.32 is the subtraction circuit 11 0 input terminal, and 31.
is the output number 4N of the transversal filter with an offset (input signal to the offset cancellation circuit)
However, the output signal of the integrating circuit 15 is applied to 32, respectively. 33 is an output terminal of the subtraction circuit 11, which is led to the determiner 12 and the subtraction circuit 13. Mata again
is the input terminal □ of the integrating circuit 15, and the error signal is transmitted to the attenuator 1.
4' added via. 35 is the apportionment circuit 15
At the output terminal of , the input terminal 32 of the subtraction (b) path 15
be guided by.

The conventional example of the offset cancellation circuit has been described above, and this circuit has a subtraction circuit 11 and an apportionment circuit 15 pc@anti-111~
114 and 151 t- were used, which was disadvantageous for integration. In other words, since the resistor is formed on the semiconductor chip, 1) it requires a very large chip area; 2)
The resistance value may be set incorrectly, and the resistance may have a non-linear slope.
3) Since it requires a steady current, it has drawbacks such as high power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional offset eraser circuits mentioned above and to provide an offset eraser circuit that is advantageous for integration.

According to the present invention, the present invention includes a determination device, a first subtraction circuit for extracting the difference between the human power and the output of the 41J leg foot, and a resistor provided for integrating the output signal of the first integration circuit. a second subtractor circuit, which does not include a resistor, provided for subtracting the output signal of this integrator circuit from the input signal at an offset voltage and passing it to the input of the determiner. An offset cancellation feature characterized by the following features can be obtained.

Hereinafter F, - D showing an example! ! J blood? ! : Detailed explanation of the present invention with reference to: 0 FIG. 4 is a diagram showing an embodiment of the subtracting circuit and the integrating circuit constituting the offset circuit tl of the present invention.

In the same figure, 8 and 110 are reduced by 3III! 150 indicates the integrator circuits 4L, which are the subtractor circuits 11 in FIG.

Each corresponds to the integrating circuit 15. First, the subtraction circuit] OK2: i, 40 is the operational amplifier, 41.4
2 are capacitors each having a capacitance group called CLC2, 4
3, 44.45.46.47 is periodically opened and closed (OF
With a switch that repeats k'-(JN), 43.44.4
5 and 46.47 are interlocked with each other. On the other hand, in the apportionment circuit 150, - is a y4 ruen device, 51.52 is a capacitor with a capacitance value of C3C4, and 53.
54.55° is a switch that periodically opens and closes 4 times, and 53 and 54 and 55 and 56 are interlocked, respectively. Furthermore, in Fig. 4, C161 is the DC offset vL.
an input terminal of a subtraction circuit 110 to which an input signal including an input signal is added;
62 is Judgment 6 in Figure 2. 〒12 is the output terminal of the subtraction circuit 110 which leads to the output terminal of the subtracting circuit 110, 63 is the error signal or the input terminal of the integrating circuit 150 (child, θ is the input terminal of the integrator circuit 150 dedicated to )1. Lo
This is the winding leading to the input terminal of the l path 110.

Next, the operations of the subtraction -@110 and the apportionment circuit 150 will be explained. First, the apportionment path 150 is filled with the error voltage across the capacitor 51 and the terminal 63 by closing the interlocking switches 53 and 8.Next, the switch b3 and 54 are closed. By opening and then closing the associated switches 55 and 56, the accumulated charge in the capacitor 51 is transferred to the capacitor 52. Furthermore, the switches 55 and 56 are opened, the old switches 53 and 54 are closed, and the above operations are repeated periodically.

Therefore, in this integrating circuit, the error signal for each period is sequentially integrated into the output voltage by a factor proportional to the capacitance ratio (C, v/C4) of capacitors 51 and 52, and finally the output voltage is It is set to a value such that the average value of the error signal voltage is zero. This integrating circuit 150 and the output signal are
is led to the subtractor 110 by tl. Subtractor 110
charges the capacitor 41 to a voltage equal to the difference between the input signal and the output signal of the integrator by closing the associated switches 43, 44, and 45, and at the same time charges the capacitor 42 to a voltage equal to the difference between the input signal and the output signal of the integrator.
Discharge (1) drop).

Next, switch 43, 44, 451 knee open, then switch.

By closing channels 46 and 47, the charge on capacitor 41 is transferred to capacitor 42. Furthermore, switch Xun and 4
7 Fully open the canopy, close switches 43, 44, 45 again,
The above operation is repeated periodically. Therefore, in the dense state, an offset-free signal multiplied by the capacitance ratio (CI/cj) of the capacitors 41 and 42 is obtained at the output terminal 62.

As described above, in this embodiment, the use of resistors that are disadvantageous to integration is completely eliminated, and #:J! Circuit 110 and integral 1g circuit 1
50 and achieves the same effect as a conventional offset canceling circuit using a resistor. The switch used in this embodiment is, for example, a W8 transistor switch, and the capacitor is, for example, an electric current between the gate electrode and the inversion layer. Therefore, according to this embodiment, an offset canceling circuit that is very convenient for integration is provided.Furthermore, the conventional offset canceling circuit using a resistor requires a large amount of current. Compared to Honji m vs +
Since it requires only a transient current to charge and discharge the capacitor, it is also the best in terms of power consumption. In addition, whereas the characteristics of the conventional circuit depended on the uniformity of the resistors 111, 112, 113, and 114, the absolute values of the resistor 151 and the capacitor 152, and CT, in this embodiment, all the characteristics depend on the capacitance ratio (C1/C , and C3/C41, the influence of manufacturing process variations in the case of integration is also small.

In addition, the integration circuit 15 and the subtraction circuit used in the above +e example]
A configuration of 1 is just 1% and many variations are possible. In short, it is sufficient to configure an integrating circuit and a subtracting circuit that do not include resistors, and the present invention does not limit the constituent elements or the method of constructing these circuits.

Next, the present invention will be explained in detail.

Figure 5 is a professional diagram of an automatic fixture constructed using the off-top-4 erasing circuit of the present invention. The portion consisting of the signal input terminal 1, the tapped delay a22 multiplier circuits 3, 4.5, and the adder circuit 6 is the same as the conventional circuit shown in FIG. Subtraction circuit 1101 determiner]2. Subtraction circuit 13
．． Attenuator 14. The portion constituted by the integral (b) path 150 is the offset canceling circuit of the present invention explained in the above iP embodiment. Also, 22.23.24 is a multiplication circuit, 25.2
6.27 is an attenuator, column, 29.30 is an integrating circuit. In FIG. 5, the output of the subtraction circuit 13 is
．． 2 is also added to one input of each of 25, and the output of each multiplier circuit is passed through an attenuator 6° and sent via 27 to an integrator circuit 28.
．． Added at 29.30.

The output of each integrating circuit 28, 29, 30 is the multiplication circuit 3 described above.
．． 4.5 is led to each one input. Also, the multiplication circuit η
, 23. The input of each believer in 24 is a multiplication circuit 3゜4.5
Similarly, each tap output of the tapped delay line 2 is added.

In the circuit constructed in this way, the output of the subtraction circuit 13 is obtained, and the difference between the input and output signals of the gain and 12, that is, the running signal, is given to the circuits 3 and 4.5 to the power of Lr. The bundler, Nobunshun Une, was made, and Ta! Guzuki i@Nobugumi 2v Tanita,
The output q2M coefficient is automatically controlled to 1 so that the MJ register value is minimized. Furthermore, at this time, the integrator 15
Since the estimated value of the offset pressure that makes the half-average A11 of the error No. 1a zero is obtained at the output of 0, this value is subtracted from the booster circuit 6 and the offset pressure is output to the interrogator output 8. 1
．． F1g is obtained. In this way, in the application example shown in FIG. 5, the offset that occurs in the transversal filter output is removed, so it is possible to significantly improve the performance of the automatic cabinet made of analog circuits.

In addition, in the above application 1+il, the subtraction circuit 110° purple is used to convert the output signal of the transversal filter to the integration circuit 15.
Exactly the same effect can be obtained by removing the offset by subtracting the output of () or by controlling the threshold voltage of the determiner 12 with the output of the integral 101M15g.

As described above, according to the present invention, it is possible to obtain an excellent offset cancellation circuit that is suitable for offset cancellation of analog automatic equalization amounts, etc., and is easy to integrate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a well-known automatic equalization amount, FIG. 2 is a block diagram of an offset canceling circuit, FIG. 3 is a circuit diagram of a conventional offset canceling circuit, and FIG. 4 is an embodiment of the present invention. FIG. 5 is a block diagram of a temple fixture showing an example of the application of the present invention. 2...Tapped delay line, 3-5...Multiplication circuit, 6
1. Addition circuit, 7/II regulator, 11... Subtraction circuit,
12... Judgment image, 13... Subtraction circuit, 14-reducer, ]5... nJ circuit, 20. kl - performance x4 width unit, 111~114.151...Resistance L 152...
・Capacitor, 4υ, 60... Performance'JIIJ-Amplifier, 43~4r', 53~56... Switch, 41
．． 42.5L 52... Capacitor, O~Sae... Multiplier circuit, 25-27.0. Diminishing device, 4-Seki...integrator circuit. Susumu C Representative Patent Attorney Hara Uchi 1 Figure 1 Figure 2

Claims (1)

[Claims] A determiner, a first subtraction circuit for extracting the difference between the human power and the output of the determiner, and a resistor provided to suppress the output No. 16 of the cumulative subtraction circuit. The output signal of this integrator circuit is drawn from the input No. 16 on which the offset voltage is superimposed, and the resistor provided to connect it to the input of the device is connected. J with no second subtraction circuit
4. An offset erasing circuit characterized by comprising four parts.