JPS5833294A - Electronic musical instrument sound suppression device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sound generation suppression method for an electronic musical instrument that generates musical tones using a positive mapped wave synthesis method.

2. Description of the Related Art Various electronic musical instruments have been developed that are capable of generating musical tones with arbitrary tones by synthesizing positive and forward waves.

The present applicant has also proposed in Japanese Patent Application No. 56-36595 regarding an electronic musical instrument that uses such a forward wave as a sound source waveform. By the way, it is possible to realize an electronic musical instrument capable of generating musical tones containing multiple overtones.By the way, in such an electronic musical instrument, according to the Sunfling theorem, frequency components of 1/2 or more of the frequency of the nanopulling clock can be realized. It is well known that distortion called aliasing occurs when any musical tone contains aliasing, and for this reason, it is often necessary to suppress the pronunciation of high-order clear tones. The above-mentioned proposal of the present applicant is insufficient to prevent an arbitrary musical tone or overtone of a predetermined order from being produced for a predetermined period of time. That is, in Japanese Patent Application No. 56-36595, if the phase address is a and the envelope information is 2, bc is used to perform multiplication.
However, in such a case, in order to suppress the pronunciation, it is necessary to set z = O, and there is a problem that control becomes difficult, especially when time division multiplexing is performed. This was done in response to the above-mentioned situation F, and its purpose is to provide a sound generation suppression method for electronic musical instruments that can suppress the generation of the above-mentioned arbitrary musical tones or overtones of a predetermined order using a simple method. It is to be.

An embodiment of the present invention will be described below with reference to the F1 drawing.

#! FIG. 1 is a circuit configuration diagram of the main part that generates the frequency f under the control of an OPU (central processing unit, not shown). That is, the above 0PtJ is the frequency information according to the operation f14 on the keyboard (shown 4), and the control number according to the operation output of various external switches.
It outputs signals, etc. and feeds them to the circuit shown in FIG. Thus, the circuit shown in Fig. 1 generates musical tones according to the time-division processing operation of four channels. In Fig. 1, l is a frequency information register, and OP
The frequency information from U is input via the gate circuit 2. This frequency a+*m register 1 is made up of four 20-bit shift registers connected in a cassgate in order to perform L6 for the above-mentioned 4-channel time-division processing operation, and is also driven by a clock ψlO (third tooth). Perform shift operation. The frequency information output from the four stages of 77 registers of the frequency information register 1 is applied to the adder 63, and is also applied to the first stage shift register of the frequency information register 1 via the gate circuit 4 and fed back. in this case,
The control signal ET from 0PtJ is directly applied to the gate circuit 2, and the control signal IN is applied to the gate circuit 4 via an inverter 5, which are controlled to open and close, respectively.

In the string, when the control signal IN is assigned to a certain channel, it is output as a "1" signal of the 21st direct-salt level at the timing of the channel, and at this time, the gate circuit M2 which is opened is The frequency H111t signal for the above operation is manually input to the first stage of the 14-wave number control register through 0-10,000. At this time, the gate circuit 4 is closed, and therefore the frequency H111t signal for the above operation is input from the fourth stage of the frequency tIj1 signal register 1. 0 and thereafter until the above operation is turned off and the channel is released.
At the timing of the channel, the control signal wfIN is output as a @0'' signal, and as a result, the gate circuit 4 is formed into a 7-41SfN, and the frequency information of the above operation is fed back and cyclically held. ing.

Adder 3 receives frequency ii1 from frequency information register 1.
and the phase address (phase address) fed back from the phase register 6, and as a result, the random phase tIf is calculated.
The 0 phase t# right register 6 is made up of four shift registers of valley 1 and 20 pits connected in cascade, and is driven by the clock ψ1G. The phase information output from the fourth stage is applied to the multiplier 7, and is also applied to the adder 3.
Therefore, the adder 3 and the phase information register 6 are circuits that perform JIK calculation on the frequency information to obtain the phase address af.

The multiplier 7 receives a signal XN based on the control of the OPU, and the multiplier 17 . is based on this signal XN,
Timings TO, TI, T2 within each channel described later
, T3, T4, the phase address af is multiplied by N (N
is positive mM)L, so add the resulting data Naf'J14
Then, at each of the above timings TO to T4, the value of the data N can be set to the #d number of true r
J), Therefore, the above-mentioned power JHH17 is, for example, 1der, the latch circuit 16 that latches this adder output, the #%1 input terminal of the adder, and the second input terminal, respectively, the above-mentioned phase address aft or the above-mentioned latch output (IIiJ d of the above No. 1d
Select the cut according to) ill! It is composed of K such as l1k6. As a result, 5-bit result data Naf will be output for each channel. Note that the most significant bit of the above result data Naf (12 pit 2 data) is the 5IGN bit representing the sign. Only this 5IGN bit is applied to the g1 input terminal of the adder 68 via the exclusive OR gate 9 (0 and the second input terminal of the adder 8 is applied to the exclusive OR gate) 10
The envelope value from the OPU is applied to the adder 11 via the gate circuit 12. This envelope value is set in advance by an external switch.
kL (Attack, Daikei, Susty/, Release)
Based on the information, OPU is activated when the performance key is turned on or off.
This is the data output and given from the gate circuit 41.
2, the envelope clock is applied to the gate circuit 1.
2 is opened, and the 0 adder 11 supplied to the mouth register 11 is also made up of 20 shift registers of envelope information registers connected in cascade, and is also driven by a clock ψ2 (IK3 diagram). . Then, the adder 11 adds the above envelope value and the data from the envelope information register 13 to create new processing/envelope information (current value of the envelope) and supplies it to the envelope information register 13. Further, the output data of the envelope information register 13 is also given to the exponential function conversion circuit 14.

The exponential function conversion circuit 14 has an attack part of the envelope waveform that is an upwardly convex curve 9, and a decay part and +
In order to make both the 717 and 1st parts form convex curves, thereby obtaining an ideal envelope waveform,
A circuit for converting the output of the envelope information register 13 into data showing an exponential change,
For example, a patent application by Sekihito Motoyama
6595) can be used. The envelope data output from the exponential function conversion circuit 14 is then given to the adder 8 via the above-mentioned exclusive orgs 1011 to 100.

The other end of the above exclusive or gate 9 is II! As shown in Figure 3, for each output of system clock φ1,
A 1m signal S which alternately repeats the level ``'' level is applied. Also, a signal φ signal from the sound generation control section 15 is applied to the other ends of the exclusive OR gates 1011 to 100 and the carry input terminal O4n of the adder 8. The details of the sound generation control unit 15 will be described later, but the sound generation control unit 15 controls the output state of the iIi φm according to the control information from the OPU and the control information from the OPU. 0 As can be seen from Figure 3, the signal ψ is 1 at level 11.
The timing at which the signal S is outputted as a signal No. 11 is the same as the timing at which the signal S is outputted as a signal No. 11 at the level "1". Therefore, No. 111 S and No. 16 ψmu are 10'''
When outputting as a level signal, the adder 8 adds the input data to the first input terminal and the input data to the second input terminal, and transfers the resulting data to the correct wave ROM section 25.
Give as hair dress day 0.

When the signal S and the signal ψ are both output as @1'' level signals, the adder 8 outputs data obtained by inverting only the level of the 8IGN pit out of the data from the multiplier 7, and an exponential function. The envelope data from the conversion circuit 14 is added to the data expressed in two's complement representation, and the resulting data is provided to the positive d-wave R, 0Mg 16. Waves are generated one after another when No. 1116 S and signal φm are both @0'' level, and the frequency is the same as the 9 sine wave, and the thick stone of the phase shift image is the same and the shift direction is opposite. , toward 0, where the positive and negative signs are opposite sine waves to the east.
The details will be described later using mathematical formulas.

On the other hand, when the signal S is output as @1" level and the 16th ψ is output as 11t of 10" level, addition #68
adds the data obtained by inverting only the level of 5IGN bits of the data from the multiplication section 7 and the curve/velope data mt≠~≠ from the exponential function conversion circuit 14, and converts the resulting data into a sine wave. It is given to the ROM section 16. In this case, four negative sine waves are output from the positive arc wave ROM 116, but these nine waves are different from the positive nine waves that were successively output when both the signals S1 and ψ are at O'' level. The frequencies are the same, and the magnitude and shift direction of the phase shift are also the same, that is, they are sine waves with different numbers.

In the sine wave ROM section 16, Seisha gL<
v i, /gL) @嘱11 is memorized - and this positive wave output from the OM section 16φ is given to the lA calculator 617, and every output of the system clock ψ1 is accumulated. The accumulated data of this system J11t17 is latched into the latch 18 when the clock φ40 (see figure 43) is output, and then sent to the amplifier and speaker (both shown as 4 in the figure). Its contents are cleared at the timing of φ40. Therefore, the system calculation data latched by the above latch 18 has a maximum of 4
This value is the cumulative value of positive and forward waves of 0.01 m.

The specific configuration of the sound generation control section 15 will be explained with reference to the following KIIZ diagram. The wave suppression register 21 can create 5 types of overtones (harmonics) for each channel, and a total of 120 types (for example, 4 chords x 5 overtones) for all channels.
Of these, there are 69 registers for inputting and storing control data to suppress sound generation, and 20 registers with a capacity of 1 bit are cascaded III! In addition, the clock φ
The input of control data for suppressing the sound driven by the spirit is (flli of the musical tone to be assigned by JPU).
Data N determined based on f and output by the OPU
gW L) AT input is AND gate 22, OR gate 2
3 to the first stage of the high-wave suppression register 21. Further, the output of the high-wave suppression register 21 is returned to the first stage of the high-wave suppression register 21 via an AND gate 24 and an OR gate 23, and is also given to an AND gate 25. gate 22
The control m=*rN is directly applied to and the AND gate 2
4 is applied with a control signal IN via an inverter 26, and is controlled to open and close, respectively. The control signal IN is the control signal IN for controlling the opening and closing of the 17th gate circuit 42.4.
This is the same signal.

The weight mode set register 27 is a register that stores time data for setting a weight shape by delaying the start of the overtone envelope attack by an arbitrary amount of time, and is a register that stores 20 shift registers with a capacity of 4 bits in cascade*d. It is also driven by a clock ψ2. The above time data is set by operating an external switch, and the data N・gW L>
AT people are AND gate 281-284, OR gate 29
1 to 294 jl'' and wait mode set register 2
The 701st stage is powered by humans. The time data output from the nine-wait mode set register 27 is processed by the AND gate 3.
01 to 304 are sent to the first stage KM111 of the wait mode set register 27 via the OR gates 291 to 294 and held in circulation. The AND gates 281 to 284 are directly applied with the control signal IN, and the AND gates 301 to 304 are connected to the inverter 33.
The wait mode count register 32 has the same configuration as the wait mode set register 27, that is, 20 shift registers with a capacity of 4 bits are connected in cascade. 0 driven by the clock ψ2 and the output of the wait mode count register 32 are given to the half adder 34 and the coincidence circuit 31, and the half adder 34 executes a +1 operation when the clock φ2 is output. The result data is fed back to the first stage of register 3200 for wait mode counting via AND/GO (AND GO) 351 to 354, and is prepared for the next +1 addition.

On the other hand, the signal KEYON output when the key is turned on is sent to the key-on register 37 via the OR gate 36, and to the AND gate 39 via the inverter 38;
40 to the weight registers 41, respectively. The key-on register 37 is a register for storing the on/off state of the key, and has 20 registers of 1/1 pit connected in cascade, and is driven by a clock φ3. The output is sent to the first stage Kmm of the key-on register 37 via the AND gate 42 and the OR gate 36, and is also provided to the AND gate 39.

The AND gate 42 is also controlled to open and close by being manually supplied with a signal KgYOF'P which is output when the key is turned off via an inverter 43. The output of the friend AND gate 39 is given to AND gates 351 to 354 to control opening and closing.

The weight register 41 is a register that stores keys (overtones) to which weight shapes are set, and is made up of 20 registers with a capacity of 1 bit connected in cascade, and clock ψ2.
Driven by. The output is fed back to the first stage of the wait register 410 via the OAG) 40, and
A coincidence detection signal from the inverter is applied to an AND gate 44 via an inverter 46 to control opening and closing of the AND gate 44 .

The output signal B of the AND gate 25 is given to the AND gate 47 as an opening/closing control signal. The signal S is applied to the AND gate 47, and the output of the AND gate 47 serves as the signal φm.

Next, the operation of the above embodiment will be explained with reference to FIGS. 3 and 4. The frequency information register 1 has a frequency range up to 4m. That is, for example, sound, 11i0
s, B intention, A3, G! When 41- and - of 41- are operated at the same time, four frequency a1# signals indicating the pitch of each key are output from the OPU and set to the assigned channels in the frequency information register 1 via the gate circuit 2. be done. After that, during the ON operation of each key, each frequency information is transmitted to the subsequent stage 91! for each output of the clock ψ1o! The IKs are sequentially lifted and held in circulation.

The above frequency information is given to the digital calculator 3 and added to the output data of the phase information register 6. This adds −
From B3, a new phase information, ie, a phase address af for the next step (corresponding to information addressing the next number point in the justice wave ROM section 164C) is created. Therefore, this phase address a/ is the above-mentioned interval 03.
, Bz, As, and G2. Further, the phase address aj is shifted by the clock ψ10 and is then given to mxm3 and the multiplier 7.

jll! The A part 7 is also given the 1H No. XN output from the OPU 9, and the *X part 7 is given this No. 16 XN
According to the contents of , the result data N a j' of type 54111I is outputted to the first input terminal of the adder 8 for each channel.

In Figure 3, the timings PO, PI, B2,
B3 indicates the timing of each channel in which the frequency information register 1, the phase information register 6, etc. perform a time-division operation for each output of black and φ10, respectively. Furthermore, the timings TO%TI, T2, T3, and T4 respectively indicate the timing of the time-division operation that is further executed by the multiplier 7, the /Illi unit 8, etc. for each output of the clock φ2 at each of the above-mentioned timings Po to P3. It shows.

Therefore, the multiplier 7 outputs, for example, result data af, 2 at each timing TO to T4 within the timing Po.
a/, 3a/, 4ajs 8a/ output. Also, all <11 at the valley timings TO to T4 within the timings P1 to P3! ] tJ is 0 history a/, 500 million result data, 5a/, 'Iaj, 9a/, lla/, 13a/
It is possible to output various outcome data such as 5afA result data.

On the other hand, the addition 511 includes the pitches 03, B2, A2, G
! Attack, decay, sustain, and release envelope values are applied via the gate circuit 12 at respective timings in accordance with the on and off operations of the respective rays. Then, the pain generator 11 adds the envelope value to the output data of the envelope information register 13, and accumulates the total amount.
New engineering/pelope information is created and envelope 1
'ft information register 13. And the envelope information clock ψ in the envelope t'#fi register 13! Therefore, the index t*a conversion circuit 14 outputs each timing TO1T1 . For each T2, T3, and T4, the finger j & FJA number will be converted and a new envelope data will be output, and on this envelope day, the evening will be exclusive OAG) 101s to 100 /10:J! 6g
The #J river is sent to the second input terminal of.

Now, the musical tone that suppresses pronunciation, that is, the suppressing harmonic (i
Assume a case where no overtones for setting l*f) or weight states are specified.q In this case, all I11@ data is stored in the harmonic suppression register 21 in the sound generation control section 15. , In addition, in the wait mode set register 27, @o@ data is held in rotation (that is, in this case, the pitches 03, B2, A
! , each signal KgY supplied at key-on of each key of G2.
When ON is in the wait register 41, it becomes “0” immediately.
Therefore, the output signal E of the AND gate 25 becomes abuse @l@, which synchronizes with signal 8. The signal φm is output from the AND gate 47,
Exclusive OR Gate 1011-100. In addition, 448 carry human power QjsVc are respectively applied. Also signal S
is marked V in the exclusive OR gate 9.

In the above state, the timing PO is now sounding 1g1
It is assigned to Ren's time-sharing processing channel of 60i, and the contents of No. 16 XN are data a/, 2a/, 3a.
Let us further assume that the multiplier 7 outputs /, 4a/, 8a/. In this case, the adder 8 uses the above timing 2.
At each timing TO to T4 of 0 yen, calculations in different states are executed when the signal 8 is at the 10@ level and when it is at the "'1" level. That is, when the timing money is 0,
The above data a/ is applied to the first input terminal of the addition H'ti 8. When the signal S is @0@ level, the 5IGN bit of data af is impressed as is, and on the other hand, when the signal S is "1" Vpel, the level of K is inverted and applied to the 5IGN bit. .

On the other hand, the signal φ is @0 at the input terminal 2 of the adder 8.
At the time of the level, the envelope data from the exponential function conversion circuit 14 is applied until that time, and the signal φm is applied to the level 11.
At @level, envelope data expressed in 20's complement? applied.

Therefore, at the above-mentioned timing TO, when the signal ψm is "0 level", the adder J148 adds the data a/ and the envelope data, and addresses the sine wave ROM@16 with the resulting data. When the level is 11@, the data a/ whose sign is inverted and the envelope data expressed in two's complement are added, and as a result, the data is busy and the sine wave ROM section 16 is addressed.Therefore, from the sine wave ROM section 16, , two types of pitch 03 (fundamental) and in waves will be produced one after another.
The nine waves are sine waves with opposite polarity signs, the same frequency, the same phase shift, and opposite shift directions.

In the other timings T'l to T4 in the above timing PO, the addition 480gt input terminal has data 2a/,
3a/, 4@/, 8a/ are applied, and the signal S is @θ
``'' level and "l" level, respectively, the same human power area as at the time of timing TO above is carried out 0 and addition Jl
The input state of the envelope data to the s2 input terminal of the instrument 8 is the same as the above-mentioned timing TO. Therefore, at timings T1 to T4, the second harmonic of the sound Qs (fundamental tone),
Each of the 3rd overtone, 4th overtone, and 8th overtone sine waves is generated one after another by 24JA, and the relationship of polarity, frequency, and phase shift in the 24-J@ sine wave of each overtone is the same as that for the fundamental tone above. It is.

Timings P1, P2, and P3 are the pitches 83 and A, respectively.
Assuming that each timing Pi is assigned to the time-sharing processing timing for the frustum of z, ()s,
, P2, and P3, the fundamental tones of pitch 82, A2, and G1, and their 2nd, 3rd, 4th, and 8th harmonic sine waves each have 2 horizontals, 1 to 4, and 81 regular waves. ROMg16
It is published one after another. In this case, the relationships among the polarity, frequency, and phase shift of the nine waves of the two-tooth type are as follows from the above table to
The timing sine wave is 0 accumulated at each output timing of the clock φ1 in the system g41'l, that is, the timing PO
Then, the timing TOK and the two system clocks ψ1
At the 0th timing TI, where 200 million sine waves of ringing f (pitch 03) are output and 200 million sine waves of ring f (pitch 03) are accumulated, a sine wave of 2 times i is further generated for the above accumulation 1 shift. # & be sniffed. Similarly, at timings T2゜'v3 and 'f4, each of the 3rd overtone, 4th overtone, and 8th overtone is 241 times higher than the accumulated direct up to that point.
Type 1 sine waves are accumulated.

Timing P1, P2. In P3, do the same and set the pitch to 82.
, A2, and G2 as fundamental tones, and their second, third, fourth, and eighth overtones are accumulated in an accumulator 17, respectively.

And, in this prefecture, a total of 40 pieces were numbed by pain 417 (241 torture x 44 g! - sound X (including the fundamental tone) 5 overtones)
The positive wave of 0 is transferred to the latch 18 when the clock ψ40 is output, and is transferred to the outside.
It's obvious that it's Knobbling Clock y) ao0
Then, the accumulator 17 accumulates the result data of the time-sharing processing of PO to P3, transfers d of it to the latch 18 at the timing of clock φ40, and clears its own contents. The operation when performing a performance in which a musical tone whose pronunciation is to be suppressed is specified will be explained. Now assume that the timing is PO~0, and the 4th and 8th harmonics of the musical tone of 40s are suppressed. Therefore, the OPU inputs data ``O'' into the harmonic suppression register 21 in the sound generation side 1 section 15 at timing 'r3, T4 in the timer/g PO, while inputting data 11'' at other timings. Set it. Therefore, this data is outputted from the OPU as data N113W DATA, inputted to the harmonic enhancement register 21 via the AND gate 22 and the OR gate 23, and thereafter cyclically held via the (1/AD gate 24).

In addition, the wait mode set register 27 contains, for example, the data required to set the wait mode by setting the above measurements to a predetermined number &1 from the second juice of all channels, delaying the start of the attack, and setting the wait mode. It will be supplied from. The time data that specifies this wait mode is
You can have Taniura So- and Taniura 4-Gebo different, or conversely, you can have 6 C with the same weight. And at the above time +th
t1 data is data Ngw oAr person and te OP U
0 is output from the AND gates 281 to 284 and the OR gates 291 to 294 and input to the wait mode set register 27, and thereafter the AND gate 30
1 to 304 are held in circulation.

Then, perform keyboard operations. The time chart shown in Figure 3 shows the case where 4fa is not operated at the same timing, and the overtones of the musical notes that are quaid-like ducks differ depending on the change in the envelope. 0 However, let us now consider a musical tone with a pitch of 83. In other words, pitch B! In response to the key operation, the signal KEY ON is stored in the register in the key-on register 3 corresponding to the timing TO~''r4 in the timing P1. The signal KgY ON is also applied to the register.Therefore, the data in the middle-on register 37 is held in circulation through the AND gate 42, and the data in the wait register 41 is held in the AND gate 44.
JJII is retained.

On the other hand, the key-off register 37 outputs the 11@ signal at every timing 'rO to T4 within the above-mentioned timing PI, and in response to this, the AND gates 351 to 354 are opened every time the AND gate 39 outputs t''111. , for the output data of the wait mode count register 32) 1
- New data that has been increased by +1 by the fader 34 is applied to the wait mode count register 32 via the at gates 351 to 354. by the way,
For the fundamental tone (0 corresponding to the timing 'I'OKn), the contents of the wait mode set register 27 are all '''O@ so as not to take the wait mode, and -*A coincidence output is immediately obtained from the circuit 31. , Therefore, the register of the weight register 41 corresponding to this fundamental tone is set to 0@, and Il1 No. E output from the AND gate 25 is always set to 1@ at the timing of rO within the timing of this Pl. 〇, the data in the wait mode count register 32 becomes very difficult by 1 every time the above timings PO to P3 go through one cycle.
1, it is detected whether or not the time data matches the above-described corresponding time data set in the wait mode set register 27. Then, the match circuit 31 detects a match, and the corresponding bit of the wait register 41 is changed to "0°IIC#," and the wait mode is stopped. That is, during the wait mode, the output of the inverter 45 is 10@, the control signal E output from the AND gate 25 maintains the state of 0@, and as a result, the lock signal φ is no longer output.

Each of the above, ]I! When dL light is performed based on the stripe 3 diagram in the operation state of each part described above after turning on, 7'-ta @ is sent from the rope wave suppression register 21 at each timing T3 and T4 within the above timing PO. When θ'' is output, the AND gate 25 is closed, so the output No. 4II E of the AND gate 25 becomes @0'', and at the timing r3 and T4 of the above timing POI/3, the output level of the signal φm is remains “0”. On the other hand, at each timing other than timing r3 and T4 within the above-mentioned timing Po, data 11'' is output from the A-wave suppression register 21, and the AND gate 25 is opened. At timings other than timing 'ra and T4, timing 'rl to T4 within timing Pl
, timing T3 within timing P3, data "1" is output from the wait register 41 at the trough timing of 'r4, and as a result, the output of the inverter 45 becomes 'θ'', which is applied to the AND gate 25. Therefore, the AND gate The output No. 1d E of No. 25 becomes "O" at timings T1 to T4 within the above timing p> and timing T3 within timing P3, = 1'4, and then No. 1!1!! No. ψ The V-bell of the frame is set to IQII.This state continues until the 11 o'clock data in the wait mode cacunto register 32 matches the corresponding o'clock 1 data in the wait mode set register 2. do.

The output state of the No. III φ arm shown in FIG. 3 shows the state at the time mentioned above. Therefore, at timings T3 and T4 within timing Po, the signal ψ^ becomes @01, so when the signal S is @0@ level, K is the data 4a/or data 8aj and the valley envelope gater. and the resulting data is Ejt wave H,0Mg
Address 16. Also, when signal 8 is 11@,
The data 4a/ or data 8a/ whose sign has been inverted, respectively, and the valley enpelogue data are added, and the resulting data is used to address the justice wave ROM 4t6. Therefore, at timing T3, the 200 million sine waves successively output from the positive nuclear wave ROM section have the same frequency, the same phase shift size and the same shift direction, and only the sign is a 4-way trough. nine waves, and therefore these two
The radial sine wave is outputted to the system 4 unit 17 and the resultant data is "0", that is, the upper 1c! 4 times high: The sounding of the J4 wave is suppressed.

Also, at timing T4, two sine waves with exactly the same sign and the sign of the 8th overtone being #4 are generated one after another, and the sine wave is
1st shift is rOJ9, the harmonic of the above 81 tones l) element i is suppressed.

In this way, according to the data set in the C1 harmonic suppression register 21, the 41
This suppresses the 4sai, 8th overtone, and the S-wave emission in one sound, and prevents the occurrence of distortion called 1ria 7/g.

In the situation shown in Figure A3, timing TI-T4 within timing Pl. The same operation as described above is performed at timing P 3 and timing T3 and r4 of ``().
Overtones, 81-1-1! ) 4 @ sound with 6 sounds and pitch 02, B1ff sound valley 1 * sound pronunciation stops at 1 hit n
, the trend of Kuwait is set in a big way. That is, Fig. 44 shows an example of envelope forming to give 6 fK, and in the figure,
During the period when WAIT is displayed, the start of the attack from the key-on will be delayed by 4 times, regarding the above-mentioned valley attack where the attack is immediately stopped.

To explain using the above-mentioned production C-shaki, the envelope data in which the 9 degrees mai-shiki sekihahentai-kaifu 14, which looks like an arrow, is exposed is represented by the symbol E (this may take a different value for each harmonic). , To simplify the explanation, all are expressed as @B@.)
O is expressed by K. First, a case will be described in which both harmonic suppression and weight-like setting are not performed. That is, at timing TO, when the signal S is at the "0@ level," the data a/ is applied to the first input terminal of the adder 8, and on the other hand, the envelope data B is applied to the second input terminal. Therefore, the resulting data is af + B, and this data is a positive wave (
This rounded sine wave supplied to the JM unit 16 is s in 2rC-"j+"
-・Kuroku formation 11). However, n is t/number of pull points.

At the above tying TO, t) tS>1"1" L
/ At the time of hell, # of gas! Data af whose sign has been inverted is stamped on the one-person trend, and the sine wave generated from two fans is as follows. ' Therefore, the cumulative value of the accumulator 17 at the end of timing TO is as follows.ノ”−′ 2°−′p (Mi y
At f'r t, T2, T3, and T4, adder 1
Data 2a/3a/, respectively, are input to the first input terminals of 8.
Since 4 a / and 8 a / are applied, the timing y
/Tl, '1'2, T3, T4M了4Ku, the above formula (3
) for system calculation 11[, the following equations (4), (5), +6),
The valley system straightness shown by (7) is the first-order system straightness.

That is, 2n-/F r' =20088a/x, 1n EL,, Open formula (7)
Therefore, the fundamental tone, 2nd overtone, 3rd overtone, 4th overtone, and 8th overtone of the selected musical tone are envelope data at valley timing zTO~'r4. It will be envelope controlled by FiK. That is, the envelope control l values of the fundamental tone and each overtone are both expressed by the following equation, 8).

Timing of the event being held 20 yen timing'r
3, since the signal ψ is at the “O” level, I
When M No. S is at the 10@ level, data 451/ is printed on the fg1 input terminal of /JOJI, j8, and envelope data E is printed on the second human power trend 4.
2< 4 a f-4-11, +H++Bui9)-
-11. 28 Furthermore, when the signal S is "1 level" at the above timing T3, the data 4a/ whose sign is inverted is applied to the 4-child of the 1st person of 0 calculation 48, and the data 4a/ whose sign is inverted is applied to the 4th child of 42 people. The signal ψ is turned on due to @0@level, so the upper ad 19) at the end of timing T3,
tlG's wooden nose 1 straight becomes rOJ, that is, 4 of high 05
The pronunciation of high IAtIL of 1 and 廿 is suppressed.

Also, the same reason applies to timing 'r4! At is suppressed at timing TI-T4 within timing P1. Timing P3. ), the suppression of the valley harmonics with a weighted - value at timing °r3 and T4 is performed for the same reason, and the start of the envelope attack is delayed by the set time: M.

Next, a method of envelope control using the above equation (8) will be explained. When the waveform is not output at the two key-on positions, the envelope data E may be set to [0]. Then, after key-on, if the envelope data E is gradually increased, the output level will increase.
2 (see figure fg4) is created. When the output level reaches the maximum, the envelope data E is gradually reduced to form a decay section. jMK envelope data E! If you keep it at a constant value, it will be a sustain state.Also, after the key is turned off, set the E/BELLOW data E to "0".
By gradually decreasing the size until the release part is created.

The case where each envelope state of the FiAD8 is input has been described above, but the control can be performed in the same manner when the envelope foreshadowing is M, such as an organ sound.

Furthermore, in the above embodiment, the number of time-division processing channels is four, but of course the number is not limited to this. In addition, in the above embodiment, one period of sine wave was stored in the positive wave ROMg16, but in addition to 4, 172 cycles M and 1/
The 4-cycle sine wave is memorized, and 1/2-cycle and 1/4-cycle sine waves are generated successively from the waveform memory.
A sine wave corresponding to the period may be created.

Furthermore, in the above embodiment, when trying to suppress sound generation, the output of the lock ψ system is set to llIlIgl.
In addition, the control unit 15 may control the timing to set the clock to φmt-"1"', for example.

As explained above, this invention uses a sine wave (or
Moxibustion)! To! Reads out the two positive and negative waves (or the remaining eight branch waves) according to the scale frequency from the stored waveform memory as two waveforms with the same frequency, opposite directions, and different signs with the same amount of phase shift. , and synthesizes the two consecutively generated waveforms to obtain one sine wave (or Yosha wave), and performs envelope control of the corrected wave (or Shayosha wave) by changing the phase shift) l. In the electronic musical instrument using the positive catfish wave synthesis method, the generation suppression is specified, and the two positive kaede waves (or yokujira waves) for the nine tones are generated with the same station wave number, the same direction, and the same violet phase shift. If we retrieve the waveforms from the waveform memory as two waveforms with different signs, what will happen if we retrieve them as two waveforms with different signs? Jj1. Therefore, we have provided a sound generation suppression method for an electronic musical instrument that suppresses the generation of the above-mentioned musical tones by synthesizing the nine successive waveforms and producing the synthesized output as a waveform. By specifying in advance the suppression of perspiration for musical tones that may cause aliasing distortion, it is possible to easily suppress the production of musical tones that are inconvenient for performance. Furthermore, if you specify the sound suppression time in advance when specifying the musical tone for which the sound generation is to be suppressed, you can also delay the start of the attack time by an arbitrary amount of time, making the performance even more effective. Further increasing one's ability becomes q-noh.

Furthermore, when the above-mentioned sound generation suppression method KiIk#I@time division processing method of the present invention is used, it is possible to generate musical tones including many overtones, and it is also possible to suppress the sound generation of each harmonic at any time. Therefore, in addition to freely suppressing overtones that cause aliasing distortion as described above, it is also possible to delay and excite only arbitrary overtones among the generated overtones. This has the advantage of increasing the o4 committee effect to *. In particular, the ability to easily obtain temporal changes in overtone components during attack is an M effect in imitating natural 4-jin.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the main part of an embodiment of this invention, @2
FIG. 3 is a detailed circuit diagram of the sound generation control section 15, FIG. 3 is a time chart for explaining the operation, and FIG. 4 is a waveform diagram of an envelope waveform for a musical tone to which a weight letter is set. l...Frequency information register, 3...Additional IE! ,6・
... Phase information register, 7... Multiplier, 8... Adder, 9°100~IQII... Exclusive OR gate, 1
1... Addition i, 13... Envelope information register, 15... Sound generation control unit, 16... Positive ξ point waveform U M
Part, 17...Register, 18...Latch, 21...
Harmonic suppression register, 27... Wait mode set register, 31... Coincidence field, 32... Wait mode set register, 34... Half adder, 37
...Key-on register, 41...Wait register.

Claims (1)

[Claims] (1) From the waveform memory that stores sine waves (or cosine waves), two sine waves (or overboard waves) corresponding to the scale frequency are generated with the same frequency, opposite directions, and the same amount of phase shift. By combining the two waveforms that are successively generated and generated as two different waveforms to obtain one sine wave (or cosine wave), and by changing the amount of phase shift, Controlling the process/pelope of waves) - In electronic musical instruments, for musical tones for which the suppression of pronunciation is specified, the above two positive waves (or aftercough waves) are controlled at the same frequency and in the same direction. A thread producing means that outputs two waveforms having different signs and which are phase-shifted from the waveform memory;
A sound generation suppression method for an electronic musical instrument, comprising a sound generation control means for suppressing the sound generation of the musical tone by synthesizing the two waveforms successively generated by R and producing a synthesized output. (2. In the sound generation suppression method for an electronic musical instrument as set forth in claim 1, the sound generation control means causes the synthesized output to become zero for an arbitrary suppression time from the key-on of the sound collection designation key. A method for suppressing sound generation for an electronic musical instrument, characterized in that it is equipped with a means for suppressing sound generation in an electronic musical instrument. ;3) Outputting frequency information corresponding to an arbitrary scale corresponding to each of a plurality of channels formed by a time division section jlK. Based on the frequency information output means and the frequency information output from the frequency information output means for each channel,
Fundamental tone addressing means for specifying the phase address of the fundamental tone; and harmonics for specifying the phase address of a predetermined a-th overtone by time-sharing processing within each channel according to the phase address of the fundamental tone specified by the fundamental tone addressing means. an address designation means, a waveform memory for storing the positive wave (To or extra core wave), an envelope information generation means for generating envelope information for each of the fundamental tone and overtone in each of the channels, and Based on each phase address by the addressing means and overtone addressing means, a phase Z shift is performed for the fundamental tone and overtone in each channel based on the above envelope information whose directions are opposite to each other and the same magnitude. a means for time-divisionally reproducing two positive waves (or negative waves) of the same frequency from the waveform memory; a synthesizing means for synthesizing, an inhibiting tone specifying means for specifying the fundamental tone or overtone to suppress pronunciation, and a fundamental tone tJ- specified by the inhibiting tone specifying means, when generating an overtone, the above-mentioned successive tone specifying means The operation is controlled to read out the two square waves (or cosine waves) from the waveform memory as two waveforms having the same frequency and direction, and having the same magnitude but with a 4@7 step and different signs. and a sound generation control means for suppressing the sound generation of the two wave sounds produced above.