JPS583353A - Delay detection circuit - Google Patents

Delay detection circuit

Info

Publication number
JPS583353A
JPS583353A JP56100518A JP10051881A JPS583353A JP S583353 A JPS583353 A JP S583353A JP 56100518 A JP56100518 A JP 56100518A JP 10051881 A JP10051881 A JP 10051881A JP S583353 A JPS583353 A JP S583353A
Authority
JP
Japan
Prior art keywords
circuit
delay
output
signal
modulated wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56100518A
Other languages
Japanese (ja)
Other versions
JPH0429265B2 (en
Inventor
Yoshifumi Toda
戸田 善文
Takayuki Ozaki
尾崎 貴之
Hisahiro Koga
古賀 寿浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56100518A priority Critical patent/JPS583353A/en
Publication of JPS583353A publication Critical patent/JPS583353A/en
Publication of JPH0429265B2 publication Critical patent/JPH0429265B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To keep almost constant phase amount with a delay circuit at all times, by returning a DC fluctuation component produced by frequency fluctuation of a modulated wave to the delay circuit via a loop circuit and variably controlling the amount of delay. CONSTITUTION:A delay circuit 20 consists of a shift register 20a and a voltage controlled oscillator 20b, and a delay modulated wave signal outputted from a tap of the amount of delay of one-bit or below of a base band signal of the circuit 20 is applied to a sinusoidal wave phase comparison circuit 22 and the phase is compared with the modulated wave signal from a terminal 10. The output of the circuit 22 varies the amount of delay of the circuit 20 according to the frequency fluctuation of the modulated wave with a loop circuit to the oscillator 20b via an LPF 24 and an amplifier circuit 26. Thus, even if the modulated wave signal has a fluctuation in frequency, the phase of the delay circuit can almost be kept constant.

Description

【発明の詳細な説明】 本発明は被変調波の周波数変動にょp生ずる復脚信漫の
アイパターン劣化を除去できるように構成し九遍延検波
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nine-way detection circuit configured to eliminate eye pattern deterioration of a reciprocating signal caused by frequency fluctuations of a modulated wave.

デシタル移動通信に訃いては、電力と屑#La帯域とを
有効に利用するため、■ 非線形伝送路に適金すること
、■ 占有周波数帯域幅が狭いこと等の条件を満足する
変調方式が要求される。前者■O条件を満足するもOと
して変調指数αsの位相連続なFmK変調方式(周波数
シフト中−インダ)即ちmt変調方式が存在する。しか
しながらこの変調方式の1まで杜、後者■の条件を満足
しない九め、変調ベースバンド信号に対してナイキスト
フィルタ等で帯域制限を加え、これによって■及び■の
条件を満足させるようにした変調方式が用いられる。
In digital mobile communications, in order to make effective use of power and the waste #La band, a modulation method that satisfies the following conditions is required: ■ Appropriate funding for nonlinear transmission paths, and ■ Narrow occupied frequency bandwidth. be done. There exists a phase-continuous FmK modulation system (frequency shift middle-indah), that is, an mt modulation system, which satisfies the former (1) O condition but has a modulation index αs. However, this modulation method does not satisfy the conditions (1) and (9), and the modulation method adds band limitation to the modulated baseband signal using a Nyquist filter, thereby satisfying the conditions (2) and (2). is used.

この種のM8に変調による変調波等の復調手段としては
、同期検波方式、遅延検波方式等が知られている。移動
通信においては、レーし−7エーゾング動作時、バース
ト毫−ド動作時及びプレス) −クオン・オフ動作時に
おける回路の引込み適度高速化及びシステムO構成の部
品化を考慮すると遅延検波方式が有利である。
As means for demodulating a modulated wave by modulating M8, a synchronous detection method, a delay detection method, etc. are known. In mobile communications, the delay detection method is advantageous when considering moderate speed-up of circuit pull-in during ray-7-aison operation, burst mode operation, and press-on/off operation and componentization of the system O configuration. It is.

第1図は従来の遅延検波回路のブロック園である。同図
に示す通シ、従来のこの種回路は、端子10を介して印
加される被変調波信号に対しベースバンド信号の1ビツ
トあるいは2ビ、部分の遅延量を与える遅延回路12、
被変調波信号と遅延被変調波信号との位相比IIRを行
う正弦波もしく社命弦波位相比較回路14、ローノ譬ス
フィルタ16及びデータ出力端子18から構成される。
FIG. 1 is a block diagram of a conventional delay detection circuit. As shown in the figure, the conventional circuit of this type includes a delay circuit 12 which provides a delay amount of 1 bit or 2 bits of the baseband signal to the modulated wave signal applied through the terminal 10;
It is comprised of a sine wave or sinusoidal wave phase comparison circuit 14 for performing phase ratio IIR between a modulated wave signal and a delayed modulated wave signal, a rhonus filter 16, and a data output terminal 18.

なお、遅延機tIL回路で通常用いられる正弦波位相比
較回路社、ベースバンド信号に対して帯域制限を行う九
変調方式を用いた場合には符号量干渉が著しく大きくな
〉復調信号のアイ・ぐターンが大きく劣化するため実用
にならず、従ってこのような場合に社符号間干渉に強い
余弦波位相比較回路が用いられる。
Note that when using the sine wave phase comparator circuit commonly used in the delay unit tIL circuit, the code amount interference is significantly large when using the nine modulation method that limits the band of the baseband signal. This is not practical because the turn is significantly degraded, and therefore, in such cases, a cosine wave phase comparator circuit that is resistant to intersymbol interference is used.

前述の如く、遅延検波回路は、同期検波回路に比較して
構成が簡単となシ、かつ同期外れ等がない利点を有して
いるが、従来O遅延回路は、遅延量が常に一定であるた
め、被変調波信号入力の周波数変動が生じると、この被
変調波信号と遅延回路で1ビツトもしくは2ビツト遍延
されて得られる遅延被変調波信号との位相誤差が大きく
1k〉、復調信号のアイツヤターンが劣化する問題を有
している。
As mentioned above, the delayed detection circuit has the advantage of having a simpler configuration and no loss of synchronization than the synchronous detection circuit, but in the conventional O delay circuit, the amount of delay is always constant. Therefore, when a frequency fluctuation occurs in the modulated wave signal input, the phase error between this modulated wave signal and the delayed modulated wave signal obtained by spreading 1 or 2 bits in the delay circuit becomes large (1k), and the demodulated signal The problem is that the eyelid turn deteriorates.

従って本発明状従来技術の上述し九問題を解消するもの
であ)、木兄−の目的は、被変調波信号の周波数変動が
生じても復調信号のアイパターンが劣化しないようにし
九遅嬌検波回路を提供することにある。
Therefore, the purpose of the present invention is to solve the above-mentioned nine problems of the prior art), and the object of the present invention is to prevent the eye pattern of the demodulated signal from deteriorating even if the frequency fluctuation of the modulated wave signal occurs. The purpose of the present invention is to provide a detection circuit.

上述の目的を達成する本発明の特徴は、被変調波信号を
遅延させる遅延回路、鋏遅延回路によりて遅延させた第
1の遅延被変調波信号と前記被変調波信号とを位相比較
する位相比較回路を備えた遅延検波回路において、前記
遅延回路からベースバンド信号の1ビツト以下の遅延量
を与えた第20遥延被変調波信号を取p出し、該第20
遥延被変調波信号と前記被変調波信号との位相比較を行
う正弦波位相比較回路及び鋏正弦波位相比較關路からの
出力信号を平滑してループ応答を定めるループフィルタ
を含む閉ループ回路をさらに設け、該ルー7回路の出力
を前記遅延回路に戻して腋遅嬌回路の遅延量を制御する
ことにある。
The features of the present invention that achieve the above object include a delay circuit that delays a modulated wave signal, and a phase that compares the phase of the first delayed modulated wave signal delayed by the scissors delay circuit and the modulated wave signal. In a delay detection circuit equipped with a comparator circuit, a 20th far-extended modulated wave signal p which has been given a delay amount of 1 bit or less of the baseband signal is extracted from the delay circuit, and the 20th
A closed loop circuit including a sine wave phase comparison circuit that performs a phase comparison between a far-reaching modulated wave signal and the modulated wave signal, and a loop filter that smoothes the output signal from the scissor sine wave phase comparison circuit and determines a loop response. The present invention further includes providing an output of the loop 7 circuit and returning the output of the loop 7 circuit to the delay circuit to control the amount of delay of the axillary delay circuit.

以下実施例によシ、本発明の詳細な説明する。The present invention will be explained in detail below with reference to Examples.

第2図は本発明の第1の実施例のツ四ツク図である・こ
の実施例鉱本発明の基本的構成から成るものである。同
図において、第1図と同一符号は同一部分を表わしてい
る。遅延回路16は、従来のものと同様に被変調波に対
してベースバンド信号01ビツト又紘2ビツトの遅延量
を与えるタッグの他に1ビツト以下の遅延量を与えるタ
ップを有している。即ち、遅延回路20はに段及び麗段
のシフトレジスタ20mと発振器20にとから成ってい
る。発振器20b紘後述するルーf回路逼ら印加される
電圧に応じて発振周波数が変化する電圧制御発振器であ
る。遅延回路2001ビツト以下の遅延量のタップから
出力された遅延被変調#Lll1号は正弦波位相比較回
路22FC印加され、端子10からの被変調波信号と位
相比較される。正弦波位相比較回路2201出力は、ロ
ーフ臂スフィルタから成〕、ループの応答を定めるルー
プフィルタ24を通シ、これKよ〉被変調波の周波数変
動に比例した略直流の信号が得られ、この信号を増幅器
26で増幅して電圧制御発振器20bO制御電圧とする
ことによ)、遅延回路200這延量が被変調波の周波数
変動に応じて可変となる・こOように本実施例で杜、正
弦波位相比較回路22、ループフィルタ24及び増幅器
26がルーfB路を構成している。
FIG. 2 is a block diagram of a first embodiment of the present invention. This embodiment consists of the basic structure of the present invention. In this figure, the same reference numerals as in FIG. 1 represent the same parts. The delay circuit 16 has a tag that provides a delay amount of 01 bit or 2 bits of the baseband signal to the modulated wave as well as a tap that provides a delay amount of 1 bit or less, as in the conventional one. That is, the delay circuit 20 includes a two-stage and two-stage shift register 20m and an oscillator 20. The oscillator 20b is a voltage controlled oscillator whose oscillation frequency changes according to the voltage applied to the loop f circuit (to be described later). Delayed modulated signal #Lll1 outputted from a tap with a delay amount of 1 bit or less in the delay circuit 200 is applied to a sine wave phase comparison circuit 22FC, and is compared in phase with the modulated wave signal from the terminal 10. The output of the sine wave phase comparator circuit 2201 is passed through a loop filter 24 (consisting of a loaf-arm filter) which determines the response of the loop, and a substantially direct current signal proportional to the frequency fluctuation of the modulated wave is obtained. By amplifying this signal with the amplifier 26 and using it as a control voltage for the voltage controlled oscillator 20b, the amount of delay circuit 200 can be varied in accordance with the frequency fluctuation of the modulated wave. 2, a sine wave phase comparator circuit 22, a loop filter 24, and an amplifier 26 constitute a loop fB path.

遅延検波回路の復調原m社次の通りである・被変調波信
号・(1)を次式で表わす亀のとする。
The demodulation source of the delay detection circuit is as follows: - Modulated wave signal - Let (1) be a tortoise expressed by the following equation.

・(1)冨a−−(・、t+デm(t) )     
−(x)但し、ω。:被変調波信号の角周波数 ψm(t) : kMjK変調による位相変化分遅延回
路において遅延量Tだけ遵嬌させられ九遍嬌被変調技信
号・〜t)紘次の様になる。
・(1) Tomi a−−(・, t+dem(t) )
−(x) However, ω. : Angular frequency ψm(t) of the modulated wave signal : A delay amount T is complied with in the phase change delay circuit due to kMjK modulation, resulting in a nine-round modulated signal ~t) Hiroji.

・’(t−4)諺トaw(#。(t−4)+す、(t−
f))−(2)正弦波又は余弦波位相比較回路14の出
力は・(1)・・’(t−f)となpローI譬スフイル
ター6を通すとその出力!(*)a次の様になる。
・'(t-4) proverb aw(#.(t-4)+su,(t-
f)) - (2) The output of the sine wave or cosine wave phase comparison circuit 14 is...(1)...'(t-f) When passed through the p-low I filter 6, the output is! (*)aIt will be as follows.

w(t)”=”−・。’+?m(t)−few(t−τ
))  −(3)2        、、、。
w(t)”=”−・. '+? m(t)-few(t-τ
)) −(3)2 ,,.

正弦液位相比I2@路O場金の一一/譬スフィルタ16
の出力11g(1)とすると 2 !、(t″PI−−1(−(t)−pm(t−r)) 
    −(4)となる・ 但し、礎。t−(2K −) IK* r−(N−A%
cs、 eK:整数、Tc&:発振器2(10発振周期 余弦波位相比較回路の場合のロー・奢スフィルタ16の
出力をwe(t)とすると となる。
Sine liquid phase ratio I2
If the output of 11g(1) is 2! , (t″PI--1(-(t)-pm(t-r))
−(4). However, the foundation. t-(2K-) IK* r-(N-A%
cs, eK: integer, Tc&: oscillator 2 (10 oscillation period, cosine wave phase comparator circuit). Let we(t) be the output of the low/luxury filter 16.

但し、−0j 冨2g K 、 r−CN−T ) T
 CL  I K :整数1丁c1:発振@20にの発
振周期一般に、正弦波位相比較回路を用いる場合は、T
中丁(ベースバンド信号の1ピット分)、余弦波位相比
較回路を用いる場合は、fwtテあるいはT#2!に選
定される0 被変調波信号の角周波数が十ノω・変化すると(3)式
は次のようになる、。
However, -0j 2g K, r-CN-T) T
CL I K: 1 integer c1: Oscillation period of oscillation @20 Generally, when using a sine wave phase comparison circuit, T
If you use a cosine wave phase comparator circuit (for one pit of the baseband signal), use fwt Te or T#2! 0 If the angular frequency of the modulated wave signal changes by ten ω, equation (3) becomes as follows.

n1□) (6)式において十ノ・。τの位相誤差が(pj*)−
pm(t−リ)と比較し無視できなくなると復調信号の
アイ−ターンは著しく劣化する・余弦波検波復調アイI
譬ターンについて被変調信号の周波I&が変動しないと
きは例えば第8図に示すものとなるが、周波数が変動し
九とti社g4図に示すものとなる。九だし、両図共2
ぜット逼延0場合″Cある・一方、本発明において紘前
述の如く周波数変動に対応して遅延検波回路20の電圧
制御発振器20にの発振周波数を制御し、遅延量を制御
する機能を有するものであるから復調信号の87N劣化
を畦土することができるものである。
n1□) In equation (6), ten. The phase error of τ is (pj*)−
The eye-turn of the demodulated signal deteriorates significantly when it cannot be ignored compared to pm(t-li). Cosine wave detection demodulation eye-I
For example, when the frequency I& of the modulated signal does not vary, it will be as shown in FIG. 8, but if the frequency changes, it will be as shown in FIG. Nine dashi, both figures 2
In the case of zero delay, there is "C." On the other hand, in the present invention, as described above, the function of controlling the oscillation frequency of the voltage controlled oscillator 20 of the delay detection circuit 20 in response to frequency fluctuations and controlling the amount of delay is provided. Since it has this feature, it is possible to eliminate 87N deterioration of the demodulated signal.

次に、本発明によるループの応答を示す。Next, the response of the loop according to the invention is shown.

”         −(7) v、s+±G ’ y−^、・TI−f俤)が ±j町、m±1G’ i”ノ・。・yf、 )’ll)
g−±に、−jss、−Fli)−(8) (5)式より、 ω、ymg[lll、 ym(N−y )”cl−”)
被変調波信号の角周波数がω。士ノω、変動すると、オ
ープンループの場合、 クロ′−ノドルーグの場合、 (伽。±ノー、)(T干jr)冨2KK±71    
    、−、Hとなる。
"-(7) v, s+±G' y-^,・TI-f俤) is ±j town, m±1G'i"ノ・.・yf,)'ll)
g−±, −jss, −Fli)−(8) From equation (5), ω, ymg[ll, ym(N−y)”cl−”)
The angular frequency of the modulated wave signal is ω. When Shinoω changes, in the case of open loop, in the case of Kuro'-nodrug, (伽.±No,)(T时jr)冨2KK±71
,-,H.

の圧縮率をα−とすると、(7)〜(ロ)式よ)次の様
になる。
If the compression ratio of is α-, then the equations (7) to (b) are as follows.

べ 第5図は被変調波信号の周波数変動(±h5々つと増幅
器26の出力電圧との関係を示しておシ、周波数変動が
0(Ub)のときに出力電圧が3.0(至)の場合につ
いて表わされている。第6図は電圧制御発振器20bの
制御電圧に対する発振周波数優位(±j町し/211 
)の特性を示しているの第7図は被変調波信号の周波数
変動(ジ町/()K対する遅延回路200位相位相時性
を示している。第7図からも判るように、本発明の実施
例における被変調波の周波数変動に対する遅延回路20
0位相偏位の圧縮車線α−中0.2となる。即ち、被変
調波の周波数が変動しても遅延検波回路内の位相貴社は
ぼ一定に制御されるので復調アイパターンの劣化量は非
常に小さくなる。
Figure 5 shows the relationship between the frequency fluctuation (±h5) of the modulated wave signal and the output voltage of the amplifier 26. When the frequency fluctuation is 0 (Ub), the output voltage is 3.0 (to). Fig. 6 shows the oscillation frequency dominance (±j town/211
) shows the phase characteristics of the delay circuit 200 with respect to the frequency fluctuation (J/()K) of the modulated wave signal.As can be seen from FIG. Delay circuit 20 for frequency fluctuation of modulated wave in the embodiment of
It becomes 0.2 in the compression lane α- of 0 phase deviation. That is, even if the frequency of the modulated wave fluctuates, the phase within the delay detection circuit is controlled to be approximately constant, so the amount of deterioration of the demodulated eye pattern is extremely small.

を九、遍爾回路20の遅延量が温度変動、電源電圧変動
等によシ変動し九としても、位相比較回路14に印加さ
れる遅延被変調波信号と正弦波位相比較回路22に印加
される遅延被変調波信号とは同一の遅延回路20から出
力されるので位相量の変動を圧縮することができる。
Even if the delay amount of the loop circuit 20 changes due to temperature fluctuations, power supply voltage fluctuations, etc., the delayed modulated wave signal applied to the phase comparator circuit 14 and the sine wave phase comparator circuit 22 Since the delayed modulated wave signal is output from the same delay circuit 20, fluctuations in the phase amount can be compressed.

第8図は本発明の第2の実施例のブロック図である・同
図において、第1の実施例(第2図)と同一部分は同一
の番号で示されている0即ち、本実施例では、第1の実
施例のループ回路の正弦波位相比較回路22とループフ
ィルタ24との間に直流成分抽出回路として、q−パス
フィルタ28、直流阻止回路30及び差動増幅器32が
設けられている。
FIG. 8 is a block diagram of the second embodiment of the present invention. In the same figure, the same parts as the first embodiment (FIG. 2) are designated by the same numbers 0, that is, this embodiment Now, a q-pass filter 28, a DC blocking circuit 30, and a differential amplifier 32 are provided as a DC component extraction circuit between the sine wave phase comparison circuit 22 and the loop filter 24 of the loop circuit of the first embodiment. There is.

正弦波位相比較回路22の出力信号はローパスフィルタ
28に印加される。四−Δスフィルタ280出力信号波
形は籐9図に示す如くなる。九だし、同図(4)は被変
調波信号に周波数変動のない場合、俤)及び(C)はそ
れぞれ4・、、−j@I@D周波数変動Oある場合の波
形である・ ローパスフィルタ28の出力は、キャパシタ等から成る
直流阻止回路300Å力に印加されて被変調波の周波数
変動によって生ずる直流成分の変動を除去した基準信号
となる。第10図は、直流阻止回路30の出力波形を示
している・こO出力(基準信号)は、ローパスフィルタ
28の出力と共に差動増幅器32のそれぞ五の入力に印
加され、その結果、差動増幅器32の出力信号は被変調
波信号の周波数変動に比例した直流信号となる・差動増
幅器32の出力信号は、ループ応答を決定するループフ
ィルタ24を介し、さらに増幅器26で増幅され九後、
電圧制御発振器20kに制御電圧として印加される0第
11図、第12図はそれぞれ、差動増幅器32、ループ
フィルタ24の出力信号波形を示している。なお、両図
において、aは周波数変動が零、bは+4−0.・は−
ノω。の場合である。
The output signal of the sine wave phase comparison circuit 22 is applied to a low pass filter 28. The output signal waveform of the 4-Δ filter 280 is as shown in Figure 9. In the same figure, (4) is the waveform when there is no frequency fluctuation in the modulated wave signal, and (B) and (C) are the waveforms when there is frequency fluctuation O, respectively. The output of 28 is applied to a DC blocking circuit 300 Å made up of a capacitor, etc., and becomes a reference signal from which fluctuations in the DC component caused by frequency fluctuations of the modulated wave are removed. FIG. 10 shows the output waveform of the DC blocking circuit 30. This output (reference signal) is applied to each of the five inputs of the differential amplifier 32 together with the output of the low-pass filter 28, so that the difference The output signal of the differential amplifier 32 becomes a DC signal proportional to the frequency fluctuation of the modulated wave signal.The output signal of the differential amplifier 32 is passed through the loop filter 24 that determines the loop response, and is further amplified by the amplifier 26. ,
11 and 12 show the output signal waveforms of the differential amplifier 32 and the loop filter 24, respectively, which are applied as a control voltage to the voltage controlled oscillator 20k. In both figures, a has zero frequency fluctuation, b has +4-0.・Ha-
No ω. This is the case.

第13図は本発明の第3の実施例のブロック図である。FIG. 13 is a block diagram of a third embodiment of the present invention.

この実施例と嬉2の1!施例(第11m)との相違点は
、直流阻止回路300代〕に量子化を行う識別回路34
が用いられている点である。
This example and 1 of 2 happiness! The difference from the embodiment (No. 11m) is that the identification circuit 34 that performs quantization is added to the DC blocking circuit 300s.
is used.

即ち、本実施例では、第9図に示す如きロー/臂スフィ
ルタ28の出力波形を識別回路340入力に印加し、被
変調波の周波数変動によって生ずる直流変動成分の含ま
れない@Omレベル、@1′″レベルに固定し九基準信
号をつくシ出す。第14図は、識別回路34の出力信号
波形を表わしている0ローパスフイルタ28の出力と識
別回路34の出力との差動増幅器32のそれぞれの入力
に印加されることによシ、その出力は第15図に示す如
き波形となる。ただし、第15図の(4)は被変調波信
号に周波数変動でない場合、(B)は周波数変動がΔω
、の場合、(C)は−Δω。の場合である。差動増幅@
32からのこのような出力がルーlの応答を決定するル
ープフィルタ24に入力されるとその出力波形は第12
図に示す如くなシ、被変調波信号の周波数変動に比例し
九直流成分を得ることができる◎ルーフ”フィルタ24
の出力が増幅器26において増幅された後、電圧制御発
振器20bK制御電圧として印加されること杜、前の2
つの実施例の場合と全く同様である。
That is, in this embodiment, the output waveform of the low/arm filter 28 as shown in FIG. A reference signal is output by fixing it at @1'' level. FIG. By applying it to each input of Frequency fluctuation is Δω
, then (C) is −Δω. This is the case. Differential amplification @
When such output from 32 is input to a loop filter 24 which determines the response of rule l, its output waveform is
As shown in the figure, nine DC components can be obtained in proportion to the frequency fluctuation of the modulated wave signal. ◎Roof filter 24
After the output is amplified in the amplifier 26, it is applied as a control voltage to the voltage controlled oscillator 20b.
This is exactly the same as in the other embodiments.

以上詳細に説明し丸ように木兄W14によれば、遅延回
路にベースバンド信号の1ピ、ト以下osig量を有す
る遥延被変調波信号七散〕出すりvfが設けられてお)
、との遥爾被変調波償奇と被変調波信号との正弦波位相
比較回路った結果から被変調波の周波数変動によりて生
ずる直流変動成分Oみと取シ出し、これを遅延回路に戻
して遅延量を可変制御しているため、被変調波信号の周
波数変動が生じても遅延回路の位相量がほぼ一定に保持
される。従って、従来の如き復調アイパターンの劣化は
生じない〇 その結果、耐フエージング特性のもともと嵐い遅嶌検t
n路に1さらに周波数変動に対する安定性を与えること
ができ、本発明によれば、デジタル移動通信Kl!求さ
れる各種の条件を全て満足させることができる。
As described in detail above, according to Kien W14, the delay circuit is provided with a far-reaching modulated wave signal (VF) which outputs a far-reaching modulated wave signal having an osig amount of less than 1 pin of the baseband signal.
, and a sine wave phase comparison circuit between the modulated wave signal and the modulated wave signal. From the results, we extract the DC fluctuation component O caused by the frequency fluctuation of the modulated wave, and apply this to the delay circuit. Since the delay amount is variably controlled in return, the phase amount of the delay circuit is held substantially constant even if the frequency of the modulated wave signal varies. Therefore, the deterioration of the demodulated eye pattern as in the conventional case does not occur.
According to the present invention, digital mobile communications Kl! can be provided with stability against frequency fluctuations. It is possible to satisfy all the various required conditions.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の遥凰検波回路のプロ、り図、第2図は本
発明の第1の実施例のプロ、り図、jI3図及び第4開
拡復調アイパターンの説明図、第5図は被変調波信号の
周波数変動に対する増幅器の出力電圧特性図、第6図は
電圧制御発振器の制御電圧に対する発振周波数偏位特性
図、第7図は被変調波信号の周波数変動に対する遅延回
路の位相偏位特性図、第8図は本発明の菖2の実施例の
ブ四ツク図、第9図はローノ臂スフ(ルタO出力信号波
形図、第10図は直流阻止回路の出力信号波形図、第1
1図は差動増幅器の出力信号波形図、第12図はループ
フィルタの出力信号波形図、第13図は本発明の第3の
実施例のプ四ツク図、第14図は識別回路の出力信号波
形図、第15図は差動増幅器の出力信号波形図である。 10.18−・・端子、14−・・正弦波もしくは余弦
波位相比較回路、IL28−W−ノスフイルタ、20−
・遅延回路、20a・・・シフトレジスタ、20b−1
圧制御発振器、22・・・正弦波位相比較回路、24−
・ループフィルタ、26・・・増@器、30・−直流阻
止回路、32・・・差動増幅器、34−識別回路。 特許出願人 富士通株式会社 特許出原代環人 弁理士青水 網 弁理士 画 館 和 之 弁理士 内 1)申 男 弁理士 山 口 昭 之 第3図 第4図 第5図 第6図 制御電圧(V) 第7図 被変調波信号の周波数変動(にHz) )9図 第10図 第11図 第12図 第14図 第15図
FIG. 1 is a professional diagram of a conventional far-over detection circuit; FIG. 2 is a professional diagram of the first embodiment of the present invention; The figure shows the output voltage characteristics of the amplifier with respect to the frequency fluctuations of the modulated wave signal, Figure 6 shows the oscillation frequency deviation characteristics with respect to the control voltage of the voltage controlled oscillator, and Figure 7 shows the characteristics of the delay circuit with respect to the frequency fluctuations of the modulated wave signal. A phase deviation characteristic diagram, FIG. 8 is a block diagram of an embodiment of the iris 2 of the present invention, FIG. 9 is a waveform diagram of the output signal of the rotor O output signal, and FIG. 10 is a waveform of the output signal of the DC blocking circuit. Figure, 1st
Figure 1 is an output signal waveform diagram of the differential amplifier, Figure 12 is an output signal waveform diagram of the loop filter, Figure 13 is a block diagram of the third embodiment of the present invention, and Figure 14 is the output of the identification circuit. Signal Waveform Diagram FIG. 15 is an output signal waveform diagram of the differential amplifier. 10.18-... terminal, 14-... sine wave or cosine wave phase comparison circuit, IL28-W-nos filter, 20-
・Delay circuit, 20a...shift register, 20b-1
Pressure controlled oscillator, 22...Sine wave phase comparison circuit, 24-
- Loop filter, 26... Multiplier, 30 - DC blocking circuit, 32 - Differential amplifier, 34 - Discrimination circuit. Patent Applicant: Fujitsu Limited Patent Originator: Tamaki, Patent Attorney, Aomi, Patent Attorney, Kazuyuki Kazukan, Patent Attorney: 1) Akira Shin, Patent Attorney, Akira Yamaguchi, Figure 3, Figure 4, Figure 5, Figure 6, Control Voltage ( V) Figure 7 Frequency fluctuation of modulated wave signal (in Hz) Figure 9 Figure 10 Figure 11 Figure 12 Figure 14 Figure 15

Claims (1)

【特許請求の範囲】 1、被変調波信号を遅延させる遅延回路、誼遅延回路に
よって遅延させた第1の遅延被変調波信号と前記被変調
波信号とを位相比較する位相比較回路を備え九遅蔦検緻
回路において、前記遅延回路からペースパンP信号01
ビ、ト以下の遥嬌量を与えた第2の遅延被変調波信号を
取〕出し、該第2の遅延被変調rILl1号と前記被変
調波信号との位相比較を行う正弦波位相比較回路及び該
正弦波位相比較回路からの出力a*を平滑してループ応
答を定めるループフィルタを含む閉ループ回路をさらに
設け、該ルーfIl路の出力を前記遥蔦閤路に#I遺し
て該遍蔦回路の遍蔦量を制御することを特徴とする遅延
検波回路。 2、前記ループ回路が前記正弦波位相比較回路の出力の
高調波成分を除くロー/lスフィルタ、諌ローI4スフ
ィルタの出力信号の直流成分を除去する直流阻止回路、
前記−一ノ帯スフィルタの出力信号と前記直流阻止回路
の出力信号との差動増幅を行う差動増幅回路を備えてお
り、骸差動増lIwA路の出力信号を前記ループフィル
タに印加するようにし九特許請求の範囲第1項記載0遅
嶌検波回路・3、前記ルー7回路が、前記正弦波位相比
較回路の出力の高調波成分を除去する四−パスフィル!
、#四−ノスフイルIの出力信号を量子化する丸めの識
別回路、前記ローノ量スフィルタの出力信号と前記識別
回路の出力を差動増幅する差動増幅回路を備えており、
皺差動増幅回路0出力信号を前記ループフィルタに印加
するようにした特許請求の範囲第1項記載の遅延検波回
路。
[Claims] 1. A delay circuit that delays a modulated wave signal, and a phase comparison circuit that compares the phase of the first delayed modulated wave signal delayed by the delay circuit and the modulated wave signal. In the delay test circuit, the pacepan P signal 01 is output from the delay circuit.
A sine wave phase comparator circuit that extracts a second delayed modulated wave signal that has a magnitude equal to or less than B, G, and compares the phase of the second delayed modulated rILl1 and the modulated wave signal. and a closed loop circuit including a loop filter that smoothes the output a* from the sine wave phase comparator circuit to determine a loop response, and transmits the output of the loop fIl path to the far-flung path #I to the loop path. A delay detection circuit characterized by controlling the amount of deflection of the circuit. 2. A low/l pass filter in which the loop circuit removes harmonic components of the output of the sine wave phase comparison circuit, a DC blocking circuit that removes direct current components of the output signal of the low I4 pass filter;
A differential amplifier circuit is provided for differentially amplifying the output signal of the -1 band filter and the output signal of the DC blocking circuit, and the output signal of the differential amplifier circuit is applied to the loop filter. As described in Claim 1, the late wave detection circuit 3 and the 7 circuit are four-pass filters that remove harmonic components of the output of the sine wave phase comparator circuit!
, a rounding discrimination circuit that quantizes the output signal of the #4-Nosfil I, and a differential amplification circuit that differentially amplifies the output signal of the Ronosfil filter and the output of the discrimination circuit,
2. The delay detection circuit according to claim 1, wherein the wrinkled differential amplifier circuit 0 output signal is applied to the loop filter.
JP56100518A 1981-06-30 1981-06-30 Delay detection circuit Granted JPS583353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56100518A JPS583353A (en) 1981-06-30 1981-06-30 Delay detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56100518A JPS583353A (en) 1981-06-30 1981-06-30 Delay detection circuit

Publications (2)

Publication Number Publication Date
JPS583353A true JPS583353A (en) 1983-01-10
JPH0429265B2 JPH0429265B2 (en) 1992-05-18

Family

ID=14276167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56100518A Granted JPS583353A (en) 1981-06-30 1981-06-30 Delay detection circuit

Country Status (1)

Country Link
JP (1) JPS583353A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423459A (en) * 1977-07-25 1979-02-22 Nippon Telegr & Teleph Corp <Ntt> Delay detector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423459A (en) * 1977-07-25 1979-02-22 Nippon Telegr & Teleph Corp <Ntt> Delay detector

Also Published As

Publication number Publication date
JPH0429265B2 (en) 1992-05-18

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