JPS583633B2 - Timing error detection method for reproduced video signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing error detection method for a reproduced video signal, in which a recording medium on which a video signal is recorded in advance and a pickup device are caused to move relative to each other, and the video signal is reproduced by the pickup device. In doing so, it is an object of the present invention to provide a timing error detection method that can easily and inexpensively obtain an error signal for generating a control signal for controlling the speed of the relative motion.

Generally, when reproducing information from a recording medium on which information such as a video signal is previously recorded, the recording medium and a pickup device are moved relative to each other at a predetermined speed relationship, and the information is picked up and reproduced by the pickup device.

Here, if there is a change in the predetermined velocity relationship of the relative motion between the recording medium and the pickup device, the information will not be reproduced correctly.In order to prevent this, the above-mentioned It is necessary to variably control the speed of relative motion.

Therefore, the present applicant previously proposed a timing error detection method for reproduced video signals as shown in FIG. 1 in Japanese Patent Application No. 49-132568.

That is, in FIG. 1, a horizontal synchronizing signal a as shown in FIG. 2A which is repeated at the horizontal line scanning rate is obtained from the video signal, and this signal is passed from the input terminal 1 to the differentiating circuit 2 and the inverter 3 to produce the signal shown in FIG. 2B. A reset pulse b of the counting circuit 4 as shown is obtained.

Next, an oscillation circuit 5 that outputs a single continuous signal of a predetermined frequency
The counting circuit 4 starts counting the output of the oscillation circuit 5 from the time when the reset pulse b changes from a high level to a low level, and the output of the oscillation circuit 5 is started for a period shorter than a period corresponding to a period of a predetermined horizontal synchronizing signal. By counting a constant number N1, a pulse C shown in FIG. 2C is obtained from the output of the counting circuit 4 through a NAND circuit 6, and a pulse d shown in FIG.

The pulse widths of these pulses C and d change in accordance with fluctuations in the frequency of the horizontal synchronizing signal that repeats at the horizontal line scanning rate.

Immediately after the counting circuit 4 counts a fixed number N1, the counting circuit 8 uses the pulse C as a reset pulse to count the output of the oscillation circuit 5 by a fixed number.

By applying the output of the counting circuit 8 to the reset terminal of the flip-flop 10 through the inverter 9 and applying the above-mentioned pulse C to the set terminal of the flip-flop 10, the pulse width of the flip-flop 10 is always constant as shown in FIG. 2E. The output pulse e is obtained as follows.

Then, the pulse d is applied to one input terminal of the differential amplifier 14 through the integrating circuit 11, and the pulse e is applied to one input terminal of the differential amplifier 14.
is added to the other input terminal of the differential amplifier 14 through the integrating circuit 12.

As a result, the time from immediately after the counting circuit 4 counts a fixed number N1 until it starts counting again by the reset pulse b is compared with the fixed time during which the counting circuit 8 counts a fixed number, and the error is An error signal of a corresponding level is output from the output terminal 15.

As a result, the proposed method can easily convert the error signal used to reproduce the reproduced video signal with high quality into an IC (integrated circuit) and is extremely inexpensive, without requiring special parts such as a 1H delay line. It has the following features:

However, in the proposed method, an OR differential circuit 2 is used as a method for obtaining the reset pulse b, as shown in FIG.
If an IC were used, there would be the following problems.

In other words, there is a threshold potential VT at the reset input terminal of TTLIC, and when the reset input terminal potential is above VT (reset pulse b is at high level), counting is stopped, and when it is below VT (reset pulse b is at low level), counting is stopped. Perform counting.

When a differential pulse as shown by the solid line in FIG. 2F is directly applied as a reset pulse to the counting circuit 4 having such characteristics, the reset pulse b is effectively
The waveform becomes as shown in , and counting is stopped for a high level period t1, and then counting is started.

Furthermore, when the differential pulse indicated by the broken line in F of the same figure is applied to the counting circuit 4 as the reset pulse b, the reset pulse b effectively takes the waveform shown in H of the same figure, and the counting is stopped for the high level period t2. and then start counting.

When the inverter 3 is used after the differentiating circuit 2 as shown in FIG. 1, the time constant of the differentiating circuit 20 changes and the pulse width of the differentiating pulse changes. The output pulse width is shown in Figure 2G.
, H change as shown by t1 and t2, respectively, and thereby the counting time of the counting circuit 4 also changes.

If a very common capacitor and resistor are used in the differentiating circuit 2, the time constant of the differentiating circuit 20 changes due to temperature changes or changes over time, and the differentiated pulse shown by the solid line in FIG. 2F becomes the broken line. It is quite possible that the pulse changes to a differential pulse as shown.

In the above proposed method, a fixed number N1 is counted from the time when reset pulse b changes from high level to low level, and pulse C
Therefore, when the reset pulse b is the pulse shown in FIG.
By counting, a waveform as shown in (■) in the same figure is obtained.

Further, when the reset pulse b is the pulse shown in FIG. 2H, the pulse C has a waveform as shown in FIG. 2J by counting a constant number N1 after the lapse of time L2.

That is, as is clear from Figures I and J, the above proposed method reduces the time from immediately after the counting circuit 4 counts a certain number to when it starts counting again with the next reset pulse b due to a change in the time constant of the differentiating circuit. changes from t3 to t4, which causes a drift in the speed error signal and deteriorates the quality of the reproduced screen.

The present invention solves the above problems, and one embodiment thereof will be described with reference to FIGS. 3 and 4 A to 4.

FIG. 3 is a circuit diagram of one embodiment of the method for detecting timing error in a reproduced video signal according to the present invention, and FIGS. 4A to 4 are signal waveform diagrams for explaining the operation of FIG. 3, respectively.

In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals.

In FIG. 3, a timing alert signal (horizontal synchronization signal) that is input from input terminal 1 and repeated at a horizontal scanning rate is converted into a pulse k with a period t4 as shown in FIG. 4A by an inverter 16, and then counted as a reset Hals. For example, 3.
Start counting continuous signals of a single frequency of 58 MHz.

After this counting circuit 17 is reset by the reset pulse k, it changes from low level to high level when it counts 8 pulses of 3.58 MHz, and changes from high level to low level when it counts 8 more pulses,
Thereafter, the same process is repeated for pulse 1 shown in FIG. 4B,
It is output from the output terminal (230th output terminal) D.

This pulse l is supplied to a differentiating circuit 20 consisting of a capacitor C2 and a resistor R2, where it is made into a differentiated pulse n as shown in FIG. 4D, and then applied as a reset pulse to the reset terminal R of the R-S flip-flop 21. .

A differential pulse m, as shown in FIG. 4C, obtained by differentiating the pulse k, is sent to the set terminal S of the flip-flop 210 from a differentiating circuit 19, which is composed of a capacitor C1 and a resistor R1, and has the same time constant as the differentiating circuit 20. applied.

Here, if the R-S flip-flop 21 is set and reset at the falling edge of the input waveform, even if the time constants of the differentiating circuits 19 and 20 change,
There is no change during the time that the Q output is at a high level (the time when the calculation power is at a low level), and the pulse width of the Q output is equal to one period of pulse 1, as shown by 0 in Figure 4 E. (in this case, 16 3.58 MHz pulses) is applied to the reset terminal of the counting circuit 18.

When this reset pulse 0 is received, the counting circuit 18 starts to receive the output signal (3.58
MHz pulse), the pulse p shown in FIG. A pulse q shown in Figure G appears.

Pulses p and q are applied to NAND circuits 22, respectively.

As a result, as shown in FIG. 4H, from the NAND circuit 22,
The counting circuit 18 divides the 3.58 MHz pulse into 208 (=16
+26+27) Pulse r is output during counting period t5 (constant) at high level and at low level during period t6 until the rising edge of the reset pulse 0 that comes in next after the end of counting, and the pulse r is outputted through the integrating circuit 12. The signal is applied to one input terminal of the dynamic amplifier 14.

Here, the constant pulse width t5 of the pulse r and the constant pulse width (high level period) t of the pulse 0 are each a time approximately corresponding to the period of one horizontal synchronizing signal (for example, NT
If an SC color video signal is recorded, 63.5
The pulse width is selected to correspond to an arbitrary time period smaller than (μsec).

Furthermore, the accuracy of the pulse widths of the pulses 0 and r depends on the frequency stability of the oscillation circuit 50, but this can be made extremely high since the crystal oscillator used in the color signal circuit in the reproduction device can be used. I can do it.

On the other hand, the other input terminal of the differential amplifier 14 is connected to the R
A pulse shown as S in FIG. 4 (inverse phase to pulse 0) taken out from the Q output terminal of the -S flip-flop 21 is applied through the integrating circuit 11 having the same time constant as the integrating circuit 12.

Here, the variable resistor 13 in the integrating circuit 11 is used for level adjustment in order to provide an optimum input potential to the control circuit of the next stage of the differential amplifier 140.

Therefore, the signal obtained from the differential amplifier 14 is such that the input horizontal synchronizing signal is
34) seconds, the voltage is at the predetermined level V because both the low level period t6 of the pulse r and the high level period of the pulse S are predetermined values.

At this time, the speed of relative movement between the recording medium and the pickup device is kept constant.

Now, if for some reason the relative speed between the recording medium and the pickup device becomes faster, the frequency of the horizontal synchronizing signal becomes higher, and the period t4 becomes a smaller value t'4.

Here, the period 15 (constant) in which the output pulse r of the NAND circuit 22 is at a high level and the period t6 in which it is at a low level have the following relationship: t6=t4-t5.

Therefore, since t4 became t'4 (<t4),
t6 becomes a value t'6 smaller than t6, and the duty cycle of pulse r changes.

Therefore, when the relative speed becomes faster, the output voltage of the integrating circuit 12 becomes higher.

On the other hand, since the period of the low level of the pulse S is constant, as the relative speed increases, the duty cycle changes and the period of the high level becomes shorter, and the output voltage of the integrating circuit 11 changes at a predetermined relative speed. It will be lower than when.

Therefore, the output signal of the differential amplifier 14 is taken out as a voltage having, for example, an average value higher than the predetermined level V.

At this time, the speed of the relative movement between the recording medium and the pickup device is controlled to be small so as to keep the frequency of the input horizontal synchronizing signal at a predetermined value.

Furthermore, when the relative speed becomes slower, the error signal is outputted from the differential amplifier 14 as an error signal having a voltage lower than the predetermined level V, for example, by an operation opposite to that described above.

Using a control signal formed from this error signal, the speed of relative movement between the recording medium and the pickup device is greatly controlled so as to bring the frequency of the horizontal synchronizing signal to a predetermined value.

Although the above embodiment has been described in which the output signal of the differential amplifier 14 is obtained as an error signal, the present invention is not limited to this, and the output signal of either the integrating circuit 11 or 12 may be obtained as an error signal. You may also use it.

Furthermore, when the differential amplifier 14 is used, assuming that the outputs of the NAND circuit 22 and the R-S flip-flop 21 have low impedance and the peak values of the respective outputs are equal, the outputs of the integrator circuits 11 and 12 are It is not affected by changes in time constant, fluctuations in power supply voltage, etc., and the detection sensitivity is increased compared to when the output of the integrating circuit 11 or 12 is used alone.

As described above, the timing error detection method of the reproduced video signal according to the present invention detects the timing error at a horizontal line scanning rate from the video signal picked up and reproduced by the pickup device that moves at a predetermined speed relative to the recording medium on which the video signal is previously recorded. A signal processing means for extracting a repeating horizontal synchronization signal, an oscillation circuit for outputting a single continuous signal of a predetermined frequency, and a count that starts counting by the output of the signal processing means for a period shorter than the period of the horizontal synchronization signal. A first counting circuit that counts a fixed number of output signals of the oscillation circuit, and a duty cycle according to the frequency fluctuation of the horizontal synchronizing signal that repeats at the horizontal line scanning rate by the output of this counting circuit and the output of the signal processing means. a first pulse forming means that outputs a first pulse in which the pulse width changes greatly (or small) and has a constant pulse width; a second counting circuit that counts a fixed number of output signals of the oscillation circuit for a shorter time than a second pulse forming means that outputs a second pulse having a constant pulse width and a constant pulse width; Since it is a means for outputting an error signal of a level corresponding to a cycle, the first pulse forming means always obtains a first pulse of a predetermined pulse width regardless of changes in characteristics of circuit elements due to temperature changes and changes over time. Therefore, the drift of the error signal can be prevented, and since the pulse widths of the first and second pulses are determined only by the frequency stability of the oscillation circuit, the timing error can be detected extremely accurately and stably. By providing a differential amplifier that compares the levels of the output pulses of the first pulse forming means and the output pulses of the second pulse forming means and outputs an error signal, the difference between the first and second pulses due to fluctuations in the power supply voltage is provided. Even if there is a change in the peak value of the pulse, it will not affect the error signal, and even if the capacitance of the capacitor used for level comparison in the differential amplifier changes due to temperature changes, changes over time, etc., the error will not be affected. Since the first and second pulses whose duty cycles change in opposite directions are applied to the input of the differential amplifier, the influence on the signal can be almost negligibly small, and the first or second pulse forming means can be applied to the input of the differential amplifier. It has a number of features, including the ability to increase detection sensitivity compared to the case where the output pulse is used alone to obtain an error signal, and the circuit configuration can be configured easily and inexpensively without the need for special parts. It is something.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of a timing error detection method for reproduced video signals proposed earlier by the present applicant, FIGS. 2A to 2J are signal waveform diagrams for explaining the operation of FIG. 1, and FIG. 4 is a circuit system diagram of one embodiment of the timing error detection method for a reproduced video signal according to the present invention, and FIGS. 4A to 4I are signal waveform diagrams for explaining the operation of FIG. 3, respectively. 4, 8, 17, 18... Counting circuit, 5...
...Oscillation circuit, 10,21...R-S flip-flop, 14...Differential amplifier.

Claims (1)

[Scope of Claims] 1. A signal processing means for extracting a reproduced horizontal synchronization signal that is repeated at a horizontal line scanning rate from a video signal that is picked up and reproduced by a pickup device that moves at a predetermined speed relative to a recording medium on which a video signal is previously recorded. , an oscillation circuit that outputs a single continuous signal with a constant frequency higher than the horizontal scanning frequency, and an output reproduction horizontal synchronization signal of the signal processing means, which starts counting the output of the oscillation circuit to match the period of the regular horizontal synchronization signal. a first counting circuit for counting a fixed number of output signals of the oscillation circuit for a period shorter than the two-dimensional time; supplying a constant first pulse whose duty cycle changes from large to small according to frequency fluctuations of the regenerated horizontal synchronizing signal and whose pulse width is equal to one cycle of the output pulse of the first counting circuit; A first pulse forming means to output, and counting is started by the output pulse of the first pulse forming means, and the output of the oscillation circuit is counted a certain number for a time shorter than a period corresponding to a regular horizontal synchronizing signal. a second counting circuit that outputs a second pulse whose duty cycle changes from small to large according to the frequency fluctuation of the reproduced horizontal synchronizing signal and whose pulse width is constant from the output of the second counting circuit; a second pulse forming means that passes through the first and second pulse forming means;
1. A timing error detection method for a reproduced video signal, comprising means for outputting an error signal of a level corresponding to the duty cycle from the output pulse of one of the pulse forming means. 2. A signal processing means for extracting a reproduced horizontal synchronizing signal that repeats at a horizontal scanning rate from a video signal that is picked up and reproduced by a pickup device that moves at a predetermined speed relative to a recording medium on which a video signal has been recorded in advance, and An oscillation circuit that outputs a single continuous signal with a high constant frequency, and an output reproducing horizontal synchronization signal of the signal processing means, starts counting the output of the oscillation circuit, and starts counting the output of the oscillation circuit in a period shorter than the period of the regular horizontal synchronization signal. a first counting circuit for counting a fixed number of output signals of the oscillation circuit for a certain period of time; and supplying the output of the first counting circuit and the output reproduction horizontal synchronization signal of the signal processing means to a flip-flop to perform the reproduction horizontal synchronization. a first pulse forming device that outputs a constant first pulse whose duty cycle changes to be large or small according to the frequency fluctuation of the signal and whose pulse width is equal to one period of the output pulse of the first counting circuit; and a second counting circuit that starts counting with the output pulse of the first pulse forming means and counts the output of the oscillation circuit a fixed number for a period shorter than the period of the regular horizontal synchronizing signal. , a second pulse forming means that outputs a second pulse whose duty cycle is changed to small or large according to the frequency fluctuation of the reproduced horizontal synchronizing signal and whose pulse width is constant from the output of the second counting circuit; and the first and second
a differential amplifier which is supplied with the output pulses of the pulse forming means, compares the levels of the first and second pulses, and outputs an error signal having a level corresponding to the duty cycle. Video signal timing error detection method.