JPS5837806A - Data synchronization signal detection circuit of PCM recording and playback device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data synchronization signal detection circuit for a PCM recording and playback device that uses a video tape recorder (hereinafter referred to as VTR) or a part thereof to record and play back PCM signals compliant with standard television signals. Regarding this, a 4-bit data synchronization signal represented by "1010" is detected from among the data signals included in the PCM signal.

Normally, PCM recording and playback equipment uses VTR or V
A part of the TR is used to record and play back PCM signals that conform to standard television signals.

In such a PCM recording and reproducing apparatus, there is a problem in that dropouts occur due to scratches or dust on the VTR tape, which is a recording medium, and erroneous signals are reproduced. If this erroneous signal occurs in the reproduced data signal, if it is an error within a certain probability, a well-known error correction code is used.

No. p, it can be completely corrected, so there is no practical problem. However, if an erroneous signal occurs in the sync signal part, there is no way to fix it, so PCM
There is a problem in that each circuit in the signal processing system becomes out of synchronization and noise is generated.

In other words, in this type of PCM recording and playback device, data is rearranged in time by an operation called interleave during recording, and data is returned to its original signal arrangement by an operation called deinterleave during playback. However, when the horizontal synchronization signal is disrupted, the time relationship between the horizontal synchronization signal and the PCM data signal is disrupted, and the two
There is a problem in that a data signal that is supposed to exist for 45 horizontal signal periods is not correctly reproduced during that period, and as a result, large noise is generated during de-interleaving and data error correction.

The present invention is a PCM used to solve such problems.
The present invention provides a data synchronization signal detection circuit for a recording/playback device.

An embodiment of the present invention will be described below with reference to the drawings.

First, the PCM signal format shown in the consumer PCM encoder/decoder file determined by the Japan Electronics Industry Association will be explained with reference to FIGS. 1 and 2.

Figure 1a shows the signal arrangement for the odd field, and Figure 1a shows the signal arrangement for the even field, each with 73H (H is 1).
It includes a vertical synchronizing signal (horizontal signal period), equalization pulse signals of 3H each before and after, a 1H control block, and a 246H data block, and in the case of an odd field in Figure 1a, PCM data After 7.5H has passed since the end of the signal, or in the case of an even field in Figure 1, the PC
Each equalization pulse signal appears after 7H has elapsed from the end of the M data signal. Figures 1c and d are Figure 1a, respectively.
This figure shows the details of the vertical synchronization signal and equalization pulse signal in FIG.

On the other hand, Figure 2a shows the signal arrangement for each pit in the horizontal signal section of the PCM signal format, in which a 4-bit white reference signal is followed by a 13-pit horizontal synchronizing signal with 5 bits apart, and then A 4-bit (101o'') data synchronization signal is placed 13 bits apart, a 128-bit PCM data signal is placed from there, and then a 128-bit PCM data signal is placed.
The next white reference signal is placed after a bit. Therefore, as shown in FIG. 2a, one horizontal signal section consists of 168 pits.

Figures 2 and 4 show a data signal obtained by slicing the PCM signal shown in Fig. 2a at level 1, and a synchronization signal obtained by slicing it at level 1, respectively. Note that the data signal includes a synchronization signal and a PCM data signal.

FIG. 3 shows the overall configuration of an embodiment of the present invention, and FIG.
FIG. 18 shows the specific configuration of each block in FIG. 3. Of these, FIG. 8 shows a data synchronization signal detection circuit according to the present invention. The configuration of this embodiment will be explained below with reference to FIGS. 3 to 18.

In Figure 3, A is an input terminal to which the data signal shown in Figure 2 is applied, B is an input terminal to which the synchronization signal shown in Figure 2 C is applied, and C is an input terminal to which the master clock signal is applied. be. A clock signal generation circuit 17 generates a clock signal H for punching the PCM signal based on the data signal applied to the input terminal A and the master clock signal applied to the input terminal C. 18 is a data signal generation circuit that punches out a data signal applied to input terminal A in response to clock signal H and generates a digitized data signal; 19 punches out a synchronization signal applied to input terminal B in response to clock signal H; Digitized synchronization signal E
This is a synchronous signal generation circuit that generates.

The data signal delay circuit 1 receives a data signal and a clock signal H as input, and delays the data signal by a predetermined bit.The output signal is sent via an output terminal F to a subsequent digital signal processing section (not shown). ). As shown in FIG. 4, this data signal delay circuit 1 consists of 8-bit NOT registers 1-1.1-2.1-3.
1-4, each knot register 1-1
By applying the clock signal H to the clock terminals 1-4, the data signal is delayed by a predetermined bit.

The synchronization signal delay circuit 2 receives the synchronization signal E and the chronograph signal H.
is input and delays the synchronizing signal E by a predetermined bit, and its output signal (2) is supplied to a horizontal synchronizing signal generating circuit 8, which will be described later. The synchronization signal delay circuit 3, based on the output signal I and the clock signal H of the horizontal synchronization signal generation circuit 8,
This is to delay the output signal (2) of the horizontal synchronizing signal generating circuit 8 by a predetermined bit.

As shown in FIG. 6, these synchronizing signal delay circuits 2, 3 are composed of 8-bit shift registers 2-1.2-2.2-3.
and D-type 7 resopflotz 2°2-4°3-1 connected in cascade, and each shift register 2-1 to 2-3,
Clock terminal C of D type flip 70 tube 2-4.3-1
A clock signal H is supplied to the shift register 2-1, and an AB input/output signal I (I, I, I3) and an output signal K of the shift register 2-1 are output. In this example, two synchronizing signal delay circuits 29.3 are used, but they collectively constitute one synchronizing signal delaying means.

In short, data signal delay circuit 1, periodic signal delay circuit 2,
It is sufficient to make the number of delay stages of 3 equal to each other and to delay the data signal and the synchronization signal by the time necessary for error correction of the horizontal synchronization signal, which will be described later.

The muting control circuit 4 includes a horizontal synchronization signal generation circuit 8
A horizontal synchronizing signal K obtained through the synchronizing signal delay circuit 3 is inputted to the output signal I of the horizontal synchronizing signal generating circuit 12 (which also functions as a meeting control signal generating circuit, as will be described later). The input signal K is controlled intermittently based on the muting control circuit outputted from the output terminal G, and the output signal is led to the digital signal processing section at the subsequent stage via the output terminal G, and is then output from the output terminal F described above. used for data signal reproduction processing. This meeting circuit 4 interrupts this erroneous horizontal synchronization signal and outputs it to the digital signal processing section when the position of the horizontal synchronization signal has significantly changed from its normal position relative to the data signal. Otherwise, the correct or correctly corrected horizontal synchronizing signal is controlled to be transmitted to the digital signal processing section.

As shown in FIG. 6, this meeting circuit 4 receives an output signal L (Ll) from a horizontal synchronizing signal generating circuit 8.

L2. A NOR gate 4-1 which receives the signal L3) as an input, an inverter 4-2 which inverts its output, and an AND gate 4 which receives the synchronization signal output from the synchronization signal delay circuit 3 and the output signal of the inverter 4-2 as input. -3,
Output signals G, J,
M is output.

The data signal opening/closing circuit 5 controls opening/closing of the data signal based on the output signal P of the data zero detection circuit 14, the output signal 0 of the horizontal synchronization signal width detection circuit 16, and the output signal N of the continuous meeting counter circuit 16. It is. Specifically, as shown in FIG. 7, it is composed of a NOR gate 5-1 and an OR gate 6-2, and if any one of the output signals P, O, and H is not satisfied, the NOR gate 6 -1 is not opened and the data signal is not passed through. In other words, as is clear from Figure 2 a, b, and c, the correct P
If the CM signal format is correct, the horizontal synchronization signal width (i
-j interval) is 13 bits, and the data in the interval from its start i to the data synchronization signal is all zero, so this is detected by the horizontal synchronization signal width detection circuit 16 and data zero detection circuit 14, and these are If the format is correct, the data signal opening/closing circuit is opened to allow the data signal to pass, and if the format is incorrect, it is shut off to gate control whether or not to detect the data synchronization signal in the subsequent stage. . The continuous muting counter circuit 16 controls the data signal opening/closing circuit 5 to open continuously based on the signal M from the muting circuit 4 so that the data signal opening/closing circuit 6 does not interrupt the data signal. belongs to.

The above data zero detection circuit 14, horizontal synchronization signal width detection circuit 1
5. The continuous muting counter circuit 16 calculates the input P based on the input data signal and synchronization signal.
The circuits 14, 15 and 16 are shown in FIG.
Figure 17.

It can be constructed with a circuit as shown in FIG.

(Left below) In Figure 16, 14-1 is a monostable multi-novel ibrator, R14-11014-1 is a resistor and capacitor that determines its constant number, 14-2.14-3 is an OR gate and a NOR gate, 14-4 is a D-type flip-flop, 1
4-5 and 14-6 are NOs forming a flip-flop.
This is the R gate.

In Figure 17, 15-1 is a monostable multi-via.
L-' -ta, R)es * ・015-1 is a resistor and capacitor that determines its time constant, 15-2 is an inverter, 16-3 and 16-4 are an OR gate and a NOR gate, 15-6 is a D type flip-flop, 15-6.1
5-7 is a NOR gate constituting a flip-flop.

In FIG. 18, 16-1 is an AND gate, 16-2
．． 16-3 is a monostable multivibrator, R16-1.
C16-1, R16-2, and C16-2 are resistors and capacitors that determine the time constant.

The data synchronization signal detection circuit 6 (Fig. 100) according to the present invention is as follows:
It detects the data synchronization signal ("1010") in the output signal Q of the data signal opening/closing (b) path 5, and specifically, as shown in FIG.
1 to 6-7 and a NOR gate 6-4.

That is, the data signal Q is input from the data signal switching circuit 6 to the input of the first stage D-type flip-flop 6-1 (however, as also related to FIG.
Since the phase of is inverted by the NOR gate 6-1 in FIG. 7, the data synchronization signal appearing at Q in FIG.
1o1''), and the clock signal H is input to the clock terminal OK. On the other hand, the above-mentioned type flip-flop 6-2 is input to the second stage D-type flip-flop 6-2.
The output Q of 1 is input, and the clock H is input to the clock terminal CK. Then, the input and output Q of the flip-flop 6-1 and the output Q of the flip-flop 6-2 are NO.
It is input to the R gate 6-4. In this way, the two-stage 7 lip-flop 6-1.
6-2 is inverted and only when the rabbit data of "olo" is continuously input to the input of the flip-flop e-71, all the inputs of the NOR gate 6-4 become "°o#" and "3". The output becomes "1". (When the input is other than "olo", one of the inputs of the NOR gate 6-4 becomes "1".
1'', so the output of the NOR gate 6-4 is "0".) In this way, the NOR gate 6-4
When the output of -4 becomes "1", the input of the third stage D-type flip-flop 6-3 becomes "1 #", and @010
This flip-flop 6-3 is inverted by the clock signal H at the next timing following ", and its output Q becomes 11
#become. This means that 4 pins of "0101" have been detected, and this is supplied as the data synchronization signal detection output R to the bit determination circuit 7 at the subsequent stage.

Note that in this embodiment, the regular data synchronization signal “1010
” is detected, the data synchronization signal detection output R is set to “1”.
', otherwise it is set to "0", but conversely, when the regular data synchronization signal "1010" is detected, the detection output R is set to "0", and otherwise it is set to "1". Needless to say, it is okay to do so.

The bit determination image Fi87 for determining the relative relationship between the horizontal synchronization signal and the data synchronization signal is based on the clock signal H, the data synchronization signal R output from the data synchronization signal detection circuit 6, and the horizontal synchronization output from the horizontal synchronization signal detection circuit 13. It uses the signal T as input and determines whether the number of bits between the horizontal synchronization signal and the data synchronization signal (ixm or j'-m) is correct, and if so, to what extent. Specifically, it can be constructed by a circuit as shown in FIG.

In Figure 9, 7-1 are OR gates, 7-2゜7-3
is a NOR gate that constitutes a flip-flop), 7-4 is a monostable multivibrator, R7-1, c7=1 is a resistor and capacitor that determines its time constant, 7-5 is a NOR gate, 7-6 to 7-10 are It is a D type flip-flop. These D-type flip-flops 6 to 7-10 constitute a counter, and count results are output from υ1 to U8, which are transmitted to the horizontal synchronizing signal generating circuit 8.

The horizontal synchronizing signal generation circuit 8 generates a correct horizontal synchronizing signal j when the horizontal synchronizing signal j is correct, and generates a correctly corrected horizontal synchronizing signal j when the horizontal synchronizing signal j is incorrect, based on the judgment result of the judging circuit 7. This is a generation circuit, and if the correctable range is set to +1 bit, it can be constructed as a circuit as shown in FIG. Incidentally, as described above, in this embodiment, the horizontal synchronizing signal generating circuit 8 also has the function of generating the muting control signal L (Ll, R2, R3).

In Fig. 10, 8→1,8=2.8-3 is correct when the signal U (U1 to U8) from the determination circuit 7 is input and the horizontal synchronization signal is +1 bit off from the correct position. NOR gate that detects when (0 bit deviation) and -1 bit deviation, 8-44~
8-6 is D type flip frog, $-7, 8-8 is NO
R gate and OR gate, 8-9 are monostable multivibrators, R and C are resistors that determine their time constants, and 8-9 are monostable multivibrators.
8→1 and capacitors, 8→1o to 8-13 are tristate gate circuits, and 8 to 14 are inverter circuits.

The control block detection circuit 9 includes a clock signal H, a data signal, and a vertical synchronization signal equalization pulse signal control circuit 1, which will be described later.
The control block shown in FIG. 1 is detected by using the output Y of No. 2 as an input, and specifically, it can be constructed by a circuit as shown in FIG. 11. In FIG. 11, 9-2 to 9-5.
9-9 is a D-type flip-frog, 9-11 is a 4-pit shift register, 9-12 is a monostable multivibrator,
R9-11C9-1 is a resistor and capacitor that determine the time constant, 9-1 is an OR gate, 9-6, 9-7 is an exclusive OR gate, and 9-8 is a NOR gate.

The data block control circuit 10 inputs the output W of the control block detection circuit 9, the clock signal H, and the vertical synchronization signal X from the vertical synchronization signal detection circuit 11, and receives the control signal of the horizontal synchronization signal generation circuit 8 described above. V and control circuit 12
This is a NOR game that outputs a control signal 2, which constitutes a flip-flop, as shown in FIG. 12.10-1
, 10-2, OR gate 10-3, and inverter 1
o-4, p-type flip-flop, and flip-flop 1o-6.

7. Since the horizontal synchronizing signal to be corrected is only that of the data block shown in FIG. 1, the control block detection circuit 9 and data block control circuit 10 perform correction processing of the horizontal synchronizing signal only in the data block. This is provided to prevent malfunctions by not performing correction processing during other periods.

The vertical synchronization signal detection circuit 11 detects the vertical synchronization signal shown in FIG. 1, and can be specifically constructed by a circuit as shown in FIG. 13. In Figure 13, 11=1 is 4
Bit counter, 11-3゜1-1-6 is a D type flip-flop, 11→5 is a monostable multivibrator, R4
, -1, and C11-1 are a resistor and a capacitor that determine the time constant, and detect the length of the vertical synchronizing signal section shown in FIG. 1c and d and output a detection output H.

The vertical synchronization signal equalization pulse signal control circuit 12 detects the vertical synchronization signal and equalization pulse signal shown in FIG.
18, . In FIG. 14, 12-1. ．． 12-2 is a NOR gate constituting a flip-flop, 12-3 is a monostable multivibrator, and R12-11C12-1 is a resistor and a capacitor that determine its time constant.

The horizontal synchronization signal detection circuit 13 detects the water column synchronization signal shown in FIG. 2, and specifically, as shown in FIG. OR game to calculate the sum) 13-4 and inverter 1
3-3, the horizontal synchronization signal detection output T is supplied from the OR gate 13-4 to the determination circuit 7, the data zero detection circuit 14, the horizontal synchronization signal width detection circuit 16, and the horizontal synchronization signal generation circuit 8. Ru.

Next, the operation of the above embodiment will be explained.

The data signal and synchronization signal applied to input terminals A and B are transmitted to data signal delay circuit 1 and synchronization signal delay circuit 2, respectively.
and is delayed for a predetermined time.

On the other hand, the data signal is also supplied to the 19-NOR gate 5-1 of the data signal switching circuit 6. When the PCM signal format detection means 14 to 16 determine that the signal is one type of PCM signal format, all of their outputs N, O, and P become "0", and the OR gate 6-
The output of 2 becomes NO”.

Therefore, the NOR gate 5-1 opens and the data signal is outputted as the output Q. Izuwa of N, O, and P.

When even one of the values becomes 1", the NOR gate 5-1 closes,
Data signals are blocked.

This data signal opening/closing port 1. The output Q of s is supplied to the D-type flip-flop 6-1 of the data synchronization signal detection circuit 6, as shown in FIG.
7" 6-1 to e-3 and the NOR gate 6-4, the data synchronization signal (
1010'') and outputs a data synchronization signal R.

This data synchronization signal R is applied to the O of the determination circuit shown in FIG.
It is supplied to the R gate 7-1, and the horizontal synchronization signal detection circuit 14
The NOR gate R-5 is opened during the period from the rise of the horizontal synchronization signal T outputted by the controller until the data synchronization signal R is input.
The period from the horizontal synchronization signal T to the data synchronization signal R is counted by directing the clock signal H to the output terminal 7-6 and 7-10. The count results are U1-U8
is stored in the U signal. Note that this signal is a signal generated after a certain period from the horizontal synchronization signal T, that is, after a period when the data synchronization signal of 1o1o'' is to be detected, and is a signal for resetting the counters 7-6 to 7-10.

The output signal U of the bit determination circuit 7 is supplied to U1 to U8 of the horizontal synchronization signal generation circuit in FIG.
If the horizontal synchronization signal is deviated by 1 bit from the format, it is detected by NOR gate 8-1. If the horizontal synchronization signal is a normal horizontal synchronization signal, it is detected by NOR gate 8-2.
A case in which the horizontal synchronizing signal is slightly shifted by +1 pixel with respect to the M format is detected by 8-3, and the outputs of these NOR gates 8-1 to 8-3 are converted to the signal S shown in FIG. 9 as a clock signal. Flip-flop 8-4 to 8-
It is stored in 6. Note that the signal S is a signal that changes from "o" to "1" when the data synchronization signal R is applied.

To explain this operation in more detail, for example, if there is a -1 pit shift, the output of the NOR gate 8-1 will be 1", and the output of the NOR gate 8-2, 8-3 will be "0". Therefore, the output ◇ of flip-flop 8-4 becomes "0",
Tri-state gate circuit 8-10 opens and 11 is output to 1. Naturally, in this case, since the output ◇ of the flip-flop 8-6 and the output Q of the flip-flop 8-6 are 1'', the tri-state gate circuits 8-11...8-12
It's closed. Note that the tristate gate circuit 8-
The fact that IQ~8-13 are closed means that these tristate gate outputs are floating jig lines. If there is a -1 bit shift, the input signal of the NOR gate 4-1 is -1 as shown in FIG.
Since the signal L1 is "1", M is "0" and therefore "γ is 1", and the tristate gate circuit 8-13 is closed. By a similar operation, if the difference is 0 bits (correct), I2 is output to I, and if the difference is +1 bit, I3 is output to ■. NOR gate 8-
7. OR gate 8-8 is flip-flop 8-4 to 8-
Generates a signal to be applied to the clear terminal and preset terminal of 6.

The output signal T of the horizontal synchronization signal generation circuit generated in this way is transmitted to the output signal T of the synchronization signal delay circuit 3 shown in FIG.
The signal is applied to the D-type flip-flop 3-1, delayed by the D-type flip-flop 3-1, and output as a signal. This signal is applied to one input terminal of AND gate 4-3 in FIG. - Signal L1 shown in Figure 10 of the force cylinder. L2. L3 is applied to the input terminal of the AND gate 4-1 of the muting circuit 4 shown in FIG. Here, Ll, L2. Any one of L3 is”
1", that is, if the relationship between the data and the synchronization signal is wrong within ±1 bit or is correct, the output M becomes "0". Then, γ is "1", and the AND gate 4-3 When opened, the signal K is output as is as signal G, and the corrected or correct horizontal synchronization signal is output as is as signal G. If Ll, L2, and L3 are all "0", that is, data and The relationship between the synchronization signals is ±2 bits, the signal G is always "Q", and the signal K
mute.

The OR gate 9-1 of the control block detection circuit 9 shown in FIG. is input, and the PCM is entered in the control block.
″′11oo, which is determined by the formant standard.
``The bit pattern is set in the flip-flops 9-2 to 9-5 and the gate paths 9-6 to 9-8 based on the clock signal H.
and a flip-flop 9-9 and a gate circuit 9-9, a counter 9-11 detects the repetition of the "11oo" pattern of the cloud, and inputs the output to a monostable multivibrator 9-12, Obtain an output signal W.

FIG. 12 shows a data block control circuit 1o, which inputs the output signal W of the control block detection circuit 9 described above and the output X of the vertical synchronization signal detection circuit 11 described later, and
A flip-flop composed of OR gates 10-1 and 10-2 is operated. vl.

v2 is the output signal of OR game) 10-3, and when the vertical synchronization signal is input, X becomes "1", vl becomes "1",
2 becomes 70''. This state continues until the signal W is applied, and the horizontal synchronizing signal generating circuit 8 shown in FIG.
It is designed to operate only in the PCM data signal portion of the M signal.

The vertical m-Q detection circuit 11 shown in FIG. The vertical synchronization signal is detected by counting the "0" periods of the vertical synchronization signal shown in FIGS. c and d. 11-1 is a "Q" period counter, monostable multivibrator 11-5, D type flip-flop circuit 1
1-6, once a vertical synchronizing signal is detected, the detection is closed by the output of the gate 11-7.

The vertical synchronization signal and equalization pulse signal control circuit 12 shown in FIG. It generates a time signal Y.

The horizontal synchronization signal detection circuit 13 shown in FIG.
The output signal is applied to the flip-flop 13-2, the horizontal synchronizing signal is counted using the clock signal H, and a horizontal synchronizing signal detection output T is generated. Note that during the data block period, the signal Y becomes "0" and no counting is performed.

The data zero detection circuit 14 shown in FIG. 16 operates the monostable multivibrator j4-1 with the horizontal synchronization signal detection output T, and outputs the output Q from the monostable multivibrator 14-1 up to the m1 bit position shown in FIG. and output the period,
When the data is zero, the output of the OR gate 14-2 is set to "0" by the data signal E and the clock signal H, and the output Q of the D-type flip-flop 14-4 is set to "0".

Thereafter, a data synchronization signal detection signal is applied from the determination circuit 17 shown in FIG. As a result, as mentioned above, if the data is zero from the horizontal synchronization signal detection output T to the judgment circuit output, the output P will be "0", and if there is a part where the data is "1" during that period, , the output Q of the D-type flip-flop 14-4 becomes "1", and the output P becomes "1".

The horizontal synchronization signal width detection circuit 15 shown in FIG. 17 detects the width of the monostable multivibrator bar 1 from the time when the horizontal synchronization signal detection output T is generated by the monostable multivibrator 15-1 until the period shown by j in FIG. The output ◇ is set to "0", and during that period, the synchronizing signal E and the clock signal H are OR gate 16.
-3, NOR gate) 15-4. If the period from T to j is "o", the D-type flip-flop 1
The D input of 6-6 becomes "0", and the output O becomes "O" while the signal is applied.

On the other hand, if the width of the horizontal synchronizing signal during the period from T to j is "1", the D-type flip-flop 1
The D input of 6-5 is 61", and the output O is "1". Here, the width from T to 5 is several bits shorter than the force ζi which is detected as the width of the horizontal synchronizing signal. There is actually no problem with the settings.

The continuous meeting counter circuit 16 shown in FIG. 18 receives the signal M from the mute ink circuit 4 shown in FIG.
After approximately one horizontal period, the output 0 of the monostable multivibrator 16-3 is changed to "0" after being applied as 1". As a result, the output N becomes 0" in the next horizontal period. Therefore, even if the output M from the meeting circuit 4 is "1" for two consecutive periods, the signal N is "1" only for the first horizontal period.
It becomes 1'', but becomes 0 in the next horizontal period.
In the above embodiment, the distance between the horizontal synchronization signal and the data synchronization signal is ±
Correction is performed when the deviation is 1 bit, and muting is applied when the deviation is over ±22 bits. For example, NOR gates 8-1 to 8-3 shown in FIG.
The number of D-type flip-flops 8- is increased accordingly.
If we increased the number of 4 to 8-6, the difference would be +/-22 bits.

Corrections can also be made easily. Since such circuit modifications are obvious to those skilled in the art, detailed explanation will be omitted here.

In addition, in the above embodiment, a PCM signal conforming to a 525-line NTSC standard television signal was described, but a 625-line PAL signal is used.

A PC that complies with the SECAM standard television signal.
It goes without saying that the same method can be applied to the M signal as well.゛As described above, the present invention receives a data signal included in a PCM signal and a clock signal as input, and when a 4-bit data synchronization signal represented by "1010" included in the data signal is input. Since the data synchronization signal is detected using a logic circuit that outputs 1'' (or '0') only when the signal is detected and outputs 0'' (or 1'') at all other times, its output Using this, it is possible to accurately perform bit determination between the horizontal synchronization signal and the data synchronization signal, and to accurately detect the PCM data signal following the data synchronization signal.

[Brief explanation of the drawing]

2, 2 and 3C are diagrams showing the a format of the PCM signal, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIGS. FIG. 2 is a block diagram showing a specific configuration of each part in the figure. 1... Data signal delay circuit, 2.3...
・Synchronization signal delay circuit, 4...Meeting circuit, 6...Data signal opening/closing circuit, 6...
・Data synchronization signal detection circuit, 7...determination circuit,
8. ..., horizontal synchronization signal generation circuit and meeting system signal generation circuit, 9 ... control block detection circuit, 1゜ ... data block control circuit, 1
1... Vertical synchronization signal detection circuit, 12...
・Vertical synchronization signal, equalization pulse signal control circuit, 13...
... Horizontal synchronization signal detection circuit, 14 ... Data zero detection circuit, 15 ... Horizontal synchronization signal width detection circuit, 16 ... Continuous muting counter circuit,
17... Clock regeneration circuit, 18...
Data signal generation circuit, 19°...Synchronization signal generation circuit. Name of agent: Patent attorney Toshio Nakao and one other person Ji
S Figure 4 L , , -J Figure 8 L
J12E Figure 13Figure 14! 2 / Figure 15 Figure 16

Claims (1)

[Claims] A data signal in a PCM signal conforming to a standard television signal and a clock signal are input, and t1'' ( A data synchronization signal detection circuit for a PCM recording/playback device, comprising a logic circuit that outputs 0" (or 0") and 0" (or 1") at other times.