JPS5839018A - Assembling method of hybrid integrated circuit - Google Patents

Assembling method of hybrid integrated circuit

Info

Publication number
JPS5839018A
JPS5839018A JP56138964A JP13896481A JPS5839018A JP S5839018 A JPS5839018 A JP S5839018A JP 56138964 A JP56138964 A JP 56138964A JP 13896481 A JP13896481 A JP 13896481A JP S5839018 A JPS5839018 A JP S5839018A
Authority
JP
Japan
Prior art keywords
resin
integrated circuit
substrate
heat
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56138964A
Other languages
Japanese (ja)
Inventor
Iwao Takiguchi
滝口 岩夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56138964A priority Critical patent/JPS5839018A/en
Publication of JPS5839018A publication Critical patent/JPS5839018A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0058Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable to assemble the titled integrated circuit at low cost without reducing a radiation effect by a method wherein resin coating is performed on the surface only of a thick film resistance substrate. CONSTITUTION:A substrate is indicated by 1 and a semiconductor chip by 2 in the diagram, and a heat-resisting tape 3 is adhered to the back side of the substrate 1. Then, using a fluidization dip resin molding method, fluidization dip resin 5 is coated, and after the coating has been finished, the heat-resisting tape 3 is peeled off while the fluidization dip resin is still soft, and the radiating plate 6 of prescribed measurements is adhered to the substrate 1 as occasion demands after the fluidization dip resin has been cured. As regards the radiating plate 6, its shape and method of adhesion are properly selected, and its assembling process is completed. The package of hybrid integrated circuit to be used for power can now be accomplished without reducing radiation effect by utilizing the coating of the fluidization dip resin.

Description

【発明の詳細な説明】 この発明は、厚膜抵抗基板の樹脂コーティングを容易に
した混成集積回路の組立方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for assembling a hybrid integrated circuit that facilitates resin coating of a thick film resistive substrate.

従来、パワー用の混成集積回路は、厚膜抵抗基板(以下
、単に基板と記す)の裏面に放熱板を貼り付け、プラス
チックケース等でパッケージすることが主流であった。
Conventionally, power hybrid integrated circuits have been mainly packaged with a heat sink attached to the back side of a thick film resistor substrate (hereinafter simply referred to as the substrate) and a plastic case or the like.

この方法は、材料費、加工費で高価なものとなっている
This method is expensive due to material costs and processing costs.

この発明は、上記の点kかんがみ′Cなされたもので、
基板の表面のみ樹脂コーティングすることにより、放熱
効果を低下させず、安価に組み立てることを目的とする
ものである。以下1図面についてこの発明を説明する。
This invention has been made in consideration of the above points,
By coating only the surface of the substrate with resin, the purpose is to assemble it at low cost without reducing the heat dissipation effect. The invention will be explained below with reference to one drawing.

第1図(a)〜(d)は、この発明の一実施例を示す工
11図で、第1図(a’)は第1図(a)の正面図であ
る。
FIGS. 1(a) to 1(d) are 11 views showing one embodiment of the present invention, and FIG. 1(a') is a front view of FIG. 1(a).

第1図(a)、(a’)Kおい【、1は基板で、2は半
導体チップであり、基板1の裏面に耐熱テープ3を貼り
付ける。この場合、複数個の基板1に同時に貼り付けが
できるよ5にクリップリード4でクランプされ、かつ直
列に保持されている。次に、流動浸漬樹脂モールド法に
より、流動浸漬樹脂5をコーティングし、第1図(b)
の状態とする。コーテイング後流動浸漬樹脂5が、まだ
軟かい5ちに耐熱テープ3を剥離し、第1図(e)の状
態とする。流動浸漬樹脂5をアフターキュア後必要に応
じ所定寸法の放熱板6を基板1に貼り付ける。この場合
、放熱板6は、熱抵抗によって形状および接着方法(ハ
ンダ付けまたは樹脂接着)の選択を行う。かくして目的
の組立てを完了する。
1 (a), (a') 1 is a substrate, 2 is a semiconductor chip, and a heat-resistant tape 3 is pasted on the back surface of the substrate 1. In this case, the substrates 5 are clamped with clip leads 4 and held in series so that they can be attached to a plurality of substrates 1 at the same time. Next, a fluid immersion resin 5 is coated by a fluid immersion resin molding method, as shown in FIG. 1(b).
state. After coating, the heat-resistant tape 3 is peeled off while the fluidized immersion resin 5 is still soft, resulting in the state shown in FIG. 1(e). After the fluidized immersion resin 5 is after-cured, a heat dissipation plate 6 of a predetermined size is attached to the substrate 1 as required. In this case, the shape and bonding method (soldering or resin bonding) of the heat sink 6 are selected depending on the thermal resistance. In this way, the desired assembly is completed.

第2図(a)〜(e)は、この発明の他の実施例を示す
工程図で、第2図(a′)は第2図(a)の正面図であ
る。
FIGS. 2(a) to 2(e) are process diagrams showing another embodiment of the present invention, and FIG. 2(a') is a front view of FIG. 2(a).

この実施−例では、第2図(a)k示すごとく放熱板6
を基板1に貼り付けまたはハンダ付は後耐熱テープ3で
テーピングし、流動浸漬樹脂5で第2図(b) k示す
ようにコーティングした後、耐熱テープ3を剥離し、第
2図(e)のように組立てを完了する。この場合、貼り
付ける放熱板6は比較的小さい形状のものとしておき、
熱抵抗によって必要な形状の放熱板をさらに、ねじ止め
等によって取り付けるようkすることも可能である。
In this embodiment, a heat sink 6 is used as shown in FIG. 2(a)k.
After pasting or soldering to the board 1, tape it with heat-resistant tape 3 and coat it with fluidized immersion resin 5 as shown in Fig. 2(b), then peel off the heat-resistant tape 3 and remove it as shown in Fig. 2(e). Complete the assembly as shown. In this case, the heat sink 6 to be pasted is of a relatively small shape,
It is also possible to further attach a heat sink having a shape required depending on the thermal resistance using screws or the like.

以上説明したようKこの発明は、パワー用の混成集積回
路の高価なパッケージを、安価な流動浸漬樹脂のコーテ
ィングへの変更過程において、通常の流動浸漬樹脂のコ
ーティングでは全面コーティングとなり、放熱板が取り
付は不可能となることを防止でき、放熱効果の低下を招
かず、安価なパッケージを実現できる利点がある。
As explained above, this invention was developed in the process of changing the expensive package of a power hybrid integrated circuit to an inexpensive fluidized dip resin coating. This has the advantage that it is possible to prevent the possibility of attachment, and that a low-cost package can be realized without deteriorating the heat dissipation effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)はこの発明の一実施例を示す各工
程の側面図、第1図(a′)は第1図(a)の正面図、
第2図(a)〜(e)はこの発明の他の実施例を示す各
工程の側面図、第2図(aj)は第2図(a)の正面図
である。 図中、1は厚膜抵抗基板、2は半導体チップ、3は耐熱
テープ、4はクリップリード、5は流動浸漬樹脂、6は
放熱板である。なお、図中の同一符号は同一または相当
部分を示す。 代理人  葛 野 信 −(外1名) 第1図 (a′) 第2図 (a′) 手続補正書(方式) I(付、、57.2月18日 1、  ’JG件の表示    特願昭 56−138
964号2、発明の名称    混成集積回路の組立方
法3、補正をする者 6、補正の対象 明細書の図面の簡単な説明の欄および図面7、 補正の
内容 DJ  明細書第4頁8〜10行のr各工程の・・・・
・・第2図(a)の」の個所を下記のように補正する。 「混成集積回路の組立工程の側面図、第2図は第1図(
a)の正面図、第3図(a)〜(c)はこの発明の他の
実施例を示す混成集積回路の組立1稈の側面図、第4図
は°第3図(a)の」 (2)  図面第1図、第2図を補正して別紙のように
第1図〜第4図とする。 以上 第1図 第2図 ム 1 第3図   第4図 ム 特許庁長官殿 事件の表示    特願昭 56−138964号発明
の名称    混成集積回路の組立方法補正をする者 5、 補正の対象 明細書の発明の詳細な説明の欄 6、 補正の内容 (1)明細書第2頁11行の[第1図(a’) Jを、
「第2図」と補正する。 (2)同じく第2頁13行の「第1図(a) 、 (a
’) Jを、「第1図(a)および第2図」と補正する
。 (3)同じく第3頁7行の「第2図(a)〜(C)」を
、「第3図(−)〜(C)」と補正する。 (4)同じく第3頁8行の[1a2図0′)は第2図(
a)」を、「第4図は第3図(a)」と補正する。 (5)同じく第3頁10行の「第2図(&)」を、「第
3図(a)」と補正する。 (6)  同じく第3頁12〜13行の「第2図(b)
」を、「第3図(b)Jと補正する。 (7)  同じく第3頁14行の「第2図(C)」を、
第3図(C)」と補正する。 以上
FIGS. 1(a) to (d) are side views of each process showing an embodiment of the present invention, FIG. 1(a') is a front view of FIG. 1(a),
FIGS. 2(a) to 2(e) are side views of each process showing another embodiment of the present invention, and FIG. 2(aj) is a front view of FIG. 2(a). In the figure, 1 is a thick film resistance substrate, 2 is a semiconductor chip, 3 is a heat-resistant tape, 4 is a clip lead, 5 is a fluidized immersion resin, and 6 is a heat sink. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person) Figure 1 (a') Figure 2 (a') Procedural amendment (method) I Gansho 56-138
964 No. 2, Title of the invention: Method for assembling a hybrid integrated circuit 3, Person making the amendment 6, Brief description of drawings in the specification subject to the amendment and drawing 7, Contents of the amendment DJ Specification page 4, pages 8-10 Row r of each process...
... Correct the part ``'' in Figure 2 (a) as follows. "A side view of the assembly process of a hybrid integrated circuit, Figure 2 is similar to Figure 1 (
3(a) to 3(c) are side views of one assembly of a hybrid integrated circuit showing other embodiments of the present invention, and FIG. 4 is a front view of FIG. 3(a). (2) Figures 1 and 2 of the drawings have been corrected to provide Figures 1 to 4 as shown in the attached sheet. Above Figure 1 Figure 2 Figure 3 Figure 4 Figure 4 Indication of the case of the Commissioner of the Patent Office Title of the invention in Japanese Patent Application No. 56-138964 Person amending the method of assembling a hybrid integrated circuit 5 Description subject to amendment Detailed Description of the Invention Column 6, Contents of Amendment (1) Page 2 of the Specification, Line 11 [Figure 1 (a') J]
Corrected to "Figure 2". (2) Similarly, page 2, line 13, “Figure 1 (a), (a
') Correct J to "Figure 1 (a) and Figure 2". (3) Similarly, "Fig. 2 (a) to (C)" on page 3, line 7 is corrected to "Fig. 3 (-) to (C)." (4) Similarly, [1a2 Figure 0') on page 3, line 8, is shown in Figure 2 (
a)” is corrected to “Fig. 4 is Fig. 3 (a).” (5) Similarly, "Fig. 2 (&)" on page 3, line 10 is corrected to "Fig. 3 (a)." (6) Similarly, page 3, lines 12-13, “Figure 2 (b)
” is corrected as “Figure 3 (b) J. (7) Similarly, “Figure 2 (C)” on page 3, line 14, is
3(C)". that's all

Claims (2)

【特許請求の範囲】[Claims] (1)  厚膜抵抗基板の裏面に耐熱テープでテーピン
グを施し、Vt動浸漬樹脂に全体を浸漬して樹脂コーテ
ィングを行った後、前記耐熱テープを引きはがし、前記
厚膜抵抗基板の耐熱テープをはがした部分−を放熱板に
貼り付けることを特徴とする混成集積回路の組立方法。
(1) Tape the back side of the thick film resistor board with heat resistant tape, immerse the whole body in Vt dynamic immersion resin to coat the resin, then peel off the heat resistant tape and remove the heat resistant tape of the thick film resistor board. A method for assembling a hybrid integrated circuit characterized by pasting the peeled portion on a heat sink.
(2)厚膜抵抗基板に放熱板を貼り付けた後、放熱板の
みに耐熱テープでテーピングを施し、流動浸漬樹脂に全
体を浸漬して樹脂コーティングを行った後、前記耐熱テ
ープを引きはがすことを特徴とする混成集積回路の組立
方法。
(2) After attaching a heat sink to the thick film resistor board, tape only the heat sink with heat resistant tape, immerse the entire body in fluidized immersion resin to coat it with resin, and then peel off the heat resistant tape. A method for assembling a hybrid integrated circuit characterized by:
JP56138964A 1981-09-02 1981-09-02 Assembling method of hybrid integrated circuit Pending JPS5839018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56138964A JPS5839018A (en) 1981-09-02 1981-09-02 Assembling method of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56138964A JPS5839018A (en) 1981-09-02 1981-09-02 Assembling method of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5839018A true JPS5839018A (en) 1983-03-07

Family

ID=15234290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56138964A Pending JPS5839018A (en) 1981-09-02 1981-09-02 Assembling method of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5839018A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625645U (en) * 1985-06-27 1987-01-14
JPS6411353A (en) * 1987-07-06 1989-01-13 Matsushita Electric Industrial Co Ltd Electronic circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625645U (en) * 1985-06-27 1987-01-14
JPS6411353A (en) * 1987-07-06 1989-01-13 Matsushita Electric Industrial Co Ltd Electronic circuit device

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