JPS5841014B2 - Parallel operation method of relay equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an economical and highly reliable repeater, particularly to a parallel operation scheme for a heterodyne repeater.

In communication systems that require high reliability, a working-standby system is adopted in which a working system device and a standby system device are provided, and switching to the standby system device occurs when a failure occurs in the working system device.

Such a working backup system is also adopted at satellite stations in broadcasting systems in order to prevent service degradation.

For example, when each broadcast channel is relay broadcasted on the same satellite station, each channel CH1
~ Corresponding to CHn, currently used heterodyne repeater REP1
a=PFPna and standby heterodyne repeater REP1
b=REPnb, and the input signal is sent to the demultiplexers H1 to H.
Branched by n to the current heterodyne repeater REP1
a=REPna and standby heterodyne repeater REP
1 b =REPn b, and switch the switching device SW1~
During normal operation, the current heterodyne repeater REP is activated by SWn.
The outputs of 1a to REPna are selected and sent.

For example, when a failure occurs in the active heterodyne repeater REP2a, the switching device SW2 switches to the backup heterodyne repeater REP2b, and sends out the output of the backup heterodyne repeater REP2b.

Therefore, interruption of broadcasting can be avoided. As mentioned above,
In the conventional active backup system, even though the backup system is completely unnecessary during normal operation, it must be installed with the same configuration as the active system, and therefore it is necessary to have an idle part. It was extremely uneconomical.

Furthermore, if the switching device fails, switching becomes impossible even if at least one of the active system and standby system is normal, resulting in a system down.

In other words, even if a working system device and a standby system device are installed, if the switching device breaks down, switching between the working and standby system will not be possible.
Reliability was dependent on the reliability of the switching device itself.

The present invention improves the conventional drawbacks as described above, and has a configuration in which there is no idle part by providing a shared section for multiple channels in the front stage, and is economical by operating the rear stage in parallel and combining the outputs. The aim is to simultaneously improve performance and reliability.

Examples will be described in detail below.

FIG. 2 is a block diagram of an embodiment of the present invention, in which the input signals of each channel CH1 to CHn are demultiplexed by demultiplexers H1 to Hn and sent to the first and second multiplexing units MULI, respectively.
, MUL2, and are collectively frequency-converted and amplified by the signals from the local signal source LS to the first and second demultiplexing sections HD1. Added to HD2.

And the demultiplexers H11 to H1n of the demultiplexer HDI and HD2
, H21 to H2n, the output side channels CH1' to CH
Signals of the same channel separated for each channel signal corresponding to n' are combined by phase combining sections SM1 to SMn and sent to output side channels CH1' to CHn'.

The multiplexing units MUL1 and MUL2, which are very small power stages, are shared by each channel CHI to CHn and have a duplex configuration, so two multiplexing units are sufficient regardless of the number of channels. The structure is economical and highly reliable, and is easy to implement.

Furthermore, the phase synthesizers SMI to S M n combine two systems of signals in the same phase and output the resultant signal, and have a configuration in which even if one system fails, the output automatically increases to a predetermined level. Therefore, reliability can be improved.

Note that such a phase synthesis section can employ a configuration that has already been proposed as a means for synthesizing parallel outputs.

The configuration of the phase synthesis section is explained in detail in Japanese Patent Application No. 52-93543.

FIG. 3 is a block diagram of an embodiment of the present invention in the case of a two-channel dual heterodyne repeater, with BPFI, B
PF2 is a bandpass filter corresponding to the branching filters H1 and H2, AI and A2 are combining circuits, HAl and HA2 are first frequency converters, and IAI.

IA2 is an intermediate frequency amplifier, La, Lb, Lla
.

Llb, L2a, L2b are active and standby local oscillators, BPFII, BPFI2. BPF21゜BPF22
is a bandpass filter, MIXll.

MIXI 2 , MIX21 and MIX22 are second frequency converters, PA is a power amplifier, and the same symbols as in FIG. 2 indicate the same parts.

Channel CH1 is Fl for the carrier frequency of the input signal.

Channel CH2 is F2 and local oscillator La.

Assuming that the oscillation frequency of Lb is FLI, in one system, the input signals of channels CI-II and CH2 are synthesized by the synthesis circuit A1, and the input signals of channels CI-II and CH2 are synthesized by the synthesis circuit A1 to the second frequency converter H of the multiplex processing unit MULI.
The frequency F from the working local oscillator La is added to A1.
The frequency is converted by the LI signal.
F I F I, 1 and F b' = F2-FL
is converted into intermediate frequencies F a' and F b' of l,
It is amplified by a wideband intermediate frequency amplifier ■A1.

Then, only the signal of the frequency Fa' is applied to the second frequency converter MIX11 by the band pass filter BPF11, and is frequency-converted by the signal of the frequency Fal from the current local oscillator Lla, so that Fa=F a ' + F al
The frequency of the channel CHI' becomes the frequency of the channel CHI', and only the signal of the frequency Fb' becomes the frequency of the second channel CHI' by the bandpass filter BPF12.
In addition to the frequency converter MIX12, the currently used local oscillator L
The frequency is converted by the signal of frequency Fa2 from 2a,
This becomes the frequency of channel CH2' of Fa-Fb'+Fa2.

The frequency relationship is exactly the same in the other system as well.

Then, the signals of the same frequency of one system and the other system are sent to the phase synthesizer SM1. They are respectively added to SM2 and amplified by the composite power amplifier PA, and a signal of frequency Fa is sent to channel CH1', and a signal of frequency Fb is sent to channel CH2'.

Therefore, even if a failure occurs in the first multiprocessing unit MUL1,
Channels CHI, C are processed by the second multiprocessing unit MUL2.
Since the input signals of H2 are processed all at once, there is no chance of system failure.

Also, a part of the demultiplexing section, for example, the second frequency converter MIXI 2
Even if a failure occurs in the second frequency converter MI of another system,
If X22 is healthy, the transmission output of channel CH2' will not be cut off.

In addition, in the local oscillator signal source LS, the local oscillator is configured by a working/standby switching system, so that even if the working local oscillator fails, the system will not go down.

Note that if the local oscillator has very high reliability, it is of course possible to use a configuration other than the active/standby switching system.

Also, the case where three power amplifiers PA are connected in parallel corresponding to each output side channel is shown, but this is because the desired power amplification is possible when each power amplifier PA is packaged. are connected in parallel to each other, so that even if a failure occurs in one power amplifier PA, transmission will not be interrupted.

FIG. 4 is a block diagram of an embodiment of the present invention in the case of an n-channel double heterodyne repeater, and FIG.
The same symbols as in the figure indicate the same parts, and the subscript n is the channel CH.
Indicates that it corresponds to n.

In this embodiment as well, the first multiplex processing unit MULI includes the first frequency converter HAI and the intermediate frequency amplifier A1.
and a second multiplexing unit MUL2 consisting of a first frequency converter HA2 and an intermediate frequency amplifier IA2.
It is shared by I to CHn.

Also, the two systems operate in parallel, and the parallel outputs are combined and output in the phase combining sections SM1 to SMn.

Therefore, even if a partial failure occurs, the system will not go down, and relay output can be performed.

As explained above, the present invention provides the multiprocessing unit MULI
, MUL2 are shared by each channel, resulting in an economical configuration, and since it is a duplex configuration, reliability can be improved.

Further, since the outputs of the two systems are combined by the phase combining sections SM1 to SMn, a switching device as in the conventional example is not required, and reliability can also be improved by this.

Note that various configurations other than those shown in FIGS. 3 and 4 can be adopted as the configuration of the heterodyne repeater, and the number of frequency conversion stages can also be freely selected.

Although the present invention has been described with respect to a heterodyne repeater, it goes without saying that it can also be applied to a booster type or general repeater that does not require frequency conversion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional heterodyne repeater in active protection mode, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 and 4 are block diagrams of the present invention for 2 channels and n channels. FIG. 2 is a detailed block diagram of an embodiment. H1 to Hn are demultiplexers, MULI and MUL2 are multiplex processing units, LS is local signal source, HDl and HD2 are demultiplexers, H1
1 to H1n, H21 to H2n are branching filters, SM1 to SMn
is a phase synthesizer.

Claims (1)

[Claims] 1 In a method of relaying signals using a relay device operating in parallel, first and second multiplexing units that collectively amplify or frequency convert each input signal of a plurality of channels, and the first and second multiplexing units First and second demultiplexing means that separate the output of the processing section into frequencies corresponding to each output channel, and synthesize the signals of the same frequency demultiplexed by the first and second demultiplexing means. 1. A parallel operation method for a relay device, characterized in that the relay device is equipped with a phase synthesizer that outputs signals corresponding to the output side channels, and relays and outputs signals of a plurality of channels.