JPS5841484A - Semiconductor memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory circuits, and more particularly to state-type semiconductor memory circuits.

In general, a stater type semiconductor memory circuit has a pair of bit lines (mx, .

BL), a large number of memory cells connected to be sandwiched between the pair of O bit lines, and the pair of bit lines (
The basic components are a pair of load transistors inserted into each of BL, BL)K, and a word line extending in the X direction for selecting each of the plurality of memory cells. Conventionally, there have been two problems in semiconductor memory circuits having the above structure, which have been drawbacks in semiconductor memory circuits based on ζO. The first drawback is that power consumption becomes unnecessarily large. This is because in the above semiconductor memory circuit, one of the pair of bit lines is always connected to one of the pair of bit lines through one of the pair of load transistors! This is because the format is such that the flow is 1kfIt. The second drawback is that it is difficult to make the access time very fast. There are two reasons for this second drawback.

The tenth cause is that when reading information from the accessed memory cell to the bit line, the steady current is drawn through the transistor in the memory channel and at the same time the information is transferred onto the bit line. Therefore, the read speed is drastically reduced. The second cause is the Y-C mutual contact (Y-C mutual contact), mainly the g-yu of the a-de transistor.In general, the larger the 1m is, the better it is in order to improve the AC speed. Are known. However, it is also well known that in order to increase g, the speed of the transistor itself must be increased. In this case, in order to increase the degree of integration, the design is usually made in the direction of decreasing -, and this results in sacrificing access time. The object of the present invention is to propose a semiconductor memory circuit which can eliminate the above-mentioned 92 drawbacks.

In accordance with the above object, the present invention is characterized in that - of the load transistor is made to appear indestructible depending on information at the time of access, and the conventional steady current is controlled in accordance with the information.

The misfire will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram showing a general state-of-the-art semiconductor memory circuit. In this figure, ML and BL are a pair of bit lines, and the pair of bit lines (BL,
A plurality of memory cells Me are arranged in engagement with the memory cell IIL). Isao 1-0 Pitthuin (BL.

BL)K also includes a pair of load transistors (Ql.

42) are inserted respectively. On the other hand, the word line WL is engaged with the memory cell MC, and a desired memory cell MC is captured by the bit line and the word line. In reality, there are a large number of memory cells, a large number of pairs of pin lines, and a large number of word lines, but these are not shown. Further, each bit line pair is provided with a write buffer for writing information and a sense amplifier for reading information, but these are not shown.

Assume now that the BLIIK logic L (therefore, the logic H on the ■ side) of the memory cell MC is stored, and that the memory cell MC is now accessed from the word line WLiC. In this case, the states of each transistor are first that the logics L and H are stored as shown in the figure, so the transistor Qi is on and the transistor Q is off.

Then, since there is an access from the word line WL, both the transistor Qs and the transistor Q4 are turned on.

Then, both transistors Qs and Qs turn on, so the power supply (Vcc) is connected to the ground (GND).
An electric current R1 flows through the transistor Q1 along the route indicated by the dotted line in the figure. This is a limited multi-stationary KR (40) in which the memory cell Me continues to be accessed, and this is the stationary current described above. This appears as a waste of power consumption (the first defect mentioned above).On the other hand, when we look at read access, this steady power #li is drawn by transistors Qs and Qi. Therefore, from the memory cell MC's point of view, the read operation must be performed with not only the bit line ILO capacitance load but also this steady current load, which reduces the access time. It is not possible to increase the speed (the second drawback mentioned above).

Therefore, in order to eliminate the above-mentioned drawbacks, the present invention focuses on the y- of the of-f transistor (Ql-Q).

Finally, l can be adjusted as appropriate to improve power consumption and access time. Al Physically, as mentioned above, the improvement in access time is 1.1 KL, and the power consumption K") and the front power distribution fi
After the rise of t, g is made small. However, generally this
is fixed and relatively small. The reason for the small size is to increase the packaging density. For this reason, in the present invention, a level converter is introduced to make the gm variable as appropriate.There is a pair of level converters, each of which converts the logic signal appearing on one of the corresponding pair of pit lines (BL, BL). It functions to convert the level and apply the voltage to one control electrode of the corresponding pair of load transistors.

FIG. 2 is a circuit diagram showing one embodiment of a semiconductor memory circuit based on the present invention. In this figure, the same components as in FIG. 1 are denoted by the same reference symbols. LC and LCs in this figure are a pair of level converters newly introduced by the present invention.Level converters LCI and LC receive and level convert the logic signals of pit line BL and BL, respectively. , these are applied to the sound damping control electrodes of the load transistors Q1 and QsO, respectively, through the FET O+'-)).

The operation is as follows. Using the explanation of FIG. 1 again, when Illll memory cell MC is accessed by the word line Wl with the transistor Qs side in the H state, the current 1 mentioned above first rises. Before this electric power mi rises, the logic level of the pit line BL is not sufficiently cooled by KLK, but is rather at the 110 level. The level H of this pit line BL is sufficiently converted from the level Δ-interval LCIK and applied to the load transistor Ql (r-) as a sufficiently high 1xli level. Then, the load transistor Q1 is sufficiently maintained in the on state (gm large).
In this on state, if the memory cell MC is accessed as before, the current l will rise rapidly.Then, this current i will pass through the transistor Q11g to the ground (GN).
D), the logic of the pit line BL falls towards LK, and this time, the level; A sufficiently low L level is applied to the transistor QIC)f-)K. For this reason, the load transistor Q1 is rapidly turned off, and thereafter maintains this off state 11 (g1 is small).

Like this (, the o-do transistor Qs is the memory cell MC
It is extremely beneficial to turn off quickly after access. This is because the current i rapidly decreases as the memory cell MC is accessed, so that from the perspective of the memory cell MC, only the original capacitive load of the pit line exists during the information read operation, and the current load ( (load due to the draw of electric fit) will no longer exist. This leads to improved access time and eliminates the second drawback mentioned above. At the same time, the current 1 rapidly decreases and remains almost zero, which leads to an improvement in power consumption and eliminates the first drawback described above.

FIG. 3 is a circuit diagram showing another embodiment of the semiconductor memory circuit according to the present invention, and the same components as in FIG. 1 are given the same reference symbols. LC and LC are a pair of level converters introduced in the 5 new nine according to the present invention.

These are the level converters (LC, LC) and the level converters (LC@, L Cm) mentioned above.
There are two ways to obtain the rounding logic signal that changes the difference: either from one's own side (self-feedback type) or from the other side (mutual feedback type). This focuses on the logic 0 complementarity of the pit line pair (ii Len x-) in the memory cell MCK. Therefore, the level converter L in FIG.
C and LC also have a level inversion function (H-+L tL→H).However, the operating principle and effect are almost the same as the semiconductor memory circuit shown in FIG.

Finally, I will give a concrete example of a level comparator.

The level converters (LC, τ) may most simply be inverters. In addition, level converter (LCI I
LCl) may be used without level inversion or by using a tortoise inverter in which two inverters are connected in series.The inverter is extremely common6, and is one in which two YRRs are connected in series. Its form is 0M08 circuit, %, It(E*h**
tt*yxha*t)/b (Depletion) type circuit is also acceptable; however, a 0M01 circuit is preferable in terms of power consumption since the steady current for f-)K of the Lord-Funzoster is almost zero. l! Even if a :/D type circuit is used, the r-to capacitance of the 10-domain transistor is extremely small compared to the pit twin capacitance, so power consumption is hardly a problem.

As described above, according to the present invention, a semiconductor memory circuit is realized which is improved in terms of access time and power consumption compared to the conventional semiconductor memory circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a general state, rectangular semiconductor memory circuit, FIG. 2 is a circuit diagram showing an embodiment of a semiconductor memory circuit based on the present invention, and FIG. 3 is a circuit diagram showing a semiconductor memory circuit based on a non-explosion It is a circuit diagram showing another example of the memory circuit.
Ql-Q proverb - Load transistor pair, LCl, LC, LC, LC- Level converter, WL-... Word line. Figure 2 L

Claims (1)

[Claims] 1. A pair of throat trines, a memory cell engaged with the pair of bit lines, a pair of load transistors respectively inserted into the pair of bit lines, and a pair of load transistors for accessing the memory cell. In a semiconductor memory circuit comprising a word line and a word line, a pair of level converters are provided, and the pair of level converters and
1-The logic signals appearing on one of the corresponding pair of bit lines are level-converted and applied to one control electrode of the corresponding pair of defective transistors. A circuit that prints a semiconductor. λ The pair of levels; and Δ-1 apply a logic signal appearing on the one line to which one of the pair of a-domain transistors belongs, respectively, to the control electrode of the load transistor. 2. The semiconductor memory circuit according to item 1. 1. The pair of levels; Δ−1 respectively converts a logic signal appearing on the other bit line to which the other of the pair of load transistors belongs to the control electrode of one of the bit lines of the pair of load transistors. 2. The semiconductor memory circuit according to claim 1, wherein the voltage is applied with one level inverted.