JPS5842251A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve high integration by a method wherein the first groove parts having specific angles of inclination are provided on a semiconductor substrate which is selectively etched to form the second groove parts and then an oxide film is filled between the first groove parts to unite with an insulation film left at the first groove parts to form a wide field region. CONSTITUTION:A thin insulation film 37 is formed on a silicon substrate 31, whereon an antioxidant film 38 is piled. A resist film 39 is patterned in a way that the whole or part of its boundary is placed on buried field insulation films 361, 362, 363 and the antioxidant film 38, the thin insulation film 37 and the silicon substrate 31 are etched to form the second groove parts. Boron is provided by ion implantation to form a p<+> region 41 at the bottom of a groove 40. After the resist film 39 is exfoliated, a field oxide film 42 is formed between buried insulation films 362 and 363 to form a wide field insulation film. Next, the antioxidant film 38 and the thin insulation film 37 are removed by etching to form a field insulation region having arbitrary axes and no steps.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
11(M@tal 0x1d@Sem1@ondu@t
or LargeS@als l1it@grat@d
This invention relates to the reform of the inter-element isolation technology of C1re+++it).

Conventionally, the ajl selective oxidation method has been generally used as an element isolation method for MO8L81, but as the degree of integration increases, various drawbacks have arisen.

This drawback will be explained below with reference to FIG. Similarly, silicon substrate (e.g. PWi, crystal orientation: (Z
oo)) Grow oxide film 1 on J, deposit nitride film I,
This shows the state immediately after I4 turning is performed to add impurities to the field portion to form an inversion prevention region 4, and then field oxidation is performed to form a field oxide film I.

The first drawback to the selective oxidation method is that
During field oxidation, there is a so-called bird's beak effect in which the field oxide film 1 digs into and grows under the nitride film 1. That is, as shown in FIG. 1, if the length of the bird's beak is B (for example, 1 μm), the minimum spacing of the nitride film 3 (determined by the technical limit of photolithography) is A (for example, 1 μm).
), the minimum field circle C is C=2A+B (for example, 3 lines), and it is impossible to make the field width smaller than this. Recently, attempts have been made to suppress I4-dobeek by reducing the thickness of the nitride film (by reducing the thickness of the oxide film 2 below the C1 nitride film) and by reducing the thickness of the field oxide film 5. However, the former method has problems such as increased stress at the end of the field Y, making it more likely to cause defects, and the latter problem, such as a drop in field reversal voltage. It's becoming difficult. The second problem is that the ions implanted for the channel strike V I4- diffuse laterally during field oxidation, and the element formation region (portion D in Figure 1) becomes separated from the P region. Otherwise, the effective device area may become narrower.As a result, a narrow channel effect occurs in which the transistor current decreases and the threshold voltage increases.

These factors are gradually becoming smaller with the miniaturization of devices.Furthermore, as the P region becomes wider in the lateral direction, the floating distance between the N+ layer of the device region and the substrate also becomes smaller. As time goes on, it becomes impossible to ignore it.

In order to overcome the conventional drawbacks, the present applicant submitted on the same date a method of manufacturing a semiconductor device using a novel field region forming means as shown in FIGS. Hereinafter, method H will be explained.

4) tzu, silicon substrate (pg, crystal orientation: (10
0)) Oxide film etc. on top! A skinning material film 11 is deposited (as shown in FIG. 2(1)).

l) Next, mass young material [Jj is Δ
Turning is performed to form a mask material 12' (see FIG. 2(b)
).

IN) Next, using the mask material 11', for example, KOH
The substrate 11 is etched and tilted using a method such as that shown in Fig. 2 (
,) as shown).

IV) Next, using a mask material JJ/, an impurity having the same conductivity as that of the substrate J1 is added to, for example, an accelerated current 8E 50
K@V, To-jF jl5 X l O”/ai O
After ion implantation under the conditions, heat treatment is performed to #1IIIJ
A P region 14 as a channel strike and /4 region is formed at the bottom of J (as shown in FIG. 2(d)).

■) Next, after removing the first mask material Jjl, the 810° film J5 was deposited by CVD (Chew%aal Vapor D).
When the width of the opening of the groove portion 1s is 1, the thickness is deposited by the @pesltl@n method to a thickness of (11!·t (a/2 ))/2 or more.

(2nd rIA(s) shown), Konoshichi@, CVD-8
102M15 is gradually AK deposited on the substrate 11 and the inner wall surface of the trench IJ, and is sufficiently filled up to the opening of the trench 13. Note 1. At the time of this deposition, there is almost no re-diffusion in the door region J4 because the high-temperature, long-time thermal oxidation treatment as in the selective oxidation method is eliminated.

Vl) Next K, CVD-810, concentrated membrane 21 y-v-
The part of the silicon substrate 11 other than the groove 11 is exposed when
Full-scale work and ching. This K remains, and a salt-filled field region 16 is formed in the substrate 11 (as shown in FIG. 2 (--)).

k) After that, shift field area 1 by normal operation 11
An r-t oxide film 11 is formed on the island-shaped element formation region separated by #.
An r-) electrode 18 made of polycrystalline silicon is formed through the electrode, arsenic is diffused to form an n''dl region 1# of the source and drain ν, an interlayer insulating film 2o is deposited 12, and a Kuntakt hole j1 is formed. The main process of IL81 is completed by opening the At gaX (as shown in Figure 2 B). By taking the above steps, the drawbacks of the selective oxidation method can be overcome. (1) The minimum width 8 of the field is determined by the minimum width 1 of the groove JJ, and since the selective oxidation method does not allow so-called bird oxidation to occur, the minimum width 8 of the field is determined by the minimum width 1 of the groove JJ. C,
Any amount of integration is possible.

(2) When shortening the field width, in the conventional selective oxidation method, the channel length of the parasitic MO8) transistor is shortened, the inversion voltage of the field becomes lower due to the shunt channel effect, and the leakage current between fields decreases. However, if the method described in 8) is used, the channel length of the parasitic MO8) becomes longer due to the large contribution of the component in the depth direction of the groove 11, which facilitates the sheet channel effect of the field. can be prevented.

(3) In order to prevent field inversion, there is a p''lI region at the bottom of the 14-shaped trench IS] Also, since there is no thermal process for field oxidation, K is difficult to diffuse into the device formation region, and device characteristics such as the narrow channel effect mentioned above are affected by K. This eliminates the deterioration of the 1+ layer and the increase in stray capacitance between the n+ layer and the substrate due to the combination of the p+ region 011.

(4) Since field oxidation such as selective oxidation is not used, there is no defect in the silicon substrate 11 that occurs due to the stress generated when the Field P oxide film digs under the nitride film.

(5) In the selective oxidation method, a step is created between the field region and the element region, but with this method, it is possible to make the gap between the field regions completely flat, resulting in a structure that is extremely suitable for microlithography. .

As mentioned above, this method has many advantages.

However, IJI in all narrow field areas
However, when forming one wide field, there are some difficulties.

That is, the width 8 of the field region is determined by the width 8 of the trench 23, and in order to leave the insulating film in the trench II, the thickness of the insulating film is T,>a @at(#/2)/ If the width of the field region is wide, an insulating film must also be deposited with In.

For example, in order to form a field with a width of 20 .mu.m, the thickness of the insulating film must be 10 .mu.mm or more, and there are many difficult problems such as deposition time, film thickness accuracy, and conditions for preventing cracks and cracks. Furthermore, it is very difficult to form a field with a width of 200 μm (for example, the lower part of the Lt-end, the lower part of the dot, etc.) using the above method. Therefore, if a wide field is required, first select a narrow field area according to the spinning speed method, as shown in Figure 3.
6, an insulating film 23 of, for example, S tO is deposited, and a wide field region 24 is formed by photolithography, leaving a portion of this insulating film 23. Ta.

This method allows the formation of a wide field oxide film and overcomes most of the defects of selective oxidation.
In some cases, one major drawback occurs. That is,
In the case of the 0 selective oxidation method, which causes a step at the end of the wide field region 24 shown in FIG. 3 and loss of flatness, half of the field film is covered with the silicon substrate, but in this method Since the field film thickness is a step as it is, there is a step difference greater than that in the selective oxidation method.This was a major obstacle when two microrings were required near a wide field film.

This development was made in view of the above-mentioned circumstances, and its purpose is to provide a method for manufacturing semiconductor devices that solves the problems of conventional element isolation technology and enables higher integration and higher performance of L8I. Hereinafter, with reference to the drawings, a case will be described in which a simple embodiment of the present invention is applied to the manufacturing process of an n-channel MO8LSI.

(1) '*zu, silicon substrate (pH, crystal orientation: (
100)) A mass media material film such as 102 film is deposited on 17, and the mask material 32 is formed by using a photolithography method or the like to form a mask material 32 (as shown in FIG. 4(1)).

(It) Next, using 1 mask material 32 as a mask,
Make a chida and make the sides with an inclination angle of 0 nine widths (&)
O A narrow first groove portion 33 is formed. There are four methods for this process, including KOH, active ions during the process, and chinking (as shown in Figure 4 (b)).

GID Next, for example, using the mask material 52 as a mask,
Accelerating Ron at voltage 5 Q K@V, dose amount 5XI
Ions are implanted under O/d conditions to form a p region (channel strike, mother region 34) at the bottom of the first trench 3S.
Figure 4 (, ) illustration).

■ Next, after removing the mask material 71, the first groove portion 3S
If the width of is 1, then (a eat(IIF/2, 1)/
An insulating film with a thickness of 2 or more (e.g. CVD!l t o,
Membrane or S! t, N4 film) SS is deposited to fill the first trench 33 (as shown in FIG. 4(d)).

(ψ Next, the insulating film 35 is etched in the trench where the silicon substrate J1 is exposed. As a result, the field insulating film 36, 1s g-, x gs is buried only in the trench j3 of !D@1.
Ka'A;E:s (4th vA (@) shown).

(, V+) Next, a thin insulating film (for example, a 500X thermal oxidation layer) 31 is formed on the silicon substrate SJ, and this insulating film 1l
Deposit oxidation-resistant gonads (for example, 3000iQ81MN4 film) J# on Jy (#!4 shown in Figure (f)).

(vii) Next, data-end the resist film S# so that the gold part or part of the boundary is on the buried field insulating film J61sJ6@#Jg- using a photolithography method. Then, using this resist film 3p as a mask, an oxidation-resistant film S8 is etched and tenderized, a thin insulating film sr is etched and tendered, and a silicon substrate J1 is further etched and tenderized to form a trench #I2. When this silicon substrate 11 is etched, a salt-filled field insulating film 36 is formed.
1 ・j 61 #,,K so that J I's are not etched at all or hardly etched (
Note that the receipt film J# may be peeled off before etching the thin insulation 831 or the ν-based faS, and subsequent etching may be performed using the oxidation-resistant film J# as a mask. The etching depth of the silicon substrate 81 varies depending on the subsequent oxidation conditions, but it is assumed to be, for example, 5000'.

(Vlll) Next, the resist film 89 ((Vlll
) -t" v N
h) As shown).

(1x) Next, after peeling off the resist film S#, field oxidation is performed using the oxidation-resistant film 38 as a mask, and a field oxide film 4j is removed between the refilled field insulating layers 86@e16m to a film thickness of 1 firn. to form a wide field insulating film. Here, silicon substrate J1
In this process, a wide field insulating region that is flat and flat with the element forming region can be formed without forming the field oxide film 41 that is twice the depth of the trench (as shown in FIG. 4(1)).

At this time, if an N4 film or the like is used as the buried field insulating material 3111°8g, the field oxide film 41 will be cut into the lateral direction during field oxidation (
(Bird beak) does not occur at all in principle, and even when the 8102 film is used as the barrier field insulating film 86Bm16B, there is almost no problem with Δ-de C-rehiro. The thin insulating film J1 underneath is removed by etching (as shown in FIG. 4(j)).

(x:)Finally, an r-) oxide film 43 and an r-) electrode (for example, polycrystalline silicon) 44 are provided, and, for example, arsenic is diffused to form n regions 4J that will become sources and drains, and an interlayer insulating film ( For example, by CVD!IIO, a film) 4- is deposited, and a run tact hole 41 is opened.

For example, by applying the arrangement 148 of L8I and ending the main authority of L8I (as shown in Fig. 4), by using the above-mentioned method 1, various results can be obtained when using the selective oxidation method described above. In addition to overcoming the drawbacks, it becomes possible to form a field insulation region of any axis without a step. Therefore, it can greatly contribute to higher integration and higher performance of LIII. Next, another embodiment of this device will be described.

(1) When forming the silicon rich substrate zxVcp region J4, in the embodiment shown in FIG.
By ion implantation using the mask material 32 such as No. 2 as a mask, as shown in FIG. As shown in FIG. 6, when the substrate 31 is etched to form the first groove 37, the resist film 49 is placed directly on the substrate without using the mask material S2, and the fins are etched. Use it as a mask.

It is also possible to use the resist as a mask to perform ion implantation.

(2) In the embodiment shown in FIGS. 4(&) to (k)K, ions are implanted into the p"fl region (channel strike, /f region
*41 is formed, however, depending on the concentration condition of the silicon substrate 31, this p region 34e41 is not necessarily necessary.Ion implantation may not be performed.Also, +@I J! The ion implantation mask is not limited to the resist film S2, but may also be an insulating film, and may be provided not only by p+ region expanded ion implantation but also by a diffusion method. - This insulating film SO may be formed by, for example, oxidizing the silicon substrate 11, or may be formed by depositing a CVD film or the like.

Note that in case of E, the width of the opening of the first groove IJ is somewhat narrower.

(4) Cut and etch the insulating film S5 to form the first trench IJ.
Buried field insulating film S61 only.

When leaving sasesgst, this field insulating film J'
A structure may be adopted in which S*J#I sagm falls from the surface of the silicon substrate 810 (as shown in FIG. 8).

(6) Field insulating film 16@*j6B+1
-s may have different depths.

(6) After depositing the insulating film 35 in the first trench I8 to completely close the first trench J1, deposit a female fusible insulating film (for example, fron silicide glass (BBQ), phosphorus silicide Glass (
PIiG), arsenic sulfide glass (ASG), etc.) are deposited and melted, and then the insulating film J5 is etched and deposited using the first layer (DIllltlsx). A two-layer structure with a thin film may be used.

(6) In the example shown in Figures 4 and 4, at and N4 films were used as the oxidation resistance j[38, but any film that can suppress oxidation of the silicon substrate 31 may be used. For example, it may be an AA, O, film or a very thick 02 film. The oxidation-resistant film 38 and the silicon substrate J were etched using a photolithography method. First, the silicon substrate J1 was etched and etched to form a second groove 40, and later the oxidation-resistant film 38 was deposited. Field oxidation may be performed after etching the oxidation-resistant film S8 in the second groove portion 40 using a photolithography method. After etching the oxidation-resistant film 1#, the silicon substrate 11 was etched and the second groove 4o was formed, and then the oxidation-resistant film Za was etched and the oxidation-resistant film Za After that, field oxidation may be performed without etching the silicon substrate 31. In this case, the flatness of the field region and the device region may be sacrificed to some extent to suppress the diffusion of the channel stock region 114 into the device region. The effect is great. When the insulating film 11 is not necessarily deposited, the insulating film 11 does not necessarily have to be deposited. As long as it is oxidized during field oxidation, field oxidation may be performed without performing the method shown in FIG. 7(1) and without etching the thin insulating film j1.

(11) In the embodiment shown in #, the field oxide film 42 may be etched using the oxidation-resistant film JI as a mask to form a flat structure (as shown in FIG. 1O).

(6) The embodiment of Shunki C1l not only performs field oxidation on the silicon substrate S1 without etching the silicon substrate S1 as in the above-mentioned embodiment, but also performs field oxidation after etching the silicon substrate S1. It also applies to K. In spite of etching the silicon substrate JJ, the y4-leFll formation 114j is thick')I
This is effective when the 1-silicon protrudes above the surface of the board 31 and the flatness is impaired.

(2) In the above embodiment, a V-shaped groove was used as the groove, but the first groove 83' having a flat bottom may be formed in the substrate 31, as shown in FIG. 11. ,
The thickness of the insulating film to be deposited is the same as described above (a@ot
・(#/2))/2 or more.

α◆ Regarding the shape of the groove, the side surfaces do not necessarily have to be flat, and a first groove I〆 having one inclined side surface as shown in FIG. 12 may be formed on the substrate j1. If the inclination angle of the side surface at the opening end of the groove 33'' is -, the thickness of the insulating film to be
(#/2)/2 or more. (2) As shown in FIG. However, the first groove portion 81' having the inclined side surface may be formed by etching with a mask material, such as acid-based machining, tendering liquid, guts, LE machining, tinting liquid, etc. (No. 18gA(b)) (Illustrated).

(2) As shown in FIG. 14 (1), an insulating film JJ such as an oxide film is deposited on the substrate 31, and after this is exposed to a plasma atmosphere, a mask material such as a resist pattern Jj is formed, and this is The first continuous portion JJ' may be formed by etching the insulating metal II and the substrate 31 as a mask (first
4 colors (as shown).

(b) First! As shown in $wA(a), when forming a first groove sj having an inclined side surface on a substrate 31, and further depositing an insulating film IJ and etching this, the base I
[There is no need to etch the layer 11 to expose it.
As shown in FIG. 5 (it), the insulating film S♂ is etched and tenderized so as to remain on the surface of the substrate 11 other than the field region S6, and the remaining insulating film 35' is applied to the r-) insulating film intermediate insulating film, etc. , or may be used as a part of them.
40! on the board Jl as shown in FIG. 16(1)! A first groove portion SS having an inclined survey is provided using a mask material 32 made of a material such as the like, and after an insulating film S5 is deposited with this mask material J2 remaining, the insulating film 8 is deposited so that the mask material S1 remains.
5 may be etched to form the field region 3g (as shown in 19th vA(b)).

(To) As shown in FIG. 17, the insulating film s ti' is left in the first trench Ss having the inclined side surface of the substrate 11 so as to protrude in an arc shape from the substrate surface.
d may also be formed.

Although the above embodiments have been described with respect to the manufacturing process of n-channel MO8L81, it goes without saying that the invention can also be applied to the manufacturing process of p-channel MO8LSI.

As explained above, according to the present invention, it is possible to overcome the various drawbacks of pigeon lofts using conventional selective oxidation methods, and also to form a field insulation region of any width without steps, As a result, it is possible to provide a method of manufacturing a semiconductor device that allows a person to achieve high integration and high performance of LsI.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view for explaining the problems caused by the conventional selective oxidation method, and Figures 2 (,) to (f) show the manufacturing process of n-channel MO8L81 according to the method submitted by the applicant on the same date. 3 is a sectional view showing a state in which the shift field region is formed by the deforming means shown in FIGS.
FIGS. 4(a) to 4(a) are cross-sectional views showing the manufacturing process 1 of the n-channel MO8LSI according to the -II theory of the present invention, FIG. 6, FIG. 6, FIG. 7, FIG. 8, and FIG. (1), (b), Figure 1O, Figure 11, Figure 12, Figure 13 (,), (b)
, Figure 14 (&), (Xun, Figure 15 (a), 佽), 1st
FIG. 6 (civilian), FIG. 17 (b), and FIG. 17 are sectional views showing other embodiments of the present invention. sl...Silicon substrate, 81...Mass p material, sx. ,y/*3 J'...first groove, J4...p
+ region channel strike, d region), #5...insulating film, zg. 16te Jam*j#s...Buried field insulating film, Jl...Thin insulating film, Jl-...Oxidation resistant film, 39...Resist film, 40...Second part, 41 ...p+ region 42...field oxide film, 43...dirt oxide film, 44...r-meter electrode, 4
5...-region (source, drain), 4g" interlayer insulating film, 41... = contact hole, 4g-m wiring, applicant's agent, patent attorney Takehiko Suzue Figure 1 Figure 2 (a) ) 31j!J 234- Fig. 4 Fig. 4 Fig. 5 Fig. 6 Fig. 9 Fig. 10m Fig. 15 Fig. 16 Fig. 17 Commissioner of the Patent Office Shima 1) Haruki Tono 1, Incident display Patent Application No. 56-140773 2, Name of the invention: Process for manufacturing semiconductor devices 3, Relationship with the case of the person making the amendment Patent applicant (3G?) Tokyo Shibaura Electric Co., Ltd. 5, Date of amendment order 4m, 1982 June 26th, 2016, 7th statement subject to amendment, page 24, line 10, a 2 of the statement of contents of the amendment (see "Figure 2 (1)
) to (f)" should be corrected to read "Fig. 2 (Maro) to (g)."

Claims (7)

[Claims] (1) - A factory that provides a first part having an inclined side surface in a desired part of a semiconductor substrate and whose inclination angle 9 is in the range of o<e<so'', and a semiconductor including the first part. a step of depositing an insulating metal over the entire surface of the substrate so that the thickness of at least a tos(@/m)/2 or more is 1, where the minimum width of the opening of at least a part of the 4111 is a; Etch this insulating film
f l, depositing an oxidation-resistant film on the main surface of the semiconductor substrate with the insulating metal remaining in the first groove, and depositing the first ζO oxidation-resistant film on the main surface of the semiconductor substrate. The second part of the fireflies is formed by selectively etching and cindering between the sSs, field oxidation is performed using this oxidation-resistant film as a mask, and the oxide film is used to close the tenth trenches. 2. Methods for manufacturing a semiconductor device characterized by a human being integrated with an insulating film formed in the device, and a factory for forming a wide field region. (2) After depositing an oxidation-resistant film on the main surface of the semiconductor substrate where the insulating film remains, selectively etching is performed between the oxidation-resistant film and the first Oj11 portion of the semiconductor substrate. By cindering, a 20111 part having an insulating metal left in the first groove part on at least a part of the side surface is provided, and then field pH is changed using the oxidation-resistant film as a mask, as described in 4IIIk. A method for manufacturing a semiconductor device according to claim 1. (3) After providing the first groove in the semiconductor substrate, the entire surface of the semiconductor substrate or at least a part of the groove is oxidized or nitrided to prevent the first groove from being blocked. A method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that a nitride film is grown. (4) After providing the first groove on the conductive substrate, and after providing the second part on the open base 1, remove impurities from the bottom or side of each groove of the same conductivity type as the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a part of the semiconductor substrate is selectively doped. (5) A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the semiconductor substrate provided with the first groove portion is completely removed. (6) A second groove portion having the insulating film left in the first groove portion on at least a part of the side surface is provided by selectively etching between the @1 groove portions of the semiconductor substrate where the insulating film remains. After that, an oxidation-resistant film is deposited on the entire surface of the semiconductor substrate, a part of the second oxidation-resistant film is etched, and then field oxidation is performed using this oxidation-resistant film as a mask. Method for preparing a semiconductor device according to item 1. (7) The method for manufacturing a semiconductor device described in the patent, characterized in that after the field oxidation, a part of the field oxide film is etched using the oxidation-resistant film as a mask to form a flat structure.