JPS584459A - Address comparison system in computer varying address mode - Google Patents

Abstract

PURPOSE:To improve the economy, by eliminating the need for the comparison between a program event recording(PER) start address and a PER end address in each address mode, every time when a specified main storage access event takes place. CONSTITUTION:When an instruction readout event or a main storage renewal event takes place, selectors 1 and 2 select the content of a control register 11 in accordance with an address mode. The output of the selectors 1 and 2 is applied to adders 5 and 6 respectively. The adder 5 calculates the difference between the content transmitted and that of an execution address register 8, and the adder 6 also calculates the difference between the transmitted content and that of the execution register 8. A check circuit 9 checks if an address handled with an instruction readout event or with a main storage renewal event exists between the PER start and end addresses, based on the output of the adders 5 and 6 and + WRAP and AROUND signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides program event recording (P
E R: Program Ev*st Ree*
In a computer that has the rd4mg → function and multiple types of address mode, the instruction read address or data write address is the PER start address and P
The present invention relates to an address comparison method in an address O-mode variable computer that makes it easy to determine whether the present invention exists in an area specified by an ER end address.

PER is a mechanism for program monitoring.

This is to facilitate the depacking of Grograms.
For example, the occurrence of an event such as reading an instruction from a designated main storage area or changing the contents within a designated main storage area is monitored. When the above-mentioned event occurs during the execution of an instruction, if the system is set in a state where the PER mechanism can be operated, a program interrupt by PERK will occur after the execution of the instruction is completed.

The control register IO stores a PER start address, and the control register 11 stores a PER end address. If the instruction read address or data write address is between the PER11 start address and the PER end address, a program interrupt occurs. If the PER end address is smaller than the PER start address, the address has wrapped around.

That is, the addresses from the PER start address to the final address and from the θ address to the PER end address are monitored by PEH. The fact that the target address exists between the PER start address and the PER end address means that in the case of a read event of an instruction in main memory, the first byte of the instruction falls within the range of the monitored address. Regarding updates in main memory,
This means that even part of the monitored address will be updated.

By the way, there are computers that have multiple types of address modes and can arbitrarily select the address mode. Address modes include, for example, separate bit address modes,
31-bit address mode.

There are 32 pits and 2 toads modes. Figure 1 is P
This shows a conventional address comparison method for checking whether there is an address handled by an instruction read or a main memory write between the ER start address and the PER end address, where 1 and 2 are selectors, and 3 is a complement. Circuit s4 is an adder, 5 and 6 are also adders, 7 is a complement circuit, 8 is an effective address register, 9 is a check circuit, IO is a control register, and 11 is also a control register.0 Control register 10 is 32 It is made up of bits.

The 0 control register 11 in which the PER start address is stored also has a 32-bit configuration;
The R end start address is stored. Address mode A is spit address mode, address mode B is 31-bit address mode t, address
Mode C indicates a 32-bit address mode, respectively. Which address-mode is currently in %PS
It is designated by W. Selector 1 sets all bits 00 to 07t of control register 10 to "0" in the case of address mode B, and outputs bits 00 to 07t of control register 10 as roJ rc. When the address mode C is entered, the contents of the control register 10 are output as they are 0.
The selector 2 operates in the same way as the selector 1. The O adder 4 is a dedicated adder for comparing the magnitude relationship between the contents of the control register 10 and the contents of the control register 11.
If the contents of the control register IO are smaller than the contents of the control register 11, a carry of θ'' is output; if the contents of the control register 10 are larger than the contents of the control register 11. Outputs a carry of "l". The adder 5 is a 0 check circuit that calculates the difference between the contents of the control register 10 and the effective address register 8.The 0 adder 6 is used to calculate the difference between the contents of the control register 11 and the effective address 8. 9 indicates that the execution address is the PER start address and the PER based on the output of the adder 4, the length (instruction length or data length), the output of the adder 5, and the output of the adder 6.
It is checked whether the end address exists or not, and if it exists, the signal CHECK 't is set to "1". Signal CHE
When CK is busy by "1", a program interrupt occurs.

The conventional address comparison scheme of FIG. 1 operates as follows. When an instruction read event or main memory update event occurs when the PER mechanism operates and the execution conditions necessary for the program to be monitored are set, the address at that time. Compare the contents of control register 1o with the contents of control register 11 according to the mode, calculate the difference between the contents of control register 10 and the contents of effective register 8, control register 1
The difference between the contents of 1 and the effective address register 8 is calculated, and a check is performed based on the above calculation result and length.

In the conventional method shown in FIG. 1, the contents of the control register 10 and the contents of the control register 11 according to the address mode are compared in magnitude every time an instruction read event or a memory update event occurs, resulting in poor performance. It has the disadvantage that the value decreases by 0 minutes, and since the magnitude comparison between the contents of the control register IO and the contents of the control register 11 is performed using a special adder, extra hardware is required, which is uneconomical. The present invention obviates the above-mentioned drawbacks.

In a variable address mode computer which eliminates the need to compare the magnitude of a PER start address and a PER end address every time a predetermined main memory access event occurs, and eliminates the need for a dedicated adder for magnitude comparison. The purpose of this paper is to provide an address comparison method. Therefore, the address comparison method in the variable address mode computer according to the present invention has multiple types of Q address modes, and when a predetermined main memory access event occurs under a state where predetermined execution conditions are set. , the address handled by the main memory access event exists within the area defined by the program event recording start address specified in the first control register and the program Φ event e recording end address specified in the second control register. In an address comparison method that uses a pipelined address mode variable computer K> to check whether or not Then, based on the carry from the predetermined bit position of the calculation result, each address mode IIc program 9 event recording start address is compared with the event recording end address,
The results of these comparisons are stored, and when a predetermined main memory access event occurs under a state in which predetermined execution conditions are set, the contents of the control register 1, li I, and the contents of the control register 2, executed. Contents of address register Length of data handled by the above predetermined main memory access event.

Based on the type of address mode at that time and the memory content of the above magnitude comparison corresponding to the address mode at that time, the address handled by the predetermined main memory access event is determined by the log event. tlI whether it exists within the area defined by the recording start address and program/event/recording end address.
It is characterized by being able to read. Below, 1 shot ll1
1 will be explained with reference to the drawings. Figure 2 is a functional block diagram of one embodiment of the present invention.

Figure 3 Fi Wrap A, Round Check Fist Flow,
Figure 4 is a diagram showing the PER check @ flow.
In the figure, 12 is a working address register, 13 is an index e address register, 14 is a complement circuit, 15 is an address adder, 16 to 18 are AND circuits, and CO, 01, and 08 are latches, respectively. Note that the same reference numerals as in diagram #I1 indicate the same thing. When comparing the magnitude of the PER start address and the PER end address, the PER start address is stored in the working address register in 1&, and the PER end address is stored in the working address register. is stored in the index register 13. Registers 12 and 12 have a feather bit configuration. The address adder 15 also uses K for address calculation, but in the present invention, the 0 address adder 15 is also used as an adder to compare the magnitude of the PER start address and the PER end address. bit OO, bit 01=
1, Carry from bit □□□ is latched Co, C
They are set to 1 and 08, respectively. The AND circuit 16 is
When mode A is designated during addressing, the output of the 11% latch CO is inverted and output. AND circuits 17 and 184 perform similar operations. The output of AND circuit 16, 17, 18 is O
This output becomes the +WRAP AROUND signal. If this signal is “1”, the address is wrapped.
The tube shows that it is done around.

When the instruction read event or main memory update event is To-)9, selector 1 selects the contents of control register 11 according to the address mode, and selector 2 also selects the contents of control register 11 according to the address mode. Select content. The output of selector l is sent to adder 5, and the output of selector 2 is sent to adder 6.

Adder 5 calculates the difference between the sent contents and the contents of effective address register 8, and adder 6 also calculates the difference between the sent contents and effective address register 8. Based on the length, +WRAP AROUND signal, the output of adder 5, and the output of adder 6,
The address handled in an instruction read event or main memory update event is between the PER open 11 address and the PER end address.
Check whether W exists.

Figure 3 shows the wrap-around check 7μm1.0 The computer of the present invention executes in an instruction pipeline system, where D is the state where instructions are decoded, and R is the operand write address. A is a state in which registers such as index and base are read to determine the register contents, and A is a state in which the execution addresses of the first and second operands are determined from the contents of the read registers and an access request is issued to the storage unit.S Bl and B CK is a state in which the storage device is accessed using the obtained address; s it and Fs are states in which operations are performed using the obtained operand data; CK is a state in which the operand data is stored in the storage device; The state for checking data, W is the write state to various registers, RR is the result register where the operation result is stored, EAl to Em3 are the input registers of the address adder, CR10C0PY R11l:G is Control register 10; register that holds the bee, CR11C0PY
REG indicates a register that holds a copy of the control register 11, respectively. Although these registers are omitted in FIG. 2, they actually exist.

In Figure 3, the first 7-- CK, P in W state.
Calculate the ER start address and store it in register CRIOC
0PY Put in RKGK. In the next 7a-CK, W state, calculate the PICR end address and register CRI.
OC0PY RIGK 0th order flow OA, B1
CR10C0PY RIG and CRII in state
Perform subtraction of C0PYRIG, bits 00, 01...
Detects the medium from the OS and latches Co, C1, C8
write to. Here, if there is no carry, the address wraps around 0 Figure 4 shows the PER check flow 0 In Figure 4, BR is the base register, DB is the displacement register, R81 R83 to R83 indicate an interrupt state. PER check 70- checks whether the write address exists in the area monitored by control register 10 and control register 11 when a main memory update event etc. occurs, and if it is within the area. If so, a program interrupt is generated. The conditions for causing a program interrupt are as follows: (6), (EAR≧CR10LCH) AND (EAR>
CRIIL CH) address is greater than CRIO and less than CR11.

(b) (EAR≦CRI I LCIi) AND
(WRAPARROUND) Address is less than CRI 1 and WRAPARROUND
D〇guu (EAR<CRIO≦KAR+L) AND (
EAR≦CRI 1)・Add address KLINGTH is CRI O
bigger.

) (EAR<CRIO≦EAR+L)AND (
WRAP AROUND) WRAP AROUND and address LENGT
The value plus H is greater than CRIO.

(E) (WRAP AROUND) AND (The address is WRAPAROUND) The address is also WRAP AROUNDL, as is clear from the explanation that WRAP AROUND is 0 or more read from latches Co, C1, and C8 depending on the address and address. According to the present invention, it is not necessary to compare the magnitude of the PICR start address and the PER end address in each address mode every time a predetermined main memory access event occurs.

Also, there is no need to have a dedicated adder.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional address comparison method for checking whether there is an address to be handled in instruction read or main memory write between a PER start address and a PER end address, and 2I11 is an embodiment of the present invention. The functional block diagram of Figure 3 is the wrap around check 70-, Figure 4 is the PER check 7E! - is a figure showing. 1 and 2...Selector, 3...Complement circuit, 4...Adder. 5 and 6... Adder, 7... Complement circuit, 8... Effective address register, 9... Check circuit, 10...
...Control register, ll...Control register, 12.
...Working Address Register, 13... Index Address 0 Patent Applicant Fujitsu Limited Representative Patent Attorney Yobu Kyotani

Claims (1)

[Claims] The present invention has multiple types of address modes. When a predetermined main memory access event occurs under a state in which predetermined execution conditions are set, the address handled by the main memory access event is a program event designated by the first control register. In the address comparison method in a pipelined address mode variable computer that checks whether the program event specified by the recording start address and the second control register exists within the area specified by the recording end address, the address The difference between the content of the first control register and the content of the second control register is calculated using addition gs, and program event 9 recording in each address mode is performed based on the carry from a predetermined bit position of the calculation result. It compares the start address and the program/event/recording end address, and stores the results of these comparisons. When a predetermined main memory access event occurs under a state in which predetermined execution conditions are set, the contents of the first control register, the contents of the second control register, the contents of the effective address register, and the predetermined Based on the length of the data handled by the main memory access event, the type of address mode at that time, and the storage content of the above magnitude comparison corresponding to the address clarity mode at that time, the address handled by the predetermined main memory access event is determined. An address comparison method in a variable access mode computer, characterized in that it is checked whether or not the program event recording start address and the program event recording end address exist in an area defined by the program event recording end address.