JPS5844821A - Logical gate circuit - Google Patents

Abstract

PURPOSE:To quicken the operating speed without increasing power consumption, by providing a means for discharging a base storage charge of an output transistor (TR). CONSTITUTION:When a high level is applied to an input terminal 11, a current flowing to a resistor 1 flows to a base of a phase inverting TR22, a collector potential is decreased and a discharge TR29 is transferred from the interrupting state to the conductive state. In this case, the collector potential of the TR22 is lowered to cut off a level shift TR23. A stored charge of the base of a phase division TR24 is rapidly discharged to a discharge TR29 through a resistor 7 and that of an output TR27 is also to the TR29. Thus, the TR27 is transited to the cutoff state in high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to logic gate circuits, and in particular to saturated bipolar logic circuits including TTL (transistor transistor logic) or DTL (diode transistor logic).

FIG. 1 is a circuit connection diagram showing an example of a conventional TTL. 11 is an input terminal, 21 is an input gate transistor, 2
, 2 is a phase inversion transistor, 31 is a PN diode,
23 is a level shift transistor, 24 is a phase division transistor, 27 is an output transistor, 25 is an output buffer transistor, and 26 is a 'II level output transistor which is connected to the transistor 25 in Darlington to form an output buffer circuit. .

31.32.34 are PN diodes, 33 is S, BD
(Shirotki barrier diode), l, 2, 3,
4.5°6, 7.8.9 and 10° resistance. 1
2 is an output terminal, and vCC and GND are power supply terminals.

28 is a level shift transistor, 29 is a discharge transistor, level shift transistor 28° diode 3
2.33,34. A discharge circuit is constituted by resistors 7, 8, 9, and 10.

The current flows to the base of the phase inverting transistor 22, and the phase inverting transistor 22 becomes conductive.

At this time, level shift transistor 23 and phase division transistor 24 transition to a cut-off state.

When the level shift transistor 23 is cut off, a current flows through the resistor 3 to the base of the level shift transistor 28, and the level shift transistor 28 becomes conductive.A current flows through the diodes 23, 33, and 34, and the discharge transistor 29 becomes conductive, and at this time, the base accumulated charge of the output transistor 27 is transferred to the discharge transistor 2.
9 and resistor 8, and the output transistor 27 is cut off.

On the other hand, the charge stored in the base of the phase splitting transistor 24 flows through the resistor 7 and enters the cutoff state similarly to the output transistor 27. Therefore, the resistor 4 causes the collector of the phase dividing transistor 24 to rise at the power supply voltage Vcct. At this time, the transistors 25 and 26 of the off-buffer circuit become conductive, driving the load attached to the output terminal and increasing the voltage. Therefore, the potential of the output terminal is high (VCC2VBE"3
．． 5V: However, VB! i is the forward voltage between the base and emitter of the transistors 25 and 26).
The phase inverting transistor 22 is turned off.

Therefore, the level shift transistor 2231, the phase division transistor 24 and the output transistor 27 become conductive, while the level shift transistor 28, the discharge transistor 29 and the transistor 25.2 of the off-buffer circuit become conductive.
6 is in a cut-off state and a low level (approximately 0.5V) is output to the output terminal.
The following) appears and becomes 10# in positive logic.

This is so-called in-phase operation.

The required performance of such a logic gate circuit is low power consumption and high speed operation. %, and the drive current of the output transistor 27 is also large, so the operation of the discharge circuit to quickly release the base accumulated charge has a large effect on the performance of conventional circuits. are doing. □ During the propagation delay time when the input changes from high level to low level and the output changes from high level to low level, the phase inverting transistor 22 is turned off, the level shifting transistor 23 is turned on, and then the phase splitting transistor 24
If the transition to the cut-off state of the discharging transistor 29 is delayed when the output transistor transitions to the conductive state, the base current to the output transistor 27 will flow to the discharging transistor 29, and the discharging This has the disadvantage that the output transistor cannot be turned on until the transistor 29 is turned off, and as a result, the propagation delay time for the output voltage to go from high level to low level becomes longer.

On the other hand, during the propagation delay time during which the output transitions from a low level to a high level, the discharging transistor 29 must become conductive as quickly as possible to absorb the charge accumulated in the base of the m-power transistor 27. When the phase inversion transistor 22 is in a conductive state and then the level shift transistor 23 is in a cut-off state, the level shift transistor 28 is brought into a conductive state by the resistor 3, and then the discharging transistor 29 is brought into a conductive state. However, in order to speed up the time during this period, it is necessary to reduce the resistors 3 and 9 to increase the power consumption and to speed up the conduction state of the discharge transistor 29.

The discharge transistor 29 is connected from the collector of the level shift transistor 23 to the level shift transistor 28 to drive the discharge transistor 29.
The conduction and quick-break operations become slower.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a logic gate circuit with a simple configuration, improved propagation delay time, and low power consumption.

According to the present invention, an input gate circuit consisting of a diode or a transistor, a transistor for phase inverting the output of the input gate circuit, an output whose base is connected to the emitter of a toster for level shifting the collector output of the phase inversion transistor, transistor name and a logic gate circuit comprising an output buffer circuit inserted between the collector of the phase splitting transistor and the output transistor, the base accumulated charge of the output transistor is controlled by switching means controlled by the emitter current of the phase inverting transistor. A logic gate circuit is obtained which is characterized in that it is provided with means for discharging.

Next, the present invention will be described in detail according to embodiments thereof with reference to the drawings.

FIG. 2 is a circuit connection diagram showing an embodiment of the present invention.The difference from the conventional circuit shown in FIG. 1 is that the discharge circuit has a resistor 9. Diodes 32° 33, and 34.
This is achieved by omitting the level shift transistor 28 and the level shift diode 31 and instead connecting the emitter of the phase inversion transistor 22 to the base of the discharge transistor 29.

The logic operation is the same in-phase operation as in FIG.

The transient state will be explained.

When a high level is applied to the input terminal 11, the current flowing through the resistor 1 flows to the base of the phase inverting transistor 220, lowering the collector potential and at the same time transitioning the discharging transistor 29 from a cutoff state to a conduction state. At this time, the collector potential of the phase inversion transistor 22 decreases, so that the level shift transistor 23 is turned off. The pace accumulated charge of the phase splitting transistor 24 is rapidly discharged to the discharging transistor 29 through the resistor 7, and the pace accumulated charge of the output transistor 27 is rapidly discharged to the discharging transistor 29. Therefore, compared to the conventional circuit shown in FIG. The transition to the cut-off state of the output transistor 27 and the phase division transistor 24 is performed at a high speed to the extent that there is no delay in transitioning the discharging transistor 29 to the conductive state.

On the other hand, when a signal changing from a high level to a low level is applied to the input terminal 11, the phase inversion transistor 22 changes from a conductive state to a cutoff state.

At this time, the collector potential of the phase inversion transistor 22 is increased by the resistor 2. At the same time, the base potential of the discharging transistor 29 is lowered by the resistor 10, so that the time when the discharging transistor 29 is turned off is approximately the same time as or earlier than when the level shift transistor 23 is turned on.

Therefore, the current that drives the output transistor 27 does not leak to the discharge transistor 29, and the output transistor 27
The transition to the conductive state is carried out at high speed.

In this way, the output transistor 27 and the phase splitting transistor 240 absorb the charge accumulated in the discharging transistor 29, which switch to the conductive state or the cut-off state quickly without increasing the power consumption. It has the effect of increasing power and speed.

Furthermore, compared to the conventional circuit, four diodes and one transistor can be saved, so the structure can be simplified.

Although the above explanation has been made regarding a single-manufactured gate circuit, it goes without saying that an AND circuit can be constructed by using a multi-emitter transistor as an input, and the present invention can also be applied to such a case. do not have.

[Brief explanation of the drawing]

FIG. 1 is a circuit connection diagram showing an example of a conventional TTL, and FIG. 2 is a circuit connection diagram showing an embodiment of a logic gate circuit according to the present invention. 10- 1.2, 3, 4, 5, 6, 7, 8, 9.10...
・Resistance, 11... Input terminal, 12...
Output terminal, 21...Input gate transistor,
22... Phase inversion transistor, 23.28...
...Level shift transistor, 24...
Phase division transistor, 25...Output buffer transistor, 26...11# level output transistor% 27...Output transistor, 29
......tt transistor, 31, 32.34.
...PN Dio-1 (11- Police Officer 1)

Claims (1)

[Claims] an input gate circuit consisting of a diode or a transistor; a transistor that phase-inverts the output of the input gate circuit; a transistor that level-shifts the collector output of the phase-inversion transistor; a phase-dividing transistor whose base is connected to the emitter of the level-shift transistor; A logic gate circuit comprising: an output transistor having a base connected to the emitter of the phase splitting transistor; and an output buffer circuit inserted between the collector of the phase splitting transistor and the collector of the output transistor; 1. A logic gate circuit comprising: means for discharging charges accumulated in the base of said output transistor by means of switching means controlled by emitter current.