JPS5846680A - Memory element - Google Patents
Memory elementInfo
- Publication number
- JPS5846680A JPS5846680A JP56145328A JP14532881A JPS5846680A JP S5846680 A JPS5846680 A JP S5846680A JP 56145328 A JP56145328 A JP 56145328A JP 14532881 A JP14532881 A JP 14532881A JP S5846680 A JPS5846680 A JP S5846680A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- electrode
- semiconductor
- semiconductor thin
- memory element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は強銹電体記憶素子に係り、特に素子の微細化お
よび高速化に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a strong electric storage element, and particularly to miniaturization and speeding up of the element.
従来の強−電体記憶素子としては第1図(−の工うに強
酵電体基板1mの一方の面に半導体薄膜2aを被着し、
共通電極8、絖み出し′W11極5、および基板の反対
向に薔き込み11億番を形成したもの。As a conventional ferroelectric memory element, as shown in FIG.
A common electrode 8, a protrusion W11 pole 5, and a protrusion No. 1.1 billion are formed in the opposite direction of the substrate.
および第1図(−のように半導体基板2b上に電界効果
トランジスタを形成し、チャ/ネル部分の上に強I電体
薄[1bを形成して共通電極(ノース電*)BsWlみ
出し電極(ドレイン電極)5.および書き込み電極(ゲ
ート電極)4を形成したものがある・前者は強−電体の
厚さか厚い友めに分極ドメインか小さくできず、素子の
微細化か不可能であり、ま几後者は比較的微細化が容易
であるが、ソース、ドレインのAa!#Jf拡敢層6お
よびその両側面に形成される比較的大きなフィールド鍼
化膜7のために構造が複雑であり、微細化への制約があ
る。ま次両省において、薔き込み時の電流通路はg1図
1a) e (b)の矢印8で示されるように半導体領
域の横方向となり、抵抗値が高いために分極反転のスピ
ードが遅くなる。A field effect transistor is formed on the semiconductor substrate 2b as shown in FIG. (drain electrode) 5. and write electrode (gate electrode) 4. In the former, the polarization domain cannot be made smaller due to the thickness of the ferroelectric material, making it impossible to miniaturize the element. Although the latter is relatively easy to miniaturize, the structure is complicated due to the Aa!#Jf expansion layer 6 of the source and drain and the relatively large field acupuncture film 7 formed on both sides thereof. , there are constraints on miniaturization.In both cases, the current path during infiltration is in the lateral direction of the semiconductor region as shown by arrow 8 in Figure 1a) e (b), and the resistance value is high. The speed of polarization reversal becomes slower.
本発明の目的は前記のような制約を除き、は−化と高速
化が可能な素子構造を提供しようとするものであり、第
2図(−〜Aに基づいてその前値を貌萌する◎第S図鑞
−は本発明の構造を示す凶であり、絶縁体基板9よに査
き込み電極番、強妨電体薄NX1b1牛導体薄MXZ
as絶縁体薄膜lOお工び齋き込みt徳4t−積層し、
半導体薄膜2aの両端に絖み出し11極5を設けている
。The purpose of the present invention is to eliminate the above-mentioned limitations and provide an element structure that can be made faster and faster. ◎ Figure S - shows the structure of the present invention, and the electrode number is inserted into the insulator substrate 9, the strong conductor thin NX1b1 and the thin conductor MXZ.
As insulator thin film 10 Inserted t virtue 4t - laminated,
Protrusions 11 and poles 5 are provided at both ends of the semiconductor thin film 2a.
本発明の第lの特徴は前記のように強峰・電体を含む全
*g’a’累を薄層化し、分極のドメインサイズによる
制約を除き、構造を半縄比して素子の微細化を可能とし
、また蓄き込み電圧の印加力向を、@S図(mlの矢印
8のように膜間に−1として、分極反転のスピードを向
上させることである。The first feature of the present invention is to thin the entire *g'a' layer including the strong peaks and electric bodies as described above, remove the restriction due to the domain size of polarization, and make the structure finer by semi-roping. In addition, the speed of polarization reversal is improved by setting the applied force direction of the stored voltage to -1 between the membranes as shown by arrow 8 in the @S diagram (ml).
第3図(−およびlcjはそれぞれ8値偏号の“l“お
よび101に対応しfc記憶状態での各層の電荷密度±
Qを示す図である。半導体薄膜2a中の電荷密度および
その極性によって読み出し電極5間の導電率が決定され
、半導体薄膜がn型のときはマイナス電荷のとき導通、
プラス電荷のとき非導通となる・ことで、半導体薄膜2
aK@き込み電+fi4を直接積層すると、同電極に発
生する電荷の友めに半導体薄膜中の電荷は打消され、電
荷密度は第3図1bJ 、 lc)の点線で示した分布
1巌となり、読み出し電極間の導電率変化は惚めて小さ
くなる。そこで、本発明の第2の特徴は半導体薄n5t
=aと着き込み電@会との閾に絶縁体4Jil[10を
挿入し1fm紀の導電事変fjの低下、即ち読み出し出
力情号の低下を防ごうとするものである。Figure 3 (- and lcj correspond to "l" and 101 of the 8-value polarization, respectively, and the charge density of each layer in the fc storage state ±
FIG. The conductivity between the readout electrodes 5 is determined by the charge density in the semiconductor thin film 2a and its polarity; when the semiconductor thin film is n-type, it is conductive when it has a negative charge;
The semiconductor thin film 2 becomes non-conductive when it has a positive charge.
When the aK@loaded charge + fi4 is directly stacked, the charge in the semiconductor thin film is canceled out by the charge generated on the same electrode, and the charge density becomes the distribution shown by the dotted line in Fig. 3, 1bJ, lc). The conductivity change between the readout electrodes becomes significantly smaller. Therefore, the second feature of the present invention is the semiconductor thin n5t
An insulator 4Jil[10 is inserted at the threshold between =a and the incoming electric power to prevent a decrease in the conductive event fj in the 1fm period, that is, a decrease in the readout output information.
本発明の纂8の41F黴は実施賭様の一つとして、本記
憶素子を後述するように24子構造とし、ワード−とビ
ット−のマトリックスでll成されるメそりプレーンの
構造を単#lIfとし、高密度fとを計り、メモリープ
レーンとしての動作スピードを向上させようとするもの
である。The 41F mold in Part 8 of the present invention is implemented by forming the present memory element into a 24-child structure as described later, and by forming a mesoriplane structure consisting of a matrix of words and bits into a single matrix. This is intended to improve the operating speed of the memory plane by measuring lIf and high density f.
つぎに本発明の−実り例をag2図−に基づいて銃明す
る。まず、清浄なガラス基&9に真空蒸層法によりAj
を約1000A被潰し、通常のホトエツチング技術によ
り書き込み電極4を形成する。Next, a practical example of the present invention will be explained based on the ag2 diagram. First, Aj was applied to a clean glass base &9 by vacuum evaporation method.
The write electrode 4 is formed by applying a crushing current of about 1000 A to a normal photoetching technique.
つぎに高周波スパッタリングにエリYM a O@を約
1μm被層し強錦電体771bとし、更に続けてプラズ
マOV Dfiによりn型のアモーファスシリコンを約
0,5μm被層し、半導体層2aとする。プラズマOV
Dにおける基板温蔵は通常のポリシリコ舎
ンを被着する場合より低く、約200℃とする。つぎに
lbおよび2aの肉薄Mをフロンガスによるプラズマエ
ツチング法により同一パターンに形成する。つぎに8i
0.を高周波スパッタリングによ参
り0.571 m被層し、ホトエツチング6技術により
絶一体層lOとする。最恢にUを真空4層伝により約1
000A被着し、ホトエツチング技術により誉き込み電
憾−お工び絖み出し電極5を形成する。Next, a layer of about 1 μm of ERI YM a O@ is applied by high frequency sputtering to form a strong brocade electric material 771b, and then a layer of n-type amorphous silicon is applied to about 0.5 μm by plasma OV Dfi to form a semiconductor layer 2a. . Plasma OV
The temperature of the substrate in D is about 200° C., which is lower than that when a normal polysilicon enclosure is applied. Next, the thin layers lb and 2a are formed into the same pattern by plasma etching using freon gas. Next 8i
0. A layer of 0.571 m was formed by high-frequency sputtering, and an absolutely solid layer 10 was formed by photo-etching 6 technology. Finally, U is approximately 1 by vacuum 4 layer transfer
000A is deposited, and an electrode 5 is formed using a photo-etching technique.
H8図は本発明による他の実施例を示すものであり、第
S図′(−における一方のdみ出し電極を一方の書き込
み電極に抵抗薄膜11で結び・他方の読み出し電極を他
方の書を込み電極に導体#膜で結ぶことKより2端子構
造とし、書き込みおよび読み出しを同一電極でできるよ
うにしtものである。本実施例は前記実施例で強鋳電体
薄膜と半導体薄膜を1川−のパターンに形成したところ
を別々にパターンニングし、一方の端に第8図のような
段差を設け、ここにTaのスパッタリングによる抵抗薄
膜を追加形成するだけで、前記の実施例と同様圧して本
実施例の素子を形成することができる。FIG. By connecting the embedded electrode with a conductor film, it has a two-terminal structure so that writing and reading can be performed using the same electrode.This example is similar to the previous example, in which a strong cast electric thin film and a semiconductor thin film are combined in one stream. By separately patterning the areas formed in the - pattern, providing a step at one end as shown in Fig. 8, and additionally forming a resistive thin film by sputtering Ta there, the same pressure as in the previous example is applied. The device of this example can be formed using the following steps.
この場合は抵抗薄膜1lFcより、舊き込みおよび続み
出しに若干の損失が加わるが184図のようるので構造
が極めて単純化され、メモリープレーンの高密、直化が
可能となる。従って配瀘装厘としての動作スピードも向
上させることか可能である。In this case, the resistance thin film 11Fc causes a slight loss in cutting in and extending out, but as shown in FIG. 184, the structure is extremely simplified and the memory plane can be made highly dense and straight. Therefore, it is possible to improve the operating speed of the filter.
なお、前記実施例では強肪電体薄換としてYMnOHt
−te用したが、BrMnO1sHoMnO@@TmM
n0@*Y b M o O@およびL u M n
O@ も同様に蘭用可能であるQIn addition, in the above example, YMnOHt was used as the ferroelectric material dilution.
-te was used, but BrMnO1sHoMnO@@TmM
n0@*Y b M o O@ and L u M n
O@ can also be used for orchid Q
M1図1a) −(b)は従来の構造、第2図(−は本
発明によるーSAh例、第8図tb+ e 4c)は本
発明の構成における電荷密度±Qの゛分布凶、第8図お
よび第4図は他の実施例を示す図である。ここでl−1
強酵電体基板、1bは強−電体#腋、21は牛導体薄膜
、sbは牛導体基板、8は共通電極、番は誉き込み電極
、5は絖み出し電極、6は高−縦波散層、7はフィール
ド酸化膜、8は4@込み電流の流れる方向、9はガラス
基板、10は杷赦坏薄膜、11は抵抗薄膜、12//i
ワード#5lllはピット−1l働は記tl素子、l
5#′iメモリーグレーンである。M1 Figures 1a) - (b) are the conventional structure, Figure 2 (- is the SAh example according to the present invention, Figure 8 tb+e4c) is the distribution of charge density ±Q in the configuration of the present invention, and 8 and 4 are diagrams showing other embodiments. Here l-1
1b is a strong electric conductor board, 1b is a strong electric conductor #armpit, 21 is a cow conductor thin film, sb is a cow conductor board, 8 is a common electrode, No. is a lead-in electrode, 5 is a protrusion electrode, and 6 is a high-wire conductor board. Longitudinal wave scattering layer, 7 is a field oxide film, 8 is 4 @ direction of flow of current, 9 is a glass substrate, 10 is a thin film of lint, 11 is a resistive thin film, 12//i
Word #5lll is pit-1l function is tl element, l
5#'i memory grain.
Claims (1)
の分極により咳半導体のキャリヤ濃”度を変化させる4
1錦電体記憶素子において、絶縁基板上に電極薄膜、強
酵電体薄膜、半導体薄膜、絶縁体薄膜および電極薄膜を
本記載の順序で積層するか、または本記載の逆の順序で
積層して形成したことを特徴とする記憶素子。 12)電極薄膜、強綽電体薄膜、半導体薄膜、絶縁体薄
膜および電極薄膜の積層補遺を有し、前記各電極薄膜を
誓き込み電極としstn記半導体薄膜に一対の読み出し
電極を設けた紀t!素子において。 一方の読み比し電極を一方の誉き込み電極に尚抵抗の薄
膜で結び、他方のdみ出し電極を他方の畜き込み電極に
低抵抗の薄膜で結び、両書き込み電極にLる8端子構造
とし九ことを特徴とする記憶素子。 (3) 強誘電体lIIIM7&がYMo (J @
* lii r Mu U @ * HnMn O@
TenMn0@*YbMn0@iたはL u Mn U
@ のうちの一つの薄膜であることを特徴とする特
許d#求の範囲第1項または第2項記載のmlj素子0
(4)、半導体薄膜がアモーファスシリコン薄膜である
ことを特徴とする特i¥Fii*求の範囲第1項または
第2項記載の記憶素子。、[Claims] (1) Bringing a ferroelectric substance and a semiconductor into @ contact, and changing the carrier concentration of the cough semiconductor by polarization of the ferroelectric substance 4
1. In a brocade electromechanical memory element, an electrode thin film, a fermented electrolyte thin film, a semiconductor thin film, an insulator thin film, and an electrode thin film are laminated on an insulating substrate in the order described herein, or in the reverse order of the present description. A memory element characterized in that it is formed by. 12) A device having a stacked layer of an electrode thin film, a strong electrical conductor thin film, a semiconductor thin film, an insulator thin film, and an electrode thin film, each of the electrode thin films being used as an electrode, and a pair of readout electrodes provided on the stn semiconductor thin film. T! In Motoko. One reading comparison electrode is connected to one of the input electrodes with a thin film of resistance, the other d extraction electrode is connected to the other input electrode with a thin film of low resistance, and both write electrodes are connected to 8 terminals. A memory element having a structure characterized by nine things. (3) Ferroelectric lIIIM7& is YMo (J @
* lii r Mu U @ * HnMn O@
TenMn0@*YbMn0@i or L u Mn U
The mlj element 0 described in item 1 or 2 of the scope of patent d#, characterized in that it is a thin film of one of the following:
(4) The memory element according to item 1 or 2, characterized in that the semiconductor thin film is an amorphous silicon thin film. ,
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145328A JPS5846680A (en) | 1981-09-14 | 1981-09-14 | Memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145328A JPS5846680A (en) | 1981-09-14 | 1981-09-14 | Memory element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846680A true JPS5846680A (en) | 1983-03-18 |
| JPH0145750B2 JPH0145750B2 (en) | 1989-10-04 |
Family
ID=15382619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56145328A Granted JPS5846680A (en) | 1981-09-14 | 1981-09-14 | Memory element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5846680A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02239652A (en) * | 1989-03-14 | 1990-09-21 | Toshiba Corp | Semiconductor device |
| WO1996029742A1 (en) * | 1995-03-17 | 1996-09-26 | Radiant Technologies, Inc. | Improved non-destructively read ferroelectric memory cell |
| US5955213A (en) * | 1995-08-25 | 1999-09-21 | Tdk Corporation | Ferroelectric thin film, electric device, and method for preparing ferroelectric thin film |
| WO2003058723A1 (en) * | 2001-12-28 | 2003-07-17 | National Institute Of Advanced Industrial Science And Technology | Organic thin-film transistor and manufacturing method thereof |
-
1981
- 1981-09-14 JP JP56145328A patent/JPS5846680A/en active Granted
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02239652A (en) * | 1989-03-14 | 1990-09-21 | Toshiba Corp | Semiconductor device |
| US5521417A (en) * | 1989-03-14 | 1996-05-28 | Kabushiki Kaisha Toshiba | Semiconductor device comprising a non-volatile memory formed on a data processor |
| WO1996029742A1 (en) * | 1995-03-17 | 1996-09-26 | Radiant Technologies, Inc. | Improved non-destructively read ferroelectric memory cell |
| US5578846A (en) * | 1995-03-17 | 1996-11-26 | Evans, Jr.; Joseph T. | Static ferroelectric memory transistor having improved data retention |
| EP0815596A4 (en) * | 1995-03-17 | 1998-06-03 | Radiant Technologies Inc | IMPROVED NON-DESTRUCTIVE FERROELECTRIC MEMORY CELL |
| US6225654B1 (en) * | 1995-03-17 | 2001-05-01 | Radiant Technologies, Inc | Static ferrolectric memory transistor having improved data retention |
| US5955213A (en) * | 1995-08-25 | 1999-09-21 | Tdk Corporation | Ferroelectric thin film, electric device, and method for preparing ferroelectric thin film |
| WO2003058723A1 (en) * | 2001-12-28 | 2003-07-17 | National Institute Of Advanced Industrial Science And Technology | Organic thin-film transistor and manufacturing method thereof |
| US7138682B2 (en) | 2001-12-28 | 2006-11-21 | National Institute Of Advanced Industrial Science And Technology | Organic thin-film transistor and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0145750B2 (en) | 1989-10-04 |
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