JPS5848149A - Fault detection system of multiprocessing system - Google Patents

Abstract

PURPOSE:To stabilize operation by measuring the time when a signal transferred between LSI controllers is interrupted or outputted for a long time, and then outputting a reset signal to the controllers if said fault does recover even when a specified time elapased. CONSTITUTION:When a system becomes abnormal and a subordinate controller 2 does not output a transfer pulse TP2, a flip-flop 4 is not reset and the output of an AND gate 7 is generated continuously, so a counter 9 goes to a prescribed value to generate a reset signal RE. If the output period of the transfer pulse TP2 is long, the output of an AND gate 8 is inputted continuously to an AND gate 10, so the sum of the output periods of the AND gates 7 and 8 exceeds timer time and the counter 9 counts up to the prescribed value to generate the reset signal RE. Then, a main controller 1 returns to its initial stage once the reset signal RE, thereby repeatedly performing the processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention detects when a plurality of LSI control devices become unable to be coupled due to disturbances such as noise or static electricity, and automatically restores the LSI control devices.

In recent years, the control devices of devices have been integrated into integrated circuits to perform sophisticated control, but especially recently, as devices have become multi-functional, one control device is no longer sufficient, and multiple devices are installed in parallel to distribute functions and link with each other. Increasingly, people are now able to operate one device while at the same time.

For example, in vending machines, in addition to conventional sales control, price display and
Additional functions such as sales aggregation and equipment failure detection are becoming desirable, and for this reason, 118-manufacturing control devices are being replaced with two.
In recent years, the main control section has been installed in parallel to control sales, and the sub-control section has been configured to set sales prices and control the additional functions mentioned above.

Figure 1 shows the signal transmission and reception between the two r and Sx control devices, and the main controller (
1), when sending data from the data bus (3) to the sub-control device (2), outputs the data signal after outputting the negative transformer 7-te pulse TP1, and the sub-control device (2) outputs the data signal. When data is taken in, a negative transfer pulse TP is outputted to mutually confirm the data and transfer the data.

However, in such a multiprocessing system, if disturbances such as noise or static electricity occur, the function may stop or the program may go astray, resulting in malfunction or failure of the system.

In view of the above points, the present invention detects the interruption of signals sent and received between control devices or the appearance of signals for a long period of time to detect abnormalities in the system due to the above causes.

The present invention will be described in detail below, but in this example, the trans-edge pulse T? ,
This shows a case where a system abnormality is detected based on the state of the system.

3rd v! In J, (4) is a flip-flop circuit,
(5) is an AND gate into which E and TP, which are inverted signals of TPI, and the q output of circuit (4) are input; (7) is an inverted signal of TP, i and 7 AN in which the q output of the flip-flop circuit (4) is input 1:1.
D gate, (8) is TP, and Furi, Puf p, P circuit (
The first output of 4) is the input signal. The ANI) gate (5) and AND gate (6) are connected to the set input side S and reset input side R of the flip-flip a and block circuit (4), respectively, and are reset by the output of It is configured to count the black pulses OP introduced from the gate α1 and output a reset signal R1 when a predetermined value corresponding to the timer setting time is counted.

In the above configuration, the 7 lip-flop circuit (4) is normally reset, and the main controller (1) outputs a negative pulse TP.
, the sub-control device (2) outputs a negative pulse T
Since P2 is not output, an output is obtained from the AND gate (5), and the PfP circuit (4) is set and the counter (9) is reset. Then, the Q output of the flip-flop circuit (4) and the TP are connected to an AND gate (7
) is obtained through the OR gate 0υ and introduced into the kMD game)(11), so the counter (9) is
Count the clock pulses OP input through the gate a value. After outputting TP, the main controller (1) then outputs a data signal, and when the sub controller (2) takes in the data and normally outputs TP, to the main controller (1), AN
An output is obtained at the D gate (6) and the Furi, Pufre, Puri circuit (4) is reset. Therefore, Mu MD Gate (7)
Although no output can be obtained during TP, the page output of the flip-flop circuit (4) is activated by the AlID gate (
Since the output is obtained in 8), the output is continuously introduced to the iD gate member from the OR gate aυ and the counter (
In 9), Taro and Coupals OF are introduced even during the generation period of TPs'. Then, at the stop of TP, Muka D gate (8
), if no output is obtained, the counter (9) is cleared,
The input of the pulse OF is prohibited and the timer operation ends.

However, as shown in the timing chart of Fig. 4, if an abnormality occurs in the system and the sub-control device (2) cannot output TPmt-, the Furi, Bufp, and P circuits (4) are not reset and the A11D gate (7) Since the output continues, the counter (9) counts a predetermined value (ie, the timer exceeds one hour) and generates a reset signal. Also, as shown in the timing chart of Fig. 5, the sub-control device (2)
P, but if the output period is long due to an abnormality, the output of AlI3) gate (8) will continue to be input to the AID gate α, so the output period of the MD gate (7) and the following (The sum of the output periods of the AND gate (8) exceeds one hour of the timer, the counter (9) counts a predetermined value and generates a reset signal R1. Then, the main controller (
1) returns to the initial state when the reset signal RE is generated and repeats the process again.

The above-mentioned abnormality detection circuit according to the present invention may be formed as an external circuit between the control devices or formed inside the main control device, but if the main control device is configured with a microcomputer, it may be formed by program control. This can also be achieved by monitoring the TPs from the sub-control device through appropriate interrupt processing, and upon detecting an abnormality, jumping to the start address of the program and repeating the operation again.

According to the present invention described in detail above, the transmission and reception of signals between the L+3 control devices is monitored, and when the signal is interrupted or output for a long time, the time is measured, and if the signal does not recover after a certain period of time has elapsed, This outputs a reset signal to the control device as an abnormality, thereby stabilizing the operation of equipment configured with control devices installed in parallel.

[Brief explanation of drawings]

Fig. 1 shows the transmission and reception of signals between L8 machine control devices installed in parallel, Fig. 2 is an operation timing chart, Fig. 3 is an example of a circuit according to the present invention, and Figs. 4 and 5 are operations in the event of an abnormality. A timing chart is shown. (1)--Main controller, (2)--Sub controller, (
4)...Arippu circuit, (9)...Counter. patent applicant

Claims (1)

[Scope of Claims] In a multiple gastric processing system in which LIFI& integrated circuit control devices are arranged in parallel and mutually exchange signals to operate devices, the first control device is connected to the second control device. If data is output after outputting the first signal to the device, and the second control device does not generate the second signal by taking in data after a predetermined time after the first signal is generated, or Even if the second signal is generated, if it does not disappear at a predetermined time point, it is determined to be abnormal and is reset to the first control device. This is an abnormality detection method for the multiplex system, which is characterized by introducing a digital signal and repeating the process again.