JPS5848251A - Information processing system - Google Patents

Abstract

PURPOSE:To realize an automatic reproduction of the video information accordant to an educational schedule, by recording each information segment with different distances shifted from an end of each track and obtaining a reproduction data with high reliability. CONSTITUTION:A program or data which is treated by a computer 3 is written and read with a video signal recorder/reproducer using a video tape. In this case, the same information segment is recorded to each of plural consecutive tracks A-C of a video tape which are formed with each field of the video signal. The different delay degress 1-3 are given to each of the same information segment from an end of each track to perform the recording. In such way, a data having high reliability can be extracted by using a majority logic which detects the coincidence between two data among three ones in the reproduction mode.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system comprising a video signal recording/reproducing machine using a tape-shaped recording medium and a computer, and in particular, a video tape recorder and a microcomputer 7 are combined to record on a magnetic tape. Program information is transferred to the microcomputer! The VTR's reproduction mode is controlled based on this program information.
It is most suitable for use in the TR control system.

An educational system using VTRs has been introduced into school education. In such a system, there is generally a large amount of time required to operate the VTR to reproduce necessary video information in accordance with the educational schedule, creating a heavy burden on the educational system.

In view of this problem, the present invention provides an educational system that combines a microcomputer type computer and an Eirin signal recording and reproducing device such as a VTR, so that the Eirin information is automatically played back according to the educational schedule. Its first purpose is to establish For this purpose, the present invention overlays each of a plurality of continuous tracks of a tape-shaped recording medium formed for each field of a video signal with the same information segment in order to reduce information reading errors. At the same time, each of the information segments is recorded at a different distance from one end of each track.Embodiments of the present invention will now be described with reference to the drawings.

In the VTR control system of this embodiment, Video Chi! The V-deo signal and the desegment information for the CPUK in the evening are recorded on the upper video track, and at the time of playback, the V-deo signal on the video tape is played back based on the program information on the tape. There are trivial configurations to control aspects.

Further, address information is recorded on each track in order to search for the V video source recorded on the tape.

Such a VTR control system can be installed, for example, in an educational system at a driving school.

FIG. 1 is a tape diagram showing information recorded on a video tape (1) that is inserted in this system.

Video sources (1) are divided into video sources S, S, . . ., classified according to the student's level. Nine of these video sources KIII are used to control the system control fcr grams Pip, , p, -...,...
... has been written. These programs are micro*y fs--fi ni-k"gtL," the microcombiner performs operations according to the program of the user,
This allows the control of the entire system.

Each program includes a program for asking questions to students, and a program for searching and reproducing necessary information in response to the students' answers to the questions (manual key operations). In particular, for the first quadrogram P, other programs Pa −Pa ・” ・・
・Address information on the tape is written, and the first
These address data are memorized into the micro combiator when the digital data is loaded into the micro combiator. A search for necessary information is performed based on the address data.

FIG. 2 is a pull diagram of the entire VTR control system.

VTR (2) is! The microcomputer (3) takes in the program written in the programmable device of the VTR (2), and the microcomputer (3) is programmed based on this program again. VTR
(2) Controls the operation.

As is well-known, the microcombinator (3) is the CPU (4).
) (central processing unit), ROM (5 to data bus (7) that connects RAM (6) and this controller) L address data (
8) I am prepared. An I10 interface circuit αυQ3 is provided which connects the microcontroller (3), an external key input device (9) and a printout device Ql. The VTR (2) is connected to a microcomputer (2) via an I10 interface circuit 0 with an extension m-
It is combined with 31 CPU (4), ROM (58 RAM (6).
R can be used without modification.

FIG. 3 is a plan view of the tape showing the tracks/l turns on the video source (1). Each trunk C on the tape!
In iI, an address ae indicating the absolute address of the track is written in each shift blanking section. The tape necessary for the program and control is written with a synchronization signal added to the video signal section.

Figure 4 shows the address recorded on the videotape.

FIG. 3 is a waveform diagram showing a format of digital data such as a program. In this embodiment, the number of data recording pits in one horizontal section is set to 8 bits, and the microcomputer (3
) and the number of bits handled by the CPU (4).

As shown in FIG. 4, the data is FM modulated and recorded over an area of 40 μm in one horizontal section.

The PM-modified data @1m has a rising/falling transition within 1 bit, and the transformed data "om" does not have this transition.

FIG. 5 is a diagram showing the data writing format for each field. Each vertical line in FIG. 5 indicates each field Pt forming the raster of one field, and each scale horizontal line number is indicated. Address data is written over the 12th to 14th horizontal intervals (H) of the vertical blanking interval (V-BLK). Therefore, the address data is inserted into the no-signal period immediately after the direct synchronization signal, so it can be reproduced! II
There is no effect on m. Each address is 3 bytes < 8 bits x 3) data, but the first 2 bits are used as sync bits, and the third bit is used as a check bit for the address data. used. Therefore, the address data itself r! With 21 bits, it is possible to address tracks corresponding to a tape length of about 10 hours.

The sync bits are used to indicate the type of information on the track, and rooJ indicates normal video information, and "11" indicates groglem information.

D on the videotape (1) in Figure 1 is the gram insertion section P.
* -Pa... is the video information recording section S
After the process is completed, program data is written at intervals of approximately 62 fields as shown in FIG. In this 62-field section, a 128-byte O-program code is written in the 57th H to 184th H of each field. By recording this closing meederogram, the recording circuit of the VTR (2) is prepared to be able to record actual program data easily and quickly.

In the field V where the program code is written, a,
Sync I on g57H? Since the turn FF (all sync/middle turn) is FM modulated as described above during writing, it is recorded as a rectangular wave signal of approximately 200 KHz and 8 cycles.

The program code is divided and written into multiple tracks of 128 bytes each, but if there is a reading error in one trunk, it will be read and the entire nine-day program will become invalid.
The same program code is written to each of the two consecutive TRATJs. Therefore, an identification code FNrooJro1Jr02J for identifying these three tracks is written in the 5811Kti next to the sink/arm turn FF.

At 59.60H following the identification code, there is a store address indicating the start address of the RAM in order to store the program in the RAM (6) of the microrompiator (3).
Address data SA is written. Furthermore, No. 61.62H
0CRC: t-do is written to k because of the store address data 8A12) erroneous detection and 1 correction of 0.

After the CRC code, fO is written in one track.
Data indicating the duram length is written, and then the 64th H~
A 128-byte program code is written over the 191H. This program code constitutes a part of the entire program (for example, 1 byte). Next to the prog 2 code is the CRC code (No. 192.1931
) is added, and the recording of a series of program data ends.

FIG. 6 is a diagram showing the tracks of the log area on the tape. As mentioned above, three tracks 00.0
1.02, the same 128-byte program segment is continuously written to form one program segment p1. and multiple fO/Tsugo Pt-P Yuki,
ps... there is one 7'o Gutum block P! It constitutes l. One grogram is 256
It has a length of bytes to IK, + bytes, and in the case of 256 bytes, it is divided into 128-byte segments and written into a total of six tracks, three tracks each. If t is 1 byte, it will be written to 24 tracks.

When reading program data, use the tzu program.
The first track of the segment (identification code r00J) is read. If the reading error is Nagari 9, then the 21st. Reading of the same grogram written in the third track] is not carried out, if there is a, the second track (code r01J
) program code is executed. [2] If there is another error in the rack, please check the third track (code r O' 2).
J) reading is performed.

If there is an error in reading up to one program block, part of the program will be lost and the entire program block will be invalid. Therefore, as shown in the tape plane iK of FIG. 7, one program block Pn and the same program block Pn'*Pn' are written in nine adjacent areas.

If in one glogram block P turtle, P a/
If an error occurs in the program segment Pn', the tape is rewound and program block Pn' is read. Further, if reading becomes unnecessary in this fa block Pn'-, rewinding is performed again and the next program block Pn' is read.

Figures 8A and 8B show damaged Qi! 8A is a partial plan view of
In the four fields (tracks), there is a high possibility that a read cine quality will occur in the same horizontal sections indicated by black circles.

Nine! In Fig. 8B, reading defects occur in the same horizontal section over a considerably long field y due to a flaw r4 in the tape longitudinal direction that occurs in the tape running system. In the case of e, as shown by black circles, there are fields P in which KQ-take cine-hiki occurs and fields in which it does not occur.

In addition, the following case must be assumed as a 9 defective reading. That is, within one field,
If there is a time when two or more bytes (or more than two horizontal sections) are read, the defective bytes may occur continuously in the same horizontal section over about three fields. This data with multiple read failures covers multiple bits, mb
It must be treated as missing data that cannot be corrected (data completely dropped out); however, it is highly unlikely that two or more consecutive bytes of data will occur in the same field.

Taking this condition into consideration, in this embodiment, as shown in FIGS. 9A to 9C, each data is recorded with a shift in three consecutive tracks (identification code r00Jr01 Jr02J) in which data of the same content is recorded. Even if read cine traversal occurs in the same horizontal section on three or more tracks due to the following operations, the probability that the same data will be defective is extremely low. Therefore, it is possible to extract extremely reliable trace data using majority logic that detects a match between two out of three data during playback.

Next, writing K of video information and program information will be explained. Figure 10 shows microphone 4-con, male eta (3) I
10 is a block circuit diagram of the data write circuit that is connected to the interface circuit f131, and FIG. 11 is its operating waveform diagram.

On the input terminal surface in Figure 10, there is a recording specification on the tape (1).
! iv video signal a signal is emitted. This V-deo signal a is sent to the sync chip output circuit, where the leading edge level of the sync signal is clamped to a predetermined reference level. The synchronizing signal 5YNC (Figure 11) in the input video signal a is used as the run f and arm pulse required for the clamp operation, and this synchronizing signal is separated from the video signal a by a synchronization separation circuit a. It will be done. Clamped video signal line changeover switch C! It is sent to the synthesis circuit 4 via It, and further sent from the output terminal (2) to the VTR (2) IC shown in FIG.

The address data and program data to be recorded are transferred to the data bus (8) of the microcomputer C controller (3) in Figure 2.
It is sent to the I# line from ~ to serial converter 4, and after being converted to serial data b as shown in Figure 11F at ζζ, it is sent to the FM modulator (2) as shown in Figure 11G.
It is modulated into data C. The FM data C is sent to the synthesis circuit (2) through AND gate 4, where a synchronization signal is added, and then output to the output terminal (2).

9 parallel → serial conversion and FM modulation are performed using 4MH obtained from the clock line of microcomputer (3).
This is performed in synchronization with the z-th mark CK. In addition, the lock CKti is supplied to the frequency division and timing control circuit (2), from which the 1/10 frequency division clock CK1 (11th EB) necessary for FM modulation and the 1/20 frequency division clock CK2
(Fig. 11D) is sent to the FM modulator, and the signal (Fig. 11C) is sent to the FM modulator, and the 1720 minutes necessary for serial conversion is sent to the FM modulator (Fig. 11C). sent to. .

Further, in the frequency division and timing control circuit, a data area signal d shown in FIG. This data area signal d represents the section in which data is inserted within one horizontal section, and is sent to the FM modulator (2) in order to operate the FM modulator 94 in this section.

Furthermore, this data area signal d is sent to the microcomputer (3) via the buffer as an instruction signal to send the next r data when data writing to the VTR is completed.
) to the data bus (8). Na$P! Iku t1
The data of the computer (3) and the tapas (8) are supplied with a direct synchronization signal V-8 output from the period separation circuit a1 in order to create address data for two recording cards within the computer.
YNC is applied via a puffer.

The address data and program data to be recorded are FM modulated by <FM' modulation S- as described above, and then sent to the synthesis circuit 4 via the AND gate 4. Since the FM modulator is always operating in the section of the data area signal d in Figure 11, an output that is similar to data 10'' is formed even in the section with virtually no data.This is recorded as it is. Then, the discrimination from the original data "0" becomes regression.For this reason, ANDr-)4 is opened and closed to prevent FM modulation data from being recorded in the no-data section.-Andr- ) (2) is opened and closed based on the output of the R8 frit defrot connection 4. This 7 frit defrot f@ is !
A signal 80H obtained by converting the address data (address used in the computer) through the lines of the address bus (7) of the device (3) by the address decoder. ,81H(16
set and renotated according to the base number). When the above address data is transferred to the data bus (8) K from the microphone (3) K, the CPU
It is also the address information given from (4) to RAM (6).

The program data and address data sent from the AND gate (2) to the synthesis circuit @ are added with a synchronization signal and sent to the VTR (2) as a TV broadcast signal -1t. That is, as shown in FIG. 10, the synchronization signal 8YNC from the input video signal a from the outside is extracted in the synchronization/period separation circuit (II). It is also supplied as a clear signal to the conductor circuit.

The signal is sent to the sync tip clamp circuit (to) through a level-to-dance converter. This sync tip clamp circuit (to) K is given the same clamp potential as the sync tip clamp circuit a on the video input side described above. At 9t, the output of the Kunde circuit (to) is the first
As shown in FIG. 1H, the synchronization tip is clamped to the same level L as the video signal to be recorded. The output of this Kutunde circuit (to) is sent to the synthesis circuit @ through the changeover switch ALT-, and is added to the recording data eK as shown in FIG. 11I.

According to this recording method, the recording traces of the synchronization signal on the tape are completely aligned between the video recording section and the data recording section. Therefore, the recording operation of the VTR (2)a is stable, and the reproduction operation (4) is stable.

The changeover of the changeover switch is carried out by a toggle type switch 7 whose input is the output 82H (hexadecimal display) of the address decoder.
Controlled by the output of Yotsude (to). That is, when the Zedeo signal is outputted in 11-g.

In the 12th to 14th horizontal sections and the 275th to 277th horizontal sections, the changeover switch (to) is connected to the contact (20b) side, and a synchronization signal is added to the track address data. Further, when the program data is recorded, the changeover switch (to) is connected to the contact (20b) side about 32 fields before the recording field of the program data, as described above.

In the manner described above, the videotape (1) shown in FIG. 1 is created. All information recording onto the tape (1) is controlled based on the program of the micron viator (3). An example of the program is as shown in the flowchart of FIG. 12, for example.

In other words, Mike Tian first receives the vertical synchronization signal V.
-Waiting for the arrival of 8YNC, judgment 100 in Figure 12
When the arrival of V -5YNC is detected, then 300μ
Delay processing 101 is performed, address data is written (process 102), and then in judgment 103 the track identification code FN is written.
Make a determination.

If F'N-00 is used, delay processing 106t- is performed and the 9th
Writing program data as shown in the figure (process 107)
If it is FN-01, perform slow processing 105 and 106.
and write the program data with a delay amount of 2 as shown in FIG. 9B, and if FN=02, the delay processing 11104
- 106 are performed, and program data is written with a delay amount of 3 as shown in FIG. 9C. As a result, smooth recording is performed.

Address data and program data are written in the fourth
This is done in the data area of about 40# in the figure, so the opening and closing of andr-)■ in figure 10 is done in the data area of about 40# in figure 15.
It is controlled like a charade.

In other words, in judgment 11110 in FIG. CPU (4) to RAM
A command to send data 1 is issued to (6), and
is sent to the data bus (8). Along with this,
A signal 80H is output from the 7-dress decouple shown in FIG. 10, and data 1 on the data bus (83) is loaded into the serial converter (2).

Further, the signal 80H sets the 7-bit differential fgs, opens r-), and writes data 1. The writing period D1 of data 1 is determined by the following judgment 112.
This continues until it is detected that the data area signal becomes low level.

When the determination 112 is Y (yes), the next data 2 write period D2 is entered, and in the same manner as described above, data 2 is sent out, loaded, and the flip-flop is set in step 11115. After writing the necessary data,
In the process 115, the signal 81 is sent from the address decoder Zeng.
H is output, flip f70 is set to 1
8 When the writing of the field is completed, the process returns to judgment J1 and the writing of the next O field is executed.

Next, the playback control of the stretcher (1) in FIG. 1 will be explained.

Already mentioned (D like < Vrkf-7” (13Kt!, VTR (
210 Controls playback.
・is written. When the VTR starts playing, first the 1F program 2 program P1 is read out and taken into the RAM (6) of the microphone printer (3). In order to read the input data, an Of program is written in a ROM provided in the extended I10 interface circuit a3 of the personal computer (3) shown in FIG. ROM that stores this fixed 7”0/!9^
is initial low I and fftf.

FIG. 14 is a flowchart showing initial row closing. When the TS control system is started, the message information is sent to the printing device shown in FIG. Address reading] is performed.The read address check [123]
It is compared with the destination address where the gramgram is being written. The address of this first f program is the same for every tape.

If the comparison result with the target address is N (no),
In step 124, the VTR is rewinded at t9 and fast forwarded, and the first-first routine L1 is continued.

When the result of the judgment 123 is Y, the cueing routine ends, and in the process 125, the reading 9 and R of the first fvs gutum P1 are performed.
Writing to A M (6) is performed.

Figure 15 is a four-wheel circuit diagram of the data reading p circuit included in the I/Q4/Turface circuit of the microcombi board, and Figure 16 shows the program module interrupt operation for data reading in Figure 15. FIG. 17 is a time chart for explanation, and is a flow chart of this interrupt operation.

As shown in FIG.
The control signal RC of the remote control output line (to) of the micro amplifier (3) is supplied via the 4-run control circuit (to), fast forward, rewind, playback, and high speed playback. (Picture search) and other remote control controls are performed.

The monitor QIK signal is sent via the reproduction output/conditions switching circuit of the VTR (2). Video switching circuit (IIJ
K is the video signal Cv formed by the combinator
is supplied from the terminal, and the switching circuit Ql is controlled so that when there is no video output from the VTR (2), the display of messages, questions, etc. is performed based on the video signal CVK. Ru.

To read the data (address data 11.7"015)A data) from the playback output of the VTR (2) with the digital camera (3) and to store the necessary data.

first! An interrupt request (interrupt request) for reading data is made to the computer (3). Due to the ζ6 interrupt request, the operation mode of my 10=n♂eta (3) is changed to the program routine for reading the main program Th data? This is performed with the -direct synchronization signal V-8YNC in the 10th interrupt request reproduction signal e which is replaced by 1. That is, the reproduced signal of the VTR (2) is sent to the synchronization separation circuit 13, and the picture axis synchronization signal V- separated by
8YNC (Figure 16) is given to Inter 2 Det Control Circuit (Wealth). This inter 2 output circuit (b) 1 is composed of, for example, an R8 flip-flop, and by supplying V-8YNC to its set input, a low level interrupt request signal is generated at its Q output. IR, RBQ (FIG. 16B) are formed. Kom
The signal is applied to the terminal (to) of the microcomputer (3), and an interrupt request is made to the microcomputer (3).

As shown in the 70-chart of FIG. 17, as described above,
First, when the arrival of the direct synchronization signal V-8YNC is detected in judgment 160, an interrupt request is set in process 131. As a result, the monitor (3) executes the interrupt routine program in step 132, and the interrupt routine program cancels the zero interrupt for reading necessary data. In other words, the program is created so that the interrupt request is reset by the processing fljA155 at the point when the fetching of the necessary data is completed, and the interrupt request is canceled by this. An interrupt request reset signal ~IR, R8T is sent from the terminal of the microcomputer (3) to the interrad Φ tunnel circuit (incorporated), and this =
The fritz differential control circuit that constitutes the control circuit is reset, and as shown in FIG. 16B, when the interrupt 1 request signal returns to high level, the 0 interrupt request signal becomes high level, and the interrupt is disabled. is released and the primary interrupt becomes possible, and the program execution moves to the main mode (return by instruction 134 in Figure 17).
.

In the normal extended video reproduction section, as shown in FIG. 16 and 8, the address datum DR immediately after V-8YNC is read in the interrupt routine IR(a), and then the main program M is returned. In the data column recording section on the tape, after an interrupt request is made with the iii direct synchronization signal,
Entering the interrupt routine IR(e) in FIG. 16B), the main fa program MK returns when reading of the program data based on the interrupt fvx program is completed.

Next, FIG. 18 is a time chart illustrating the operation of the data reading circuit in FIG.
This is a flowchart explaining the operation of the pigeon.

At 9 o'clock when data is read, the reproduction signal of the VTR (2) (first
Figure 8) is Pedestal Kutsun f/Data Slicer Q7
), is processed at ζ, and sliced at level U of the Kg18 diagram, and FM data f (address data or program data) of the 18th diagram is extracted. The pedestal clamp uses the horizontal synchronization signal H-8YNC obtained from the synchronization separation circuit (Fig. 18B).
The clamp signal g obtained by delaying the signal by the delay circuit (2) until one port of the C video signal as shown in FIG. 18C is obtained.
It is carried out based on.

Ri2in f/Slicer Q? ) output faFM demodulator (4
The demodulated data h shown in FIG. 18E (@1' is high level and @01 is low level) is returned. In addition, FM
As mentioned above, the data f is a transmission signal with a self-clock, and based on this data f and the 4 MHz signal CK obtained from the microphone CI-N-T-Sonori party Tsukutwin, the FM Demodulator - Figure 18 PK shown in 8
Shift clock 1 for bits is reproduced. Demodulated data h and shift clock i are provided by a serial-parallel converter.
Sent to.

Demodulated data h at the rising edge of shift clock 1 at ζζ
are sequentially shifted into an 8-bit shift register and converted into a4 parallel data. The 8-bit/bit data j output from the converter IaF4 is applied to each line of the data bus (8) of the microphone a/video converter (3).

From the serial to Notzler converter in Figure 15.

- The data given to Tapas (8) is
It is taken into the RAM (6) of the implementer (3). It is synchronized with the output of the lift counter that counts the 8V bit shift clock 1 of the data acquisition Thai Dender Co., Ltd. in FIG. 18F. In general, when - serial to I4 serial conversion operations are completed, that is, when 8 bits of serial data is sent to the serial to /parallel conversion 41, nine converted parallel data are stored in the RAMK. Therefore, the Vt counter ■ is.

The timing output is configured to produce a timing output such as an 8-bit count of the shift clock. However, in the control system of this embodiment, data transmission is carried out using the line self-crossing method as described above, so if there is a dropout of a few bits in the data, 8 bits of data will be collected within one horizontal section. However, it may be difficult to import data. 'For this reason, in this embodiment, the C cut counter ■ is set to 8 V, and from its output, a 6-net signal kt is obtained, which rises at the 6-th voltage (j) and falls at the 9-th voltage shown in FIG. . This 6-bit signal is applied to a data bus (8)K via a tri-state buffer. This buffer so is! The output is brought into conduction by the read command signal RDK outputted to the terminal of the output terminal (3), and the output is normally open.

In the computer (3), data is read using the 6C cut signal k as a bladder. That is, the 19th
7vI-Char) Ex in the figure, it is detected in judgment 140 that the 6-bit signal k has changed from low level L to high level H, and after processing 141 with a delay of about 6.75 μm, processing 142 Data 1 within one horizontal section is read. The delay of 6.75 μm is provided in anticipation of the arrival of the 8th bit of data. According to this reading method, even if ♂ bit P lot out is ``2% 8 # bits within one horizontal section, a reading bladder is always formed as long as at least 6 bits of data arrive, and f- Evening capture will be held. Of course, this data is IRl) data.

As mentioned above, the same data is written in six adjacent tracks, so if it is determined that the data is incorrect, the correct data can be read from the first track or the next track. .

The C cut counter and the serial to/relay converter (to) output the delayed horizontal synchronizing signal g (Fig. 18 C
) is cleared by the delay signal g, thereby securing the data reading section R shown in FIG. 18GK. When a complete -&l'l dot is read, data is taken into the RAM at the positions of the arrows Mln to 'Wimg in the above-mentioned reading section.

When data reading for one horizontal section is completed, 7 in Figure 19
0- Chart Judgment 143. Processing 144°145-...
The data of the next horizontal section is read as follows. Incidentally, it may be the 5th bit WA or the 7th bit of the Thai data reproduction data that sets the 72nd bit for data reading.

The data read in this way is stored in a buffer memory in the micro-thumpier (3), subjected to an error check using a CRC code (YIIC), and written to the RAM (6). The CRC check is vulnerable to tape defects such as those shown in Figures 8A and 8B, and CRC checks are susceptible to tape defects such as those shown in Figures 8A and 8B.
In the majority voting method, which identifies storm data with a match of
If there is a read loss (data dropout), the rationale is weakened. In particular, one of the triplet 12
Even though the 8th byte data pull is read correctly, if both of the other two blocks are K[,
If a majority vote is taken, the result will be reading cine performance.

Therefore, in this embodiment, reading failures are reduced by using IA check based on CRC and majority logic as shown in FIGS. 2OA-20C.

In other words, the 1st and 2'1st tracks of the triple writing are checked for errors using CRCK, and if an error is detected in both of these checks, 3
A majority vote is taken to detect a match between two of the six pieces of data consisting of the data read in the 11th track and the data read the previous two times. - In Chard, tzu processing 150 reads 128/doite data in one field and writes it to the buffer memory. 6. Next, in judgment 151, CRC:ff- code added to the data detects an error. ,W
If Ashi is detected, where is it? Set the OK flag at 1152, and if there is no flag, go to 1115! Is S OK 7? Reset the data.

At the 211th track, as shown in FIG. 20B, the OK flag is first determined in judgment 160, and if it is set, in step 11161, the storm data of the first track in the buffer memory is stored in the memory (RAM). Transfer to (6). If the OK flag is reset, the same thing as the data reading and checking in the first track is performed on the data in the second track, that is, in step 162
Read 28 bytes of data and write it to memory,
Next, in judgment 163, erroneous code is detected using the CRC code, and OK7 ladders are set according to the detection result (processing 164).
Or perform a reset (step 11165).

Next, as shown in the 20th CIll, the OK flag is determined in judgment 170, and if it is set, the data of the 2nd track written in the memory in process 162 of FIG. 20B is checked. is valid data. OK
If the flag is reset, a process 171 reads one byte of data, and a decision 172 reads the data, which consists of this data and the corresponding data of the first track in the paratour memory and the corresponding data of the second track in the memory. 3
When a match is detected, the matched data is written into memory in process 173. This work of extracting good data by majority vote is performed for 128 bytes, and it is determined that all of the data has been completed. ] The reading of one two-person segment is completed. If judgment 1
If no match is detected in step 72, an error is displayed in step 175.

The VTR0 rewinds and proceeds to read another block on the tape in which the same program has been written.

When performing majority voting as described above, if a 1-byte overlap occurs while reading each 128-byte data, the data arrangement will shift after that, making it difficult to take a majority vote. In this embodiment, when reading the data, as described above, the 6 outputs of the cut counter shown in FIG.
At the rising edge of the pit signal, 7 pulses are raised to take in 1 byte data within 1 horizontal section.C%fh. Therefore,
When there are many bit V losses, the 79 signal due to the 6v bit signal may not stand, and one byte of data may be lost. Since the next data is stored in the memory area corresponding to this missing data, the data arrangement gradually shifts when missing data occurs.For example, data Ds
, DI-Da, the quintuple write trough 1. The following Table 1 situation can occur as the read data of OO, 01, 02.

Table 1 Track data 00 DI -Dm -Dsol
D,,Dh? 02 Dm-Ds,? In the table above, track 00 is read successfully.

Data D is missing in track 01, and data D is missing in track 02. Therefore, if the majority logic is applied to the read data of the three tracks shown in Table 1, it becomes difficult to execute it], or incorrect data may be regarded as correct data.

For this reason, in this embodiment, data acquisition using inter-bar software, which creates a 7 lag using the 6-bit signal, and data acquisition using software are used in combination. The fE2 sum of the loop that checks the rounding flag of data reading in judgments 140, 143-. in FIG. 19 is as follows.

LD C, 7N OP OP OP 0P IN Any (read) Set the C register k, for example 7g (hexadecimal number), then the 6-bit signal in the MSB of the M register is a sign bit, and this is 1 (negative). If so, the flag has been raised, and the 1st section 01 byte data is the 15th
It is transferred to the combiator (3) via the serial → /l parallel converter wheel shown in the figure.

Next, increment (INC) C increments the contents of the C register by +1, and in OR (OR) C, the MOB OR of the A register and C register is placed in the M register. If MOB is 0 (positive), jump to statement number 4jD12B and detect the 6-bit signal k()2da) again. If the flag is set, MOB in the A register becomes @1" and a 7-lag signal is detected. The detection loop was removed and four N0Ps were detected.
After a delay due to (Ration), an instruction (IN, M) to read data into the A register is issued. Note that the delay due to NOP is reduced to the delayed polishing process by processing 141, 144--k in Fig. 19, and during this time the microcontroller is
It waits for the arrival of the 8th bit after the flag of the bit signal is raised. When data has been taken in, checked, and transferred to memory, the preset value is put into the C register again.

If a bit dropout occurs and the flag is not set due to the detection of a 6-bit signal, the flag detection loop continues to operate, and each time this loop is executed, the contents of the C register are incremented by +1, so for example At the fourth time, 11jsB of the C register becomes @1m by carrying. Then, in the next ORC, "1" (negative, true sign) is entered in the MOB of the error register, so the detection and output loops are removed and data sales are performed. Therefore, even if a bit dropout occurs and a 6-pit signal is not formed, the data will be captured after a certain period of time, so it is obvious that data will be missing. Therefore, the majority logic will work effectively. be able to. That is, as shown in Table 2 below, even if there is erroneous data x, the data order does not shift, so it is difficult to extract good data by majority vote.

Table 2 Data 00 Da Da Dsol
Da In other words, if the execution time of one read flag detection loop is, for example, 7.25 μsec, it is 63.5 μsec (
Loop count) x 7.25 μ + (other execution time) 6.
If the time of 3.54s+7.25J1m or 63.5us(IH')+a is 9,
Data is captured even if the flag is wet. Then, when the next data is read, if the flag is set normally, 63.5-1+α
Data acquisition is performed before the time elapses. Konotot! i
The timer of the software that performs the above time measurement is synchronously combined (resynchronized) at the data acquisition timing of the 6-bit signal k with 7 lags. The time required for error checking, data transfer, etc.

(Other execution time) + (2X 7.25--) <
It is necessary to fill the tube to 65.5 μm. In other words, when a read drop occurs, data is deposited over a period of time of 65.5 μm+α, so the next read 11 operation results in 65.5 A.
In order to jump into the loop that detects the capture flag within 1, it is necessary to allow for a shorter time than 65-5 m minus twice the loop execution time. The execution time may be, for example, about 38 .mu.S. However, it is necessary to shorten the execution time of the flag detection routine f (process 140 in FIG. 19) as well as the allowable time for data reading.

(The following is a blank space, continued on the next page.) As described above, the present invention records the same information segment redundantly on each continuous track of the tape-like recording medium formed for each field of the Eirin signal. Since each of the same information segments is recorded at a different distance from one end of each track, scratches along the length of the tape can cause all the same parts of the same data written multiplexed on each track to be recorded. It is possible to prevent reading failures, and by performing majority voting to detect coincidence of two pieces of multiple-written digit data, extremely reliable reproduced data can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of a tape showing information recorded on a video tape used in the VTR control system of the present invention, and FIG. 2 is a block diagram of the entire VTR control system.
3E is a plan view of the tape showing the track pattern on the videotape, Figure 4 is the waveform showing the format of digital signals such as addresses and programs recorded on the videotape, and Figure 5 is the write format of data for each field. FIG. 6 is a diagram showing each track of the program writing area on the tape. FIG. 7 is a plan view of the tape to explain multiple writing of the program block. The figures are a partial plan view of a tape with damage to the data recording section, Figure 9 is a time chart for explaining the shifting recording of data, and Figure 10 is a data writing circuit included in the I10 interface circuit of the microcomputer. 11 is its operating waveform diagram, FIGS. 12 and 13 are flowcharts showing the control program of the microcomputer when writing data, and FIG. 14 is the initial loader program of the microcomputer when reading data. Figure 15 is a block circuit diagram of the data reading circuit included in the I10 interface circuit 1C of the microcomputer, and Figure 16- explains the program interrupt and interrupt operation for data reading of the circuit in Figure 15. 17 is a Q flowchart to explain this interrupt operation, FIG. 18 is a time chart to explain the data reading operation of the circuit in FIG. 15, and FIG. 119 is a flowchart to explain the data reading operation. Figure 20A~
@200 Figures are flowcharts for checking data reading in microcomputers. In addition, in the numbers used in the drawings, (11...
・・・・・・・・・・・・Video tape (2)...
・・・・・・・・・-VTR13；・・・・・・・・・
・・・・・・Microcomputer (4)・・・・・・
・・・・・・・・・-0PU(5)・・・・・・・・・・
・・・-ROM(6)・・・・・・・・・・・・・・・
RAMaS・・・・・・・・・・・・Track p
,,p,,p,...Program data 1)Ill)!
......This is a program segment. Agent Souvenir Katsu l Pine wood Shu Figure 11-374- Figure 12

Claims (1)

[Claims] In an information processing system in which programs or data handled by a computer are written and/or read and recorded using a video signal distribution/playback device using a tape-shaped recording medium, each field of a video signal is formed. The same information segment is recorded on each of a plurality of consecutive tracks of the tape recording medium, and each of the same information segments is recorded at a different distance from one end of each track. Information processing system 0 characterized by