JPS5851461B2 - Time division multiplex control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a time division multiplex control system, particularly a time division multiplex control system for transmitting data from terminals having different transmission speeds via a time division multiplex line.

Conventionally, in a time division multiplex network system, a time division multiplexer is provided and a plurality of multiplexers are connected to each other by a time division multiplex line.

In such conventional time division multiplexing multiplexers, the processing capacity of the multiplexer is not always sufficient, so when sending transmission information onto the time division multiplexing line, for example, the following It was being processed.

That is, for example, transmission requests from terminals A, B, C, . . . are assigned to predetermined time slots TA, TB, Tc, . . . on the time division multiplex line. It was supposed to be sent.

Therefore, the number of transmission requests is limited to tJ by the number of time slots on the time division multiplex line, and one or more time slots are required to transmit control signals such as line disconnection detection. If the slots are allocated in advance, the frequency of transmission of the control signal will be low, and the transmission efficiency will decrease accordingly.

The present invention is based on the above considerations, and is capable of efficiently transmitting data sent from terminals with different transmission speeds via a time division multiplex line, and also allows the transmission side to efficiently transmit data from terminals with different transmission speeds.
It is an object of the present invention to provide a system that can accurately notify a receiving side of how slots are allocated.

Therefore, the time division multiplexing control system of the present invention has a time division multiplexing device on the transmitting side, a plurality of terminals connected to the time division multiplexing device on the transmitting side via terminal lines, and a time division multiplexing device on the receiving side. A time division multiplexing control system comprising a multiplexing device and a time division multiplex line connecting the time division multiplexing device on the transmitting side and the time division multiplexing device on the receiving side, the method comprising: a time division multiplexing device on the transmitting side; The conversion device includes a priority selection means for selecting one data transmission request according to the priority order of the terminal when data transmission requests are sent from one or more terminals, and a data transmission request selected by the priority selection means. Channel allocation means for allocating an empty channel of the time division multiplex line to the transmission request; and sending the data transmission request selected from among the time slots of the empty channel allocated by the channel allocation means. a time slot selection means for selecting a number of time slots according to the transmission speed of the incoming terminal; a multiplexer for selectively connecting the plurality of terminal lines to the time division multiplex line; Transmission start instruction signal generating means for placing a transmission start instruction signal on the terminal line of the terminal that has sent the selected data transmission request when the transmission request is selected; a time slot counter; and a time slot counter. A scanner address table that stores multiplexer control information in a memory location determined by the number of
A scanner that reads the scanner address table using the contents of the slot counter as an address and sends the read multiplexer control information to the multiplexer.
address table read control means; and a multiplexer uniquely determined by the terminal using the time slot in each storage location determined by the respective number of one or more time slots selected by the time slot selection means. scanner address table write control means for writing control information, the receiving side time division multiplexing device comprising: a plurality of channel buffers;
a distributor for selectively connecting the time division multiplexed line to each of the plurality of channel buffers; a transmission start instruction signal detection means; a time slot counter; and a time slot number having the transmission start instruction signal. time slot number storage means for storing a time slot number; channel buffer selection means for selecting an empty channel' buffer when a transmission start instruction signal is sent via the time division multiplex line; A time slot table that stores distributor control information in a memory location determined by a number, and a time slot table that reads the time slot table using the contents of the time slot counter as an address and distributes the read distributor control information as described above. a time slot table reading control means for sending the selected channel to each memory location determined by each of the one or more time slot numbers stored in the time slot number storage means; - Time slot table write control means for writing distributor control information uniquely determined by the buffer.

This will be explained below with reference to the drawings.

Figure 1 shows a time division multiplexing network to which the present invention is applied.
An embodiment of the system configuration, FIGS. 2A and 2B are explanatory diagrams illustrating line allocation using a conventional time division multiplexing multiplexer and line allocation using a time division multiplexing multiplexer used in the present invention, and FIG. Embodiment FIGS. 4 and 5, which are explanatory diagrams conceptually explaining the time division multiplex control system, show the configuration of an embodiment of the transmitting side and receiving side of the present invention.

In FIG. 1, 1 is a time division multiplexer 7, a network system, 2-0, 2-1, 2-2, . . . are time division multiplexers iTDM, 3-0, 3, respectively.
-1, 3-2, . . . are node control units, respectively;
4 to 12 are channels, respectively, 13 to 16 are port adapters, 17 to 19 are terminals, 20 is a network control center and a terminal for monitoring the network status, and 21 to 26 are time division multiplex lines, respectively. , 27 to 30 represent husband and wife terminal lines.

Each time division multiplexer iTDM 2 has a respective node controller NC3, a channel CH1 and a port adapter PA.

The channel CH is connected to a time division multiplex line, whereby the time division multiplexers iTDM2 are linked together.

Port adapter PA also connects the terminal (1) via the terminal line.
0, etc.).

Each node control unit NC is provided with a node channel table (not shown), and a time division multiplex network
Information regarding the configuration of the system 1 is stored.

For this reason, for example, the time division multiplexer iTDM2
-1, if a transmission request occurs from the terminal 18,
The node control device 3-1 uses the node channel table to determine whether the destination of the transmission is to a terminal belonging to its own multiplexer 21 or to a terminal belonging to another multiplexer, for example 2-0. Judgment is based on the content.

For example, if the signal is for terminal 17 belonging to multiplexer 2-0, it is transmitted to multiplexer 2-0 via channel 7 and time division multiplex line 21.

Multiplexer 2-0 receives the above transmission on channel 6.

The data is then transmitted to the terminal 17 via the port adapter 13 and line 27 under the control of the node controller 3-0.

Needless to say, when transmitting from terminal 17 to terminal 18, the above route is reversed.

For example, if a line failure occurs in the line 21 as indicated by the X mark in the diagram, the failure situation is recorded in the node channel table in the node control unit 3 of each multiplexer and transmitted from the terminal 18 to the terminal 17. In doing so, multiplexer 2-1 transmits via channel 8 and line 23 to multiplexer 22.

Multiplexer 2-2 then transmits to multiplexer 2-3 via channel 10# and line 22, and multiplexer 2-0 transmits to terminal 1 via port adapter 13.
7.

FIG. 2A illustrates line assignment by a conventional time division multiplexer TDM, and FIG. 2B illustrates line assignment by an intelligent time division multiplexer iTDM according to the invention.

Note that the symbols 2-0, 2-1, and 21 in the figure correspond to those in FIG.
A conventional time division multiplexer corresponding to −0, a,
b, c,... and a', b', c/...
・represents transmission information.

Further, for the sake of simplicity, the time division multiplex line 21 is shown as having four channels CH8 to CH3.

In the case of line assignment using the conventional time division multiplexer TDM, as shown in FIG. 2A, terminal A sends transmission information a to terminal Z, terminal B sends transmission information When it is assumed that transmission information C is to be transmitted to terminal X, and transmission information d is to be transmitted from the terminal to terminal W, the procedure is as follows.

That is, a channel CHo using, for example, one time slot on the line 21 is allocated in advance for terminal A, a channel CH1 is allocated in advance for terminal B, and so on. Channel CH3 corresponding to
is assigned in advance.

Then, multiplexer 2-1' receives information a from terminal A.
is transmitted to multiplexer 2-σ via line 21 on channel CHo.

The multiplexer 2-0' transmits the information a transmitted by the channel CHo to the terminal Z as information from the terminal device A.

Therefore, in the illustrated example, terminals A, B, and C.

The number of D is limited by the number of channels on the line 21.

Furthermore, for control signals that occur relatively infrequently,
If one channel is fixedly allocated, one channel will be occupied by a control signal that occurs infrequently, further reducing transmission efficiency.

When using the intelligent time division multiplexer iTDM, as shown in FIG. 2B, empty channels (time slots) on the line 21 are sequentially found and transmitted information is assigned to them.

That is, when transmitting information d' and e' sequentially from terminal C to terminal
Information e' is transmitted using H3, and information d' is transmitted using free channel CH2.

To explain the invention in more detail, the time signal on the line 21
If a slot constitutes one frame as shown in FIG. 3A, for example, for a terminal line with a transmission rate of 50 BPS, as shown in FIG. 3B, there is a time slot T in channel CHo. .

, channel CH, and time slot T,...
..., time slot Tn-2 is assigned to channel CH (fl-2), time slot Tn-1 is assigned to channel CH (n-+), and the terminal line with a transmission rate of 100 BPS is assigned in advance. For channel CHo
time slots To and Tn for channel CH1, time slots T1 and Tn++ for channel CH1, etc.
Channel CH(n-2) has time slots T, 2 and T
2fi-2 and channel CH(.

-1), time slots Tn-1 and T2n-1 are respectively allocated in advance.

Also, if there are data transmission requests from multiple terminal lines at the same time, only the data transmission requests from one terminal line are valid according to a predetermined priority order, and data transmission requests from other terminal lines are placed on standby. .

Note that when transmitting data, the terminal sends out a data transfer request, and when a data transmission permission signal is sent, it sends out the data.

Furthermore, in the case of the present invention, an empty channel is assigned an empty state instruction signal, and a transmission start instruction signal is given to an empty channel allocated upon generation of a transmission request in place of the previous empty state instruction signal prior to data transfer. be granted.

Here, the empty state instruction signal may be, for example, a logic rOJ signal string, and the transmission start instruction signal may be, for example, a logic "1" signal string.

Hereinafter, the transmission start instruction signal of this logic "1" signal string will be referred to as a continuous Z code string.

Then, a so-called header is added to the allocated empty channel, and data is then transferred.

Therefore, on the receiving side, by looking at the reversal of the empty state instruction signal to the transmission start instruction signal within one frame, it is possible to judge which speed has been allocated based on the number of time slots inverted. The destination address can be easily recognized by assembling the inverted time slots and looking at the header.

FIG. 4 shows the configuration of an embodiment of the transmitting side of the time division multiplex control system according to the present invention.

In the figure, 31°, 32, ..., 33 are respectively terminal A,
B, ..., terminal line connected to N, 34,
35, ..., 36 are buffer devices, 37
is a priority selection circuit which, when transmission requests are generated simultaneously from multiple terminals among terminals A, B, . . . , N, prioritizes the transmission requests according to a predetermined priority 38 is a rewritable port address channel address correspondence table in which port addresses, that is, address information of terminals A, B, . . . , N are associated with channel address information. 39 is an address counter that specifies the address for the port address channel address correspondence table 38, and 40 is a A port decoder converts the port address information from the priority selection circuit 37 into corresponding transmission speed information, and 41 is a register that converts the port address information from the priority selection circuit 37 into corresponding transmission speed information.
A table 42 stores the transmission rate information converted and outputted by the decoder 40, and the channel address information, transmission rate information, and time slot address information are shown in FIG. 3B, for example. 43 is a scanner address table in which the above-mentioned time slot address information and multiplexer address information are stored in association with each other; 44 is a multiplexer; There are registers 54, 55, . 47 is a frame synchronization circuit that outputs a frame synchronization bit; 48 is a write/read control circuit that specifies the address for the scanner address table 43; 49 is a flag "O" detection circuit, 50 is a comparison circuit, 51 is a write control circuit, 52 is a continuous Z code string generation circuit, 53 is a transmission end monitoring circuit, 54
,55. . . . , 56 represents a register, 57 an OR gate, 58 an editing circuit, and 59 a modulation/demodulation circuit.

In the case of this embodiment, the transmission process is executed according to the following two processing modes.

That is, (1) terminals A and B. . . . A registration processing mode in which, when a transmission request is generated from N, an idle channel is selected according to the priority of the terminal and time slot address information corresponding to the selected idle channel is registered (11 ) The terminals A and B read out the time slot address information registered in the registration processing mode.

. . . , a transmission processing mode in which the transmission information sent from N is assigned to the time slot and transmitted.

(4) Registration processing mode (1) When a transmission request occurs from any terminal among terminals A, B, ..., N, for example, terminal A, the address information of terminal A, that is, the port address information takes priority. Selection circuit 37
is output from.

(2) At the same time, the address counter 39 starts an addressing operation for the port address channel address correspondence table 38.

When the address counter 39 starts the addressing operation, the flag bit information in the port/address/channel/address correspondence table 38 is read out.
For example, when flag bit information of logic "0" is read, the flag "0" detection circuit 49 sends a count stop signal to the address counter 39.

Here, flag bit information can be thought of as information that indicates whether the channel is currently in use or not.
Channels that are in use are given, for example, logic "1" information, while channels that are not in use are given, for example, logic "0" information.

(3) When a count stop signal is sent from the flag "0" detection circuit 49, the address counter 39 stops counting operation.

Then, the port address information, that is, the terminal person's address information, from the priority selection circuit 3T as described above is written in the port address information storage location corresponding to the flag bit information of logic "0" detected as described above.

In addition, the flag bit information of the above logic rOJ is set to logic “1”.
The flag bit information is inverted and the channel address information corresponding to the flag bit information is read out.

(4) While the above processes (2) and (3) are executed,
The port address information outputted from the priority selection circuit 37 as described above is converted into corresponding transmission speed information by the port decoder 40.

That is, for example, if the transmission rate of terminal A is 100 BPS, the address information of terminal A, that is, the port address information, is converted to the transmission rate information of 100 BPS.

The converted transmission speed information is then set in the register 41.

(5) The table 42 is indexed using the channel address information read from the port address/channel address correspondence table 38 as described above and the transmission speed information set in the register 41 as described above, and the channel address information as described above is indexed.
The time corresponding to the address information and the above transmission speed information
Slot address information is read.

That is, for example, in the case where an l frame is configured as shown in FIG. 3, the channel address information is information corresponding to channel CH1, and the transmission speed information is information corresponding to a transmission speed of 100 BPS. Then, time slots T1 and Tn+ shown in FIG.
The time slot address information corresponding to 1 and 1 is read out.

(6) The time slot address information read from the table 42 is written onto the scanner address table 43 along with the corresponding multiplexer address information.

Here, the multiplexer address information refers to terminals A and B.
, . . . , can be considered to be the address information of the gate in the multiplexer 44 corresponding to Information may be thought of as being carried over time division multiplexed links.

(7) On the other hand, if transmission requests are generated simultaneously from multiple terminals among terminals A, B, . . . , N, the priority selection circuit 37 selects the terminal with the highest priority among the multiple terminals. Outputs the port address information corresponding to the selected terminal.

Then, the registration process is performed in the same manner as the processes (2) to 6) above.

During this time, transmission requests from the remaining terminals are kept in a standby state, and for example, when the registration process corresponding to the above-mentioned terminal is completed, it may be considered that the registration process corresponding to the terminal with the next highest priority is executed.

(B) Transmission processing mode (8) When the port address information is output from the priority selection circuit 37, the continuous Z code string generating circuit 52 generates a continuous Z code string, and the terminal specified by the port address information Registers 54, 55, ..., corresponding to
The continuous Z code string is stored in 56.

Here, the continuous Z code string corresponds to the above-mentioned transmission start instruction signal.

(9) On the other hand, the counter 46 performs an addressing operation for the scanner address table 43, and
Multiplexer address information corresponding to each time slot is sequentially read out from the address table 43.

The multiplexer 44 is controlled by the read multiplexer address information as described above, and is controlled by the registers 54, 55 . Each terminal A, B, . . . is sent via . . . 56.

The transmission information from N is assigned to time slots on the time division multiplex line.

Of course, registers 54, 55 .・・・・・・、5
The time slot selected in the above-mentioned registration processing mode is assigned to the continuous Z code string stored in any of the above-mentioned registration processing modes.

00) When the transmission of transmission information from a terminal consisting of terminals A, B, . . . , N, for example, is completed, the completion monitoring circuit 53 outputs port address information corresponding to the terminal.

01) The port address information output above is
It is compared with the port address information read from the address-channel-address correspondence table 38 by a comparison circuit 50, and when a match is found, the counting operation of the address counter 39 is stopped.

Then, the port address information on the port address channel address correspondence table 38 is erased, and the flag bit information corresponding to the port address information is inverted from logic "1" to logic "O".

At the same time, the channel address information corresponding to the above port address information is
Read from the address correspondence table 38, and
The table 42 is accessed for address information.

02) On the other hand, the port address information output from the termination monitoring circuit 53 is converted into corresponding transmission speed information by the port decoder 40, and the table 42 is accessed via the register 41.

α3) The table 42 is accessed using the channel address information and the transmission rate information, and the corresponding time slot address information is read.

Then, the scanner address table 43 is accessed using the read time slot address information, and information that associates the time slot address information corresponding to the time slot address information with the multiplexer address information is obtained. will be deleted.

(14) The frame synchronization circuit 47 generates a synchronization bit for each frame.

The synchronization bit is connected to the OR gate 57 and the edit circuit 58.
A time slot is assigned by the multiplexer 44 as described above and added to the beginning of each incoming frame.

For this reason, the output of the editing circuit 58 is provided, for example, in a configuration as shown in FIG. 3A.

The output from the editing circuit 58 is then modulated by a modulation/demodulation circuit 59 and sent to the receiving side.

FIG. 5 shows the configuration of an embodiment of the receiving side of the present invention.

In the figure, 60 is a code detection circuit that detects the code of each time slot, and 61 is a counter, which is a code detection circuit 6.
0 detects and outputs a frame synchronization signal when continuous Z is detected in one time slot, counts the detection output, converts the counted value to speed, and outputs it, 62
is a time slot counter and sign detection circuit 60
is reset every time it detects a frame synchronization signal, counts up for each time slot, and gives number data to each time slot; 63 is an AND gate;
4 is a register that stores the number of time slots in which continuous Z has been detected, 67 is a buffer, 68 is a multiplexer, CB, CB2 . ... is the channel buffer, 65 is the channel buffer, speed, time,
This is a slot correspondence table (hereinafter referred to as a channel table), which allocates the time slot in which the flag information is detected and the speed detected by the counter 61 to an unused channel buffer, for example 69, and stores the time slot in the channel buffer 69 on the transmitting side. This shows something for accumulating data of assigned channels.

66 is a time slot channel buffer correspondence table (hereinafter referred to as a time slot table);
The channel buffers registered in the channel table 65 are arranged in the order of time slot numbers, and the data of the time slot number of the buffer 67 that is addressed from the time slot counter 62 and corresponds to the time slot number is stored in the stored channel. This is for specifying a buffer and selectively providing it to the channel buffer 69.

Further, 70 is an information identification circuit that identifies the data accumulated in the channel buffer 69, and 71SW is a switch group. When the information identification circuit γ0 identifies a data transfer destination address, the channel 72 (CHl) of that address
. . . CHn, ) to which the channel buffer 69 is connected.

In this embodiment, the reception process can be summarized as follows.

That is, (i) when a continuous Z code string is detected in the received data, the channel buffer CB1. CB2...
..., registers the time slot and speed corresponding to the selected channel buffer, and distributes data to the channel buffer.
(11) This is a data transfer processing mode in which allocated channel data is identified and the data is delivered to the channel to be transmitted.

(4) Time slot processing mode When information is sent from one channel, as described above, one
Flag information is placed in two time slots, and one
As mentioned above, each time slot within a frame must have one
The continuous Z code string is made to occur in only one channel or the continuous Z code string does not change, and the receiving side is also configured on this premise.

(1) The received data is branched and input to the code detection circuit 60 and further stored in the buffer 67.

(2) When a synchronization signal indicating the beginning of a frame is sent, the code detection circuit 60 generates a frame synchronization signal detection signal f.

The time slot counter 62 is reset by this signal f.

The time slot counter 62 counts the time slot pulses sent from a time slot pulse generator (not shown).

The time slot pulse generator can be configured with a timer counter that outputs a pulse every time the time determined by the time width of the time slot elapses.

(3) When a continuous Z code string is detected in a frame, the counter 61 counts this detection output Z.

At this time, the AND gate 63 is opened by the detection output Z, and the time slot number of the time slot counter 62 is stored in the register 64.

(4) Next, when a frame synchronization signal is detected, the speed data output from the counter 61 and the time slot data stored in the register 64 are registered in the channel table 65 based on the detection signal f.

The contents of the counter 61 indicate how many time slots with continuous Z code strings exist in one frame, and by checking this, it is possible to determine the transmission speed of the channel with that time slot. You can find out if it has been assigned.

This method of registration is similar to the method described above using table 38 of FIG.

For example, channel buffer CB1. CB2. ...
A flag F is set in the area prepared corresponding to each of the areas, and if this area is used, "1" is stored, and if this area is not used, "091" is stored. .

Therefore, the output of the counter 61 and the contents of the register 64 are written in the area where a table control circuit (not shown) detects 0''.

(5) When the registration is completed, the channel buffer number (for example, CB1) corresponding to the registered time slot number is stored in the time slot table 66.

The output of the time slot counter 62 is input as an address to the time slot table 66, and the time slot registered in the channel table 65, for example, T.

, Tn is the number of the channel buffer 69 (C
B1) is stored.

In the above case, the buffer 67 must be capable of storing data of one frame or more.

In other words, the time slot table 66 is in read mode when data is passed to the channel buffer allocated to the time slot registered in the channel table 65.
This is because the multiplexer 68 performs this operation at the time when the time slot counter 62 is addressed, and no channel buffer is allocated to the last time slot at the time one frame is received.

(6) The multiplexer MPX sends a channel buffer corresponding to the channel buffer data read from the time slot table 66, that is, a buffer 67 in CB1 in this example.
Connect.

(B) Data transfer processing mode (7) The data accumulated in the channel buffer (CB1) 69 is identified by the information identification circuit TO in terms of transfer address, speed, etc.

When the transfer destination address is identified, the channel 72 (CH1 to CHn) corresponding to the transfer destination address is selected, and the switch group 71 is switched to transfer the data.

As explained above, according to the present invention, when a data transmission request is received via a terminal line without fixedly allocating time slots to terminals, the transmission speed of the terminal is adjusted within one frame. Since an empty channel with a corresponding number of time slots is allocated to the data transmission request, the time division multiplex line can be used efficiently.
As a result, data transmission efficiency can be improved.

In addition, an empty state indication signal is placed in the time slot of an empty channel, and when the empty channel is assigned to a terminal line, prior to transmitting data from the terminal line via the time division multiplex line, A transmission start instruction signal is placed in a time slot corresponding to the number of transmission speeds in the assigned channel.

Therefore, on the receiving side, it is possible to detect the change from the empty state instruction signal to the transmission start instruction signal and easily recognize that transmission information has been assigned to the 7 time slots.

Furthermore, when data transmission requests are received from multiple terminals at the same time, channel assignment and time slot selection processing are performed for the terminal with the highest priority, and then channel assignment and time slot selection processing are performed for the terminal with the next highest priority.
Since slot selection processing is performed, it is possible to prevent a situation in which multiple channels having time slots with transmission start instruction signals exist simultaneously in one frame. It is possible to prevent confusion regarding judgment from occurring.

[Brief explanation of drawings]

Figure 1 shows a time division multiplexing network to which the present invention is applied.
FIGS. 2A and 2B are explanatory diagrams illustrating line allocation using a conventional time division multiplexing multiplexer and line allocation using a time division multiplexing multiplexer used in the present invention, and FIG. 3A is an exemplary configuration of a system. B is an explanatory diagram conceptually explaining a time division multiplex control system according to an embodiment of the present invention, and FIGS. 4 and 5 show configurations of an embodiment of the transmitting side and receiving side of the present invention. In the figure, 2-0.2-1.2-2 are time division multiplexers, 17.18.19 are input ports or terminals, 21, 22. -23 each represents a time division multiplex line, and To to T2n+1 each represent a time slot.

Claims (1)

[Claims] 1. A time division multiplexing device on the transmitting side, a plurality of terminals connected to the time division multiplexing device on the transmitting side via terminal lines,
A time division multiplexing control system comprising a time division multiplexing device on the receiving side, and a time division multiplexing line connecting the time division multiplexing device on the transmitting side and the time division multiplexing device on the receiving side, the method comprising: The time division multiplexing device on the side includes priority selection means for selecting one data transmission request according to the priority order of the terminal when data transmission requests are sent from one or more terminals, and the priority selection means. channel allocation means for allocating an empty channel of the time division multiplex line to the data transmission request selected by the channel allocation means; and the selected data from among the time slots of the empty channel allocated by the channel allocation means. time slot selection means for selecting a number of time slots according to the transmission speed of the terminal that has sent the transmission request; a multiplexer for selectively connecting the plurality of terminal lines to the time division multiplex line; Transmission start instruction signal generation means for placing a transmission start instruction signal on the terminal line of the terminal that has sent the selected data transmission request when a data transmission request is selected by the priority selection means; and a time slot counter. and a scanner address table that stores multiplexer control information in a memory location determined by the number of time slots.
Scanner address table reading leg means that reads the scanner address table using the contents of the time slot counter as an address and sends the read multiplexer control information to the multiplexer, and the time slot selection means selects the time slot. scanner address table write control means for writing multiplexer control information uniquely determined by the terminal using the time slot into each storage location determined by the number of each of the one or more time slots. The receiving side time division multiplexer is equipped with a plurality of channel multiplexers.
a buffer, a distributor for selectively connecting the time division multiplexed line to each of the plurality of channel buffers, a transmission start instruction signal detection means, a time slot counter, and a time slot counter having a transmission start instruction signal. time slot number storage means for storing slot numbers; channel buffer selection means for selecting an empty channel buffer when a transmission start instruction signal is sent via the time division multiplex line; A time slot table that stores distributor control information in a storage location determined by the slot number, and a time slot table that uses the contents of the time slot counter as an address to read the distributor control information read out. said selected time slot table read control means to said distributor and said selected time slot table to each memory location determined by each of said time slot number or plurality of time slot numbers stored in said time slot number storage means. and time slot table write control means for writing distributor control information uniquely determined by the channel buffer assigned to the time slot table.