JPS5851575A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the electron mobility of a semiconductor device by forming a crystal defect in the boundary between an electron supply layer and a channel layer, accelerating and diffusing N type impurity in the channel layer, and then forming and allowing electrodes, thereby reducing the contacting resistance. CONSTITUTION:An electron supply layer 4 made of N type AlGaAs single crystal is used as an upper layer, a channel layer 2 made of GaAs single crystal substantially having no impurity is used as a lower layer, proton (H<+>) is implanted in the vicinity of the boundary between the layers 4 and 2 of source and drain forming region, thereby forming a crystal defect, N type impurity is accelerated and diffused from the layer 4 into the layer 2 of the source and drain forming region, and source and drain electrodes 9 are then formed and alloyed. In this manner, a high electron mobility transistor of low contacting resistance of the source and drain regions can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing Fi cow conductor equipment. In terms of bonds,
Patent application filed by the applicant of this patent application
The present invention relates to an improvement in a method for manufacturing a high electron mobility transistor according to No. 2035).

High electron mobility transistors have different electron affinities2
The electron a change in the electron storage layer (two-dimensional electron gas) generated near one heterojunction surface formed by joining different semiconductors is controlled by the voltage applied to the control electrode. Hold the electrodes-r! An active conductor device that controls the impedance of a conductive path formed by the electron storage layer (two-dimensional electron gas) between a pair of output electrodes provided.

A major feature of high electron mobility transistors is that the electron mobility of the above-mentioned electron storage layer (two-dimensional Amiko gas) is maintained at a low temperature, e.g. 77°K, at which the effect of impurity scattering is the main cause of suppressing electron mobility. There is a 1% chance that it will become extremely large. The above electron storage layer (two-dimensional electron gas) is a semiconductor layer (channel layer) with a high electron affinity that does not require impurity doping, but it is very thin and has a thickness within about 100X in the vicinity of the heterojunction. 71% of the electron affinity required for the impurity P to be spatially separated from the layer consisting of the small conductor (electron supply layer),
Its electron mobility is not affected by impurity scattering. Therefore, extremely high electron mobility is achieved at low temperatures where the effect of impurity scattering prevents an increase in electron mobility. This improvement in electron mobility is achieved by using ordinary N-type (I x 10110l7”) GaAs.
It has been experimentally confirmed that it is about 10 times or more than "t%."

There are several combinations of conductors that can form a high electron mobility transistor, as long as they have similar lattice constants, a large difference in electron affinity, and a large difference in energy gap. . Among them, the present invention deals with N-type aluminum gallium arsenide (A/Ga
Aa) is used as the electron supply layer and non-doped gallium arsenide (
This is an improvement when using GaAs) as the channel layer.

In addition, high electron mobility transistors are classified into two types depending on whether the semiconductor layer (channel layer) with high electron affinity is placed on the upper layer or the lower layer. Depending on whether the ratio between the metallurgical thickness of the channel layer and the metallurgical thickness of the semiconductor layer with low electron affinity (electron supply layer) is larger or smaller than a specific value determined by the layer structure. Normally off type (enhancement mode P). In the latter case, the metallurgical thickness of the semiconductor layer (electron supply layer) with small electron affinity Depending on whether it is larger or smaller than a specific value determined by
The present invention has an improvement 1 in the case where the channel layer is the lower layer and the supply layer is the upper layer.

In a high electron mobility transistor having such a configuration, electrical conduction between the source/drain electrodes and the electron storage layer (two-dimensional electron gas) containing a conductive medium has conventionally been achieved using a gold/gold germanium material (au/gold/germany material). This was done by alloying the source/rrain electrode forming material such as AuGe), but since aluminum (GaAs) is a 1% conductor with which ohmic contact is difficult to form, it is particularly difficult to form source/drain electrodes. When the layer to which the electron supply layer is aluminum gallium arsenide (A/GaAs) i', satisfactory results have not been obtained. aAs
) layer and channel layer of gallium arsenide (GaAs)
A method has been adopted in which a part of the layer is removed and source/drain electrodes are formed directly on the gallium arsenide (GaAs) layer that is the channel layer, but in this case, it naturally becomes a mesa type, which hinders integration. It had the disadvantage of becoming

The purpose of the present invention is to eliminate this drawback, and the present invention uses an electron supply layer made of a single crystal layer of summer-type aluminum gallium arsenide (A/GaAs) as an upper layer, and uses arsenide gallium arsenide containing substantially no impurities. To provide a method for manufacturing a high electron mobility transistor with low contact resistance in the source/drain region in a planar type high electron mobility transistor having a channel layer such as a single crystal layer of Alium (GaAa) as the lower layer. be.

The gist is that gallium arsenide (GaAs), which is substantially free of C2 impurities, is grown on a substrate made of moderately insulating gallium arsenide (GaAs) with chromium (C0r) etc.
A channel layer made of a single crystal layer, a 9277 layer made of an aluminum gallium arsenide (A/GaAs) single crystal layer containing no impurities, and an N-type aluminum gallium arsenide (A/GaAa) single crystal layer. An electron supply layer consisting of
Drain formation region 9. Form a mask in the outer region and use this mask to program only the source and drain regions.
The aluminum arsenide (A4GaAe) layer and the aluminum arsenide (A4GaAe) layer are implanted in this region.
After generating defects in the 70010sn + c
A heat treatment of 1 degree F is applied to the area where crystal defects were generated in the previous process.
s) layer, silicon (Sl), which is an N-type impurity, is diffused at an accelerated rate into the gallium arsenide (GaAa) layer in the opposing region, which equally contains crystal defects, to form aluminum gallium arsenide (AIGaAs). layer and arsenide gallium (Ga)
After reducing the contact resistance between the aluminum nitride (A/N) layer and the aluminum nitride (A/N) layer, the protective film made of aluminum nitride (A/N) is removed.
Source/drain electrodes made of materials such as Au/AuGe are formed and then alloyed to form source/drain electrodes with low contact resistance.
A drain electrode is formed, and then a gate electrode is formed in a gate electrode formation region sandwiched between the source and drain electrodes using a conventional method. The conditions for proton implantation are based on the "LBS theory" regarding the acceleration energy of the implanted ions and the depth that the implanted ions reach.
In consideration of the thickness of the electron supply layer and the Tumasofa layer, the selection should be made so that the gap between the implanted ions is maximized near the interface between the 79777 layer and the channel layer.More specifically, If the thickness of the aluminum layer (A/GaAs) layer is α2Jm, 59K
It is desirable to implant ions with an acceleration energy of approximately eV or more. Furthermore, the function of the Tsumasho layer interposed between the channel layer and the electron supply layer is to accelerate diffusion of silicon (Si) into the source/P-rain region.
The purpose of this method is to prevent impurities from diffusing into the channel layer below the gate region from the electron supply layer and reducing the electron mobility of the electron storage layer (two-dimensional insulator gas) during heat treatment at about 0°C.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor bag according to an embodiment of the present invention, specifically, an electron transfer transistor, will be explained with reference to the drawings, and the structure and unique effects of the present invention will be clarified.

Using the Molecule error beam epitaxial growth method (see Figure 1),
A non-doped gallium arsenide (GaAl) layer (channel layer) 2 is formed on a semi-insulating gallium arsenide (GaAs) substrate 1 doped with chromium (Or), etc., and a non-doped gallium arsenide (GaAs) layer (channel layer) 2 with a thickness of approximately 150 to 6oX. Aluminum/Ga 8 layer (A177 layer) 3 having a
Then, an aluminum island umgarium arsenic (mu/GaAs) layer (electron supply layer) 4 doped with m and having a thickness of about α2fim is formed. As mentioned above, the function of the layer 3 is to prevent impurity diffusion in the region below the gate during the epitaxial growth process and the heat treatment process.

Referring to FIG. 2, a mask layer 5 is formed on the electron supply layer 4 except for the source and r-rain regions using a photolithography method.
Energy around 0 KeV and I x 10”/IIP
Protons (H+) are injected at varying doses.

This energy generates a region 6 containing the largest amount of crystal defects near the interface between the Tsumasso layer 3 and the channel layer 2.

After removing the mask layer 5 (see FIG. 3), a protective film 7 made of aluminum nitride (A/N) having a thickness of about 1000× is formed by sputtering, and then heat treated at a temperature of about 700° C. If this protective film 7 were not present, the electron supply layer 4 would be made of aluminum gallium arsenide (A/GaAs) (
A8) is sublimed and the electron supply layer 4 is damaged.0 In this heat treatment step, an N-type impurity is added to the arsenide gas (GaAs) region of the region 6 where crystal defects have occurred in the previous step. ) diffuses at an accelerated rate to form an N-type gallium arsenide (GaAa) region 6', and the contact resistance between the electron supply layer 4 and the channel layer 2 is reduced in this region where the source/drain 7 is formed.

After melting and removing the protective film 7 using hot phosphoric acid (H3PO4), etc., see FIG. Cover, Gold/Gold Gourmet Todorotsumu (Au/AuGe)
A metal layer 9 such as the above is deposited and then alloyed at 400 to 450°C. Step F above, Naj's gallium arsenide (Ga
As) region 6' is formed at 〒, so that the source
In the drain formation region, a gold/gold germanium layer (
Mu/AuGθ) layer 9 and electron storage layer (two-dimensional electron gas)
The contact resistance will be very low.

Refer to FIG. 5 Mask layer 8 and gold/gold germanium (Au/muGe) formed thereon from other than the source/drain regions.
By removing layer 9, source/f-rain electrode 9 is completed.

Refer to Fig. 6. Using a photolithography method, cover the area other than the gate formation area with a mask (not shown)'t%, and after vapor depositing aluminum gourd (A/), etc., use a lift-off method to cover the area other than the gate formation area with a mask (not shown). and the aluminum (A/) layer,
Goo) Complete 10.

As explained above, according to the present invention, an electron supply layer such as a single crystal layer of N-type aluminum gallium arsenide (GaAs) is used as an upper layer, and gallium arsenide (GaAa) containing substantially no impurities is used as an upper layer. ) In a planar high electron mobility transistor with a channel layer made of a single crystal layer as the lower layer, protons (H+) are intentionally injected near the interface between the electron supply layer and the channel layer in the source/drain formation region. Crystal defects are created and NW! Provided is a method for manufacturing a high electron mobility transistor with low contact resistance in the source/drain region, which is characterized by performing accelerated diffusion of impurities, followed by formation of a north P-rain electrode and alloying. can do.

[Brief explanation of the drawing]

Figures 1+2+3+4 and 5.6 are sectional views 1 of a substrate in main steps of a semiconductor device, specifically a planar high electron mobility transistor, according to an embodiment of the present invention. 1...Chromium P-treated insulating arsenide gallium material substrate, 2...Channel layer (substantially impurity-free aluminum oxide film 5I! single crystal layer), 3.
. . . Nonotufa layer (aluminum gallium arsenic layer containing substantially no impurities), 4 . . . electron supply layer (
- N-type aluminum layer (Arsenic layer), 5...
Mask layer (photoresist layer), 6... region containing crystal defects, 6'... N-type gallium arsenide region, film... protective film made of aluminum nitride, 8.・
・Mask layer (photoresist layer), 9... Source/drain electrode layer (gold/gold germanium upper layer), lO...
Gate electrode layer (upper layer of aluminum alloy) 0 Figure 6

Claims (1)

[Claims] A channel layer made of a single crystal layer of gallium arsenide containing substantially no impurities is formed on a substrate made of medium-insulating gallium arsenide, and a monocrystalline layer of gallium arsenide containing substantially no impurities is formed on the channel layer. An electron supply layer made of an N-type single crystal layer of aluminum gallium arsenide is formed on the second sofa layer, and a source/P-rain of the electron supply layer is formed. A mask is formed on a region other than the formation region, and using the mask, protons are selectively implanted into the source/drain formation region, and then heat treatment is performed at a temperature sufficient to cause impurity diffusion in the proton implantation region 1. After applying
A step of forming a source/drain electrode on the source/P-rain forming region of the electron supply layer, forming a metal layer on the gate electrode forming region sandwiched by the source/drain electrode, and completing the gate electrode. , a method for manufacturing a semiconductor device.