JPS58528U - Fail-safe type AND circuit - Google Patents
Fail-safe type AND circuitInfo
- Publication number
- JPS58528U JPS58528U JP9347781U JP9347781U JPS58528U JP S58528 U JPS58528 U JP S58528U JP 9347781 U JP9347781 U JP 9347781U JP 9347781 U JP9347781 U JP 9347781U JP S58528 U JPS58528 U JP S58528U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- fail
- stage
- output
- safe type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のアンド回路の構成例を示すブロック図、
第２図はこの考案の一実施例を示すブロック図、第３図
は第２図の具体例を示す回路図である。 ′
１、 ＩＡ、 ２・・・・・・増幅回路、３．４・
・開塾流回路、ＲＹｌ、 ＲＹ２． ＲＹ・・曲リレー
、ＴＲ１〜ＴＲ３・・曲トランジスタ、Ｒｃｍ、 ＲＣ
２・・開塾流器。FIG. 1 is a block diagram showing an example of the configuration of a conventional AND circuit.
FIG. 2 is a block diagram showing an embodiment of this invention, and FIG. 3 is a circuit diagram showing a specific example of FIG. '1, IA, 2...Amplification circuit, 3.4.
・Kaijuku style circuit, RYl, RY2. RY...Tune relay, TR1~TR3...Tune transistor, Rcm, RC
2...Kaijuku Ryuuki.
Claims (1)
を得る回路において、前記ｎ個のアナログ信号をそれぞ
れ与えられるｎ個の第１回路と、各第１回路の出力をそ
れぞれ整流して直流信号に変換するｎ個の第２回路とを
設け、ｍ（ｍは２からｎまで）段目の第２回路の出力を
ｍ−１段目の第１回路の一部電源にするとともに、当該
第１回路の主電源と逆極性になるように接続し、前記ｎ
個のアナログ信号の論理積を初段の第２回路の出力で得
るようにしたことを特徴とするフェールセーフ形アンド
回路。- In a circuit that obtains a logical product signal from n analog signals in a fail-safe manner, there are n first circuits to which each of the n analog signals is applied, and the output of each first circuit is rectified into a DC signal. n second circuits for conversion are provided, and the output of the m-th (m is from 2 to n) stage second circuit is used as a part of the power supply for the m-1 stage first circuit; Connect it so that it has the opposite polarity to the main power supply of the circuit, and
1. A fail-safe AND circuit characterized in that the AND circuit of two analog signals is obtained at the output of a second circuit in the first stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9347781U JPS58528U (en) | 1981-06-24 | 1981-06-24 | Fail-safe type AND circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9347781U JPS58528U (en) | 1981-06-24 | 1981-06-24 | Fail-safe type AND circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58528U true JPS58528U (en) | 1983-01-05 |
Family
ID=29888443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9347781U Pending JPS58528U (en) | 1981-06-24 | 1981-06-24 | Fail-safe type AND circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58528U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5152254A (en) * | 1974-11-01 | 1976-05-08 | Japan National Railway | FUEERUSEEFUANDORONRIKAIRO |
-
1981
- 1981-06-24 JP JP9347781U patent/JPS58528U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5152254A (en) * | 1974-11-01 | 1976-05-08 | Japan National Railway | FUEERUSEEFUANDORONRIKAIRO |
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