JPS5855873A - Ic tester - Google Patents
Ic testerInfo
- Publication number
- JPS5855873A JPS5855873A JP56155886A JP15588681A JPS5855873A JP S5855873 A JPS5855873 A JP S5855873A JP 56155886 A JP56155886 A JP 56155886A JP 15588681 A JP15588681 A JP 15588681A JP S5855873 A JPS5855873 A JP S5855873A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- memory
- pattern generator
- register
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001960 triggered effect Effects 0.000 claims description 4
- 238000012360 testing method Methods 0.000 abstract description 5
- 238000012545 processing Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 230000004044 response Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（１７発明の技術分野
この発明は、ＩＣの評価試験や分類試験などで、ＩＣの
電源電圧や入力電圧などを変えて試験する場合に、リア
ルタイムでこれらの電圧を変えられるＩＣテスタについ
てのものである。[Detailed Description of the Invention] (17 Technical Field of the Invention This invention provides a method for changing the power supply voltage, input voltage, etc. of an IC in real time when testing is performed by changing the power supply voltage or input voltage of the IC in an IC evaluation test or classification test. This is about an IC tester.
（２１従来技術
従来装置の一例を第１図に示す。図で、１は試験される
ＩＣ５の試験プログラムを実行するコンビエータ、２は
マイクロプログラムを実行するパターン発生器、５はコ
ンビエータ１からプログラム電圧Ｖｌ、Ｖ２などを与え
ら牡るレジスタ、４はＤ／Ａ変換器である。(21 Prior Art) An example of a conventional device is shown in FIG. A register 4 is a D/A converter to which Vl, V2, etc. are applied.
コンビエータ１はパターン発生器２をトリカスる。パタ
ーン発生器２はコンビ為−夕１から電圧を変える命令が
くると、パターン発生器２の動作を一時中止し、コンビ
為−夕１を介して新たに変更する電圧をレジスタ５に転
送する。Combiator 1 tricuses pattern generator 2. When the pattern generator 2 receives a command to change the voltage from the combination controller 1, the pattern generator 2 temporarily stops its operation and transfers the voltage to be newly changed to the register 5 via the combination controller 1.
次Ｋ、第１図の動作波形例を第２図に示す６図のタイミ
ングＴ１でコンビエータ１がレジス゛り５をトリガし、
レジスタＳからの出力はＤ／Ａ変換器４を経てＩＣ５に
電圧ｖ１として与えられる。Next, the operation waveform example of FIG. 1 is shown in FIG. 2. At timing T1 in FIG. 6, the combiator 1 triggers the register 5,
The output from the register S is applied to the IC 5 as a voltage v1 via the D/A converter 4.
タイミングＴ２でレジスタ５にデータを転送しトリガす
ると、ＩＣ５の電圧■１が電圧Ｖ２に変る。この電圧が
変る時間Ｔｍはパターン発生器２の命令から電圧■２を
出すまでのコンビエータ１の処理時間で決り、実際には
タイミングＴ５でＩＣ５に電圧ｖ２が加わる。When data is transferred to the register 5 at timing T2 and triggered, the voltage 1 of the IC 5 changes to the voltage V2. The time Tm during which this voltage changes is determined by the processing time of the combiator 1 from the command of the pattern generator 2 until it outputs the voltage 2, and in reality, the voltage v2 is applied to the IC 5 at timing T5.
（６） 従来技術の問題点
第１図の従来装置では、を圧■１をＩＣｓに加えておき
、電圧■１を電圧■２に変るためにトリガしてから実際
に電圧■２がＩＣ５に加わるまでの時間Ｔｍは数ｍｓも
かがシ、リアルタイム性に欠けるという問題がある。(6) Problems with the prior art In the conventional device shown in FIG. The time Tm until the signal is added is several milliseconds, and there is a problem in that it lacks real-time performance.
（４）発明の目的
この発明は、第１図のコンピュータ１とレジスタ３０間
にメモリをおき、ＩＣ５の電圧を変える場合はパターン
発生器２がこのメモリをトリガしてコンピュータ１の処
理時間、転送時間の影響を受けないＩＣテスタを提供す
るものである。(4) Purpose of the Invention This invention provides a memory between the computer 1 and the register 30 in FIG. The present invention provides an IC tester that is not affected by time.
（５）発明の実施例 この発明による実施例の系統図を第３図に示す。(5) Examples of the invention A system diagram of an embodiment according to the present invention is shown in FIG.
図で１〜５は第１図と同じなので説明を省略する。In the figure, 1 to 5 are the same as in FIG. 1, so their explanation will be omitted.
６はメモリで、メモリ６には変更する電圧を記憶させる
。メモリ６には複数のデータを記憶することができ、複
数の電源の値番同時に変えたり、１つの電源の値を複数
回変えたりすることができる。6 is a memory, and the memory 6 stores the voltage to be changed. A plurality of data can be stored in the memory 6, and the value numbers of a plurality of power supplies can be changed at the same time, and the value of one power supply can be changed multiple times.
コンピータ１はパターン発生器２をトリガする。パター
ン発生器２はマイクロプログラムを実行し、電圧を変え
る命令がくると、メモリ６をトリガする。メモリ６はデ
ータを読み出し、レジスタ３にデータを高速で転送する
。Computer 1 triggers pattern generator 2 . The pattern generator 2 executes a microprogram and triggers the memory 6 when a command to change the voltage comes. The memory 6 reads data and transfers the data to the register 3 at high speed.
次に、第３図の動作波形例を第４図に示す。図のタイミ
ングＴ１１でレジスタ３をトリガすると、レジスタ３か
らの出力は第１図と同じようにＤ／Ａ変換器を経てＩＣ
ｓに電圧■１として与えられる。Next, FIG. 4 shows an example of the operating waveforms shown in FIG. 3. When register 3 is triggered at timing T11 in the figure, the output from register 3 passes through the D/A converter to the IC as in Figure 1.
The voltage is given to s as voltage ■1.
タイミングＴＩ２でレジスタ３をトリガすると、ＩＣｓ
の電圧■１が電圧ｖ２に変る。この電圧が変る時間Ｔｎ
はパターン発生器２°の命令がらメモリ６の読み出し時
間で決シ、実際にはタイミングＴＩＳでＩＣ５に電圧■
２が加わる。When register 3 is triggered at timing TI2, ICs
The voltage ■1 changes to the voltage v2. Time Tn for this voltage to change
is determined by the reading time of the memory 6 according to the command of the pattern generator 2°, and in reality, the voltage is applied to the IC5 at the timing TIS.
2 is added.
時間Ｔｎは通常数百ｎｓである。すなわち、この発明は
電圧変更の処理時間を少なくするためＫ、メモリ読み出
しの高速性を利用したものである。The time Tn is usually several hundred ns. That is, the present invention utilizes the high speed of memory readout in order to reduce the processing time for changing the voltage.
＋６１ 発明の効果
この発明によれば、電圧を変えてＩＣを試験する場合に
電圧をリアルタイムで変えることができるので、高速で
ＩＣをテストすることができる。+61 Effects of the Invention According to the present invention, when testing an IC by changing the voltage, the voltage can be changed in real time, so the IC can be tested at high speed.
第１図は従来装置の一例、
第２図は第１図の動作波形例、
第５図はこの発明による実施例の系統図、第４図は第５
図の動作波形例。
１・・・・・コンピュータ、２・・・・・・パターン発
生器、３・・−・・・レジスタ、４・・・・・・Ｄ／Ａ
変換器、５・・・・・試験されるＩＣ１６・・・・・・
メモリ。
代理人 弁理士 小俣欽司
第１図
第２ ｒ４
第４図−FIG. 1 is an example of a conventional device, FIG. 2 is an example of the operating waveform of FIG. 1, FIG. 5 is a system diagram of an embodiment according to the present invention, and FIG.
An example of the operating waveform shown in the figure. 1...Computer, 2...Pattern generator, 3...Register, 4...D/A
Converter, 5...IC16 to be tested...
memory. Agent Patent Attorney Kinji Omata Figure 1 Figure 2 r4 Figure 4-
Claims (1)
暴−一と、仁のコンビ晶−一でトリガされるパターン発
生器と１−４ち、ＩＣへの電圧、電流を変えてＩＣの特
性を測定するＩＣテスタにおいて、 変更する電圧、電流値を記憶するメモリを備え、前記パ
ターン発生器からの信号で前記メモリの内容を読み出し
、この読み出しデータを前記レジスタにストアすること
を特徴とするＩＣテスタ。[Claims] 1. A combination device that sends an IC test program to a register, a pattern generator triggered by a combination device, and 1-4, a pattern generator that changes the voltage and current to the IC. An IC tester that measures the characteristics of an IC by using a memory that stores voltage and current values to be changed, reads the contents of the memory using a signal from the pattern generator, and stores this read data in the register. Features of IC tester.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56155886A JPS5855873A (en) | 1981-09-30 | 1981-09-30 | Ic tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56155886A JPS5855873A (en) | 1981-09-30 | 1981-09-30 | Ic tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5855873A true JPS5855873A (en) | 1983-04-02 |
Family
ID=15615648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56155886A Pending JPS5855873A (en) | 1981-09-30 | 1981-09-30 | Ic tester |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5855873A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5674666A (en) * | 1979-11-26 | 1981-06-20 | Nec Corp | Voltage level generator |
-
1981
- 1981-09-30 JP JP56155886A patent/JPS5855873A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5674666A (en) * | 1979-11-26 | 1981-06-20 | Nec Corp | Voltage level generator |
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