JPH01143100A - High speed random access memory testing device - Google Patents

Abstract

PURPOSE:To easily execute the test of high speed RAM by executing the test controlling the input of a common hold control signal to the input of a cycle common clock signal. CONSTITUTION:A common clock signal 37 is given to a RAM synchronized with a tester clock, and continuously, the input of a common hold control signal 38 is controlled so that the signal 37 may be effective for only two rounds, for instance, between the tester clocks. Since the signal 37 for a test is synchronized with the timing of tester strobing, accordingly, the signal 38 can be controlled by the tester. This RAM hold cancelled for only two pulse of the signal 37 fetches each signal of writing data 12, an address 15 and writing control input 19 by a first pulse, and the contents of a memory cell array 26 are fetched to a reading data FF group 29 by a second pulse and outputted. Thus, a memory access can be measured by two pulses of the signal 37, and a high speed RAM test can be executed easily.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a test method for random access memory;
In particular, it relates to a test device for high-speed random access memory.

[Conventional technology]

Conventionally, low interlock random access memory (hereinafter referred to as RAM) has been tested by inputting addresses, write data, write instructions, etc. using a memory tester, and performing functional tests by strobing read data output. Ta.

[Problem that the invention seeks to solve]

However, in this case, address input, write data, write instruction input, etc. were each set according to the input timing standard, but in the case of address input, access performance varies depending on the accuracy of the skinny adjustment in the memory tester. There was a problem with this.

In addition, recent RAMs have become faster and faster, and memory testers that test them are currently unable to keep up in terms of performance, especially in terms of high speed. That is, the measurement accuracy of the memory test is poor, and the RAM access value is buried in the memory test.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed RAM test device that can easily test high-speed RAM that cannot be tested with sufficient accuracy using conventional memory testers.

[Means for solving problems]

A high-speed RAM test device of the present invention includes an address flip-flop circuit for setting an address input, a write data flip-flop circuit for setting a write data input, a write instruction flip-flop circuit for setting a write instruction,
a read data flip-flop circuit for setting read data; all of these flip-flop circuits have a hold function; and a common clock input section that commonly supplies a periodic clock signal to these flip-flop circuits; Similarly, a common hold control signal input section provides a common hold control signal that cycles to the common clock signal common to these flip-flop circuits,
Thereby, the common clock signal and the common hold control signal are applied to the high-speed random access memory to be tested, thereby enabling operation in an arbitrary clock cycle.

Therefore, using the high-speed RAM test device of the present invention, high-speed RAM
When testing M, since a stable periodic clock and hold control are used, the test can be easily and highly accurate.

〔Example〕

The present invention will be described in detail below with reference to Examples.

FIG. 1 is a block diagram of a high-speed RAM test device according to this embodiment. Write data 12 input from a write data input group terminal 11 is set in a write data flip-flop (hereinafter referred to as F/F) group 13. Similarly, address 15 input from address input group terminal 14 is set in address F/F group 16. The write control input 19 input from the write control input group terminal 18 is set to the write side iHF/F group 20.

These write data F/F group 13, address F/F group 1
6, and corresponding outputs from the write control F/F group 20, such as a write data F/F group output 22, an address F/F group output 23, and a write control F/F group output 24, are output from the memory cell array 26. is input. The output 28 from this memory cell array 26 is set to a read data F/F group 29,
The output 30 is output from the read data output group terminal 31.

The above write data F/F group 13, address F/F group 16
, the write control F/F group 20, and the read data F/F group 29 are connected to a common clock input terminal 34 and a common hold control input terminal 35.

A common clock signal 37 and a common hold control signal 38 are applied to the common clock input terminal 34 and the common hold control input terminal 35, respectively, and are used to control the above-mentioned F/'F group.

Next, the operation will be explained.

FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG. In this embodiment, the tester clock 41 (Fig. 2a)
), a periodic common clock signal 37 is sent to the RAM in synchronization with
(C in the same figure) and the common hold control signal 38 (D in the same figure) so that only two common clock signals 37 (C in the same figure) are valid during the subsequent tester clock 41 (A in the same figure)
controls the input. This common clock signal 37 for testing (C in the same figure) is synchronized with the timing of the tester clock 41 (A in the same figure) and therefore the tester strobe 42 (B in the same figure), so the common hold control signal 38 (D in the same figure) can be controlled by tasks.

The RAM whose hold is released by two pulses of the common clock signal 37 (C in the same figure) receives the first pulse 43 (
The write data 12 (e), address 15 (f), and write control input 19 (g) from the tester are taken in at step C), and the second pulse 44 (g) is input from the tester. In FIG. C), the contents of the memory cell array 26 are taken into the read data F/F group 29 and outputted as the read data F/F group output 44.

In this way, memory access can be measured using two pulses of the common clock signal 37 (C in the figure).

Since the common clock signal 37 (C in the same figure) is applied continuously, it can be set with high precision, and moreover, high-speed testing can be realized.

〔Effect of the invention〕

As explained above, the present invention provides an F/F group with a hold function, a common clock input terminal, and a common hold control input terminal in the human output interface section of the RAM under test, and responds to the input of a periodic common clock signal. By controlling the input of the common hold control signal and performing the test, it is possible to easily test high-speed RAM, which is insufficiently accurate with existing memory testers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a high-speed RAM test device according to the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of FIG. 11...Write data input group terminal, 13...
...Write data F/F group, 14...Address input group terminal, 16...Address F/FIJ, 18
...Write control input group terminal, 20...Write control F/F group, 26...Memory cell array, 29...Read data F/F group, 34...
- Common clock input terminal, 35...Common hold control input terminal. Applicant: NEC Corporation Representative

Claims (1)

[Claims] An address flip-flop circuit that sets address input, a write flip-flop circuit that sets write data input, a write instruction flip-flop circuit that sets write instruction, and read data. A read data flip-flop circuit is provided, all of these flip-flop circuits have a hold function, and a clock input section that commonly supplies a periodic clock signal to these flip-flop circuits is provided. a common hold control signal input section for providing a common hold control signal that cycles to the common clock signal to the common hold control circuit; 1. A high-speed random access memory test device characterized in that it provides a clock cycle and enables operation in an arbitrary clock period.