JPS585596B2 - inverter circuit - Google Patents

inverter circuit

Info

Publication number
JPS585596B2
JPS585596B2 JP52139843A JP13984377A JPS585596B2 JP S585596 B2 JPS585596 B2 JP S585596B2 JP 52139843 A JP52139843 A JP 52139843A JP 13984377 A JP13984377 A JP 13984377A JP S585596 B2 JPS585596 B2 JP S585596B2
Authority
JP
Japan
Prior art keywords
voltage
inverter
transformer
wave
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52139843A
Other languages
Japanese (ja)
Other versions
JPS5473237A (en
Inventor
雨海秀行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Electric Industry Co Ltd
Original Assignee
Nippon Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Industry Co Ltd filed Critical Nippon Electric Industry Co Ltd
Priority to JP52139843A priority Critical patent/JPS585596B2/en
Publication of JPS5473237A publication Critical patent/JPS5473237A/en
Publication of JPS585596B2 publication Critical patent/JPS585596B2/en
Expired legal-status Critical Current

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  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 本発明はインバータ回路並びに点弧方法に関するもので
あり、その目的とするところは、パルス巾モジュレーシ
ョン方式(以後PWM方式と称すにより負荷電圧を制御
できると共に直流入力電圧が低い場合にも小容量の転流
コンデンサで確実に転流ができると共に、出力側短絡保
護並びに濾波の容易なインバータ回路を提供するにある
。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter circuit and an ignition method, and its purpose is to control load voltage by using a pulse width modulation method (hereinafter referred to as PWM method) and to achieve a low DC input voltage. It is an object of the present invention to provide an inverter circuit that can reliably commutate current with a small-capacity commutating capacitor even in cases where the output side is short-circuit protected and that filtering is easy.

第1図は従来におけるインバータ回路である。FIG. 1 shows a conventional inverter circuit.

第1図においてEは直流電源、Th1〜Th4はサイリ
スタ、Tはトランス、Fは濾波回路、1は負荷である。
In FIG. 1, E is a DC power supply, Th1 to Th4 are thyristors, T is a transformer, F is a filter circuit, and 1 is a load.

第1図においてサイリスタTh1〜Th4に対しては図
示されていない転流回路が接続されているのでThlと
Th2またはTh3とTh4は交互に点弧と消弧が繰返
される。
In FIG. 1, commutation circuits (not shown) are connected to the thyristors Th1 to Th4, so that Thl and Th2 or Th3 and Th4 are alternately turned on and off.

従ってサイリスタThl〜Th4の点弧を適当に行うと
、トランスTの1次巻線に第2図に示す如き多数の矩形
波を発生せしめることができる。
Therefore, by properly firing the thyristors Thl to Th4, a large number of rectangular waves as shown in FIG. 2 can be generated in the primary winding of the transformer T.

この矩形波電圧の巾を変化せしめると図示平均値曲線v
1の大きさが変化しインバータの出力電圧を制御するこ
とができる。
When the width of this rectangular wave voltage is changed, the average value curve v
1 can be changed to control the output voltage of the inverter.

かかる電圧制御方式をPWM方式と称する。This voltage control method is called a PWM method.

曲線V1を正弦波に近づけることにより、正弦波電圧負
荷1に対して濾波回路Fを小さくすることができる特長
を有する。
By making the curve V1 close to a sine wave, the filter circuit F can be made smaller with respect to the sine wave voltage load 1.

しかし第1図に使用される転流コンデンサに充電される
電圧はほぼ直流電圧Eの電圧に等しいので直流電源Eが
低い電圧の場合においては転流コンデンサの容量を極め
て大きなものを必要とする欠点があった。
However, the voltage charged in the commutating capacitor used in Figure 1 is approximately equal to the voltage of the DC voltage E, so when the voltage of the DC power supply E is low, the commutating capacitor must have an extremely large capacity. was there.

かかる欠点を解決するインバータとして第3図に示すイ
ンバータによりPWM方式を行うことが考えられ既に弊
社より実願昭52−142503で実用新案登録出願中
である。
As an inverter to solve these drawbacks, an inverter shown in FIG. 3 using the PWM method has been proposed, and our company has already applied for a utility model registration under Utility Model Application No. 142503/1983.

第3図のインバータにおいてC1は転流コンデンサ、N
1はトランスTの1次巻線の中性点である。
In the inverter shown in Figure 3, C1 is a commutating capacitor, N
1 is the neutral point of the primary winding of the transformer T.

第3図のインバータにおいては転流コンデンサC1に対
しては直流電源Eの約2倍の電圧に充電される結果、コ
ンデンサC1には十分な転流エネルギーが蓄えられるの
で、直流電源Eの電圧が低い場合も小容量のコンデンサ
で確実に転流を行い得る利点がある。
In the inverter shown in Figure 3, the commutation capacitor C1 is charged to a voltage approximately twice that of the DC power supply E, and as a result, sufficient commutation energy is stored in the capacitor C1, so that the voltage of the DC power supply E increases. Even when the current is low, there is an advantage that commutation can be performed reliably with a small capacitor.

しかし第3図のインバータにおいては、PWM方式とし
た場合、トランスTの出力電圧は第4図に示す如き矩形
波となり、正の半波電圧期間にも負の矩形波が存在する
ので濾波回路Fが大きくなるとともに、負荷短絡時イン
バータの出力電圧を零に絞っても、トランスTの出力側
には高調波電圧即ち半サイクル期間に巾がほぼ同一の正
の矩形波と負の矩形波が交互に繰返される状態になるの
で浦波回路Fの高調波に対するインピーダンスが小さい
と高調波短絡電流がかなり大きくなる欠点があつた。
However, in the inverter shown in Fig. 3, when using the PWM method, the output voltage of the transformer T becomes a rectangular wave as shown in Fig. 4, and since a negative rectangular wave also exists during the positive half-wave voltage period, the filter circuit F As the voltage increases, even if the output voltage of the inverter is reduced to zero when the load is shorted, a harmonic voltage, that is, a positive rectangular wave and a negative rectangular wave of approximately the same width alternate in the half cycle period on the output side of the transformer T. If the impedance of the Urahami circuit F to harmonics is small, the short-circuit current of the harmonics becomes considerably large.

本発明は第3図に示す如きインバータを2台し上組合せ
、各インバータの点弧を異らしめると世に前記インバー
タの出力側を直列に接続することにより、正の半波期間
には複数の正の矩形波のみを、また、負の半波期間には
複数の負の矩形波のみを発生する如くすることにより、
第1図および第3図のインバータにおける欠点をなくし
、PWM方式により負荷電圧を制御できると共に直流入
丈電圧が低い場合にも、小容量の転流コンデンサて確実
に転流ができると共に出力側短絡保護並びに濾波の容易
なインバータ回路としだものである。
The present invention combines two inverters as shown in FIG. By generating only a positive square wave and only a plurality of negative square waves during the negative half-wave period,
Eliminating the drawbacks of the inverters shown in Figures 1 and 3, the load voltage can be controlled using the PWM method, and even when the DC current length voltage is low, commutation can be performed reliably using a small-capacity commutation capacitor, and output side short circuits can be achieved. This is an inverter circuit that is easy to protect and filter.

本発明によるインバータ回路の実施例回路を第5図に示
す。
An embodiment of the inverter circuit according to the present invention is shown in FIG.

第5図においてC2は転流コンデンサTI,T2はトラ
ンス、Nl,N2はそれぞれトランスTI,T2の1次
巻線の中性点、IVi,Iv2は第3図に示すインバー
タと同様のインバータであって負荷の慣性電流を直流電
源側へ帰還せしめる帰還回路等を備えているが図示され
ていない。
In FIG. 5, C2 is a commutating capacitor TI, T2 is a transformer, Nl and N2 are the neutral points of the primary windings of the transformer TI and T2, respectively, and IVi and Iv2 are inverters similar to the inverter shown in FIG. A feedback circuit for feeding back the inertial current of the load to the DC power supply side is provided, but it is not shown.

インバータIV1,IV2は共に直流電源Eの電圧を印
加されて、それぞれトランスT1およびT2の2次巻線
に交流電圧を発生する如く接続され、トランスTI,T
2の2次巻線は互いに直列に接続されて、その出力を濾
波回路Fを介して負荷1に供給する如く接続される。
Both inverters IV1 and IV2 are connected to the voltage of the DC power supply E and are connected to generate an AC voltage in the secondary windings of the transformers T1 and T2, respectively.
The two secondary windings are connected in series with each other, and are connected so as to supply the output to the load 1 via the filter circuit F.

第5図においてトランスT1の出力電圧が第6図イにな
る如くサイリスタThlとTh2を交互に点弧し、トラ
ンスT2の出力電圧が第6図口になる如くサイリスタT
h3とTh4を交互に点弧すると瀘波回路Fの入力側に
は第6図ハに示す如き電圧が印加される。
In FIG. 5, thyristors Thl and Th2 are turned on alternately so that the output voltage of the transformer T1 becomes as shown in FIG.
When h3 and Th4 are turned on alternately, a voltage as shown in FIG. 6C is applied to the input side of the filter circuit F.

八に示す電圧は電圧イと口の和の電圧である。The voltage shown in 8 is the sum of voltage A and voltage A.

ハに示す電圧波形は正の半波期間においては正の矩形電
圧波形のみが生じ、負の半波期間においては負の矩形電
圧波形のみが生ずる。
In the voltage waveform shown in C, only a positive rectangular voltage waveform occurs during the positive half-wave period, and only a negative rectangular voltage waveform occurs during the negative half-wave period.

第6図八においてv3は矩形波の平均値曲線を示す、ま
た第5図において、トランスT1の出力電圧が第T図二
になる如くサイリスタThlとTh2を交互に点弧し、
トランスT2の出力電圧が第1図ホになる如くサイリス
タTh3とTh4を交互に点弧すると、波形回路Fの入
力側には第7図へに示す電圧が印加されるへに示す電圧
は電圧二とホの和の電圧である。
In FIG. 6, v3 represents the average value curve of a rectangular wave, and in FIG.
When the thyristors Th3 and Th4 are turned on alternately so that the output voltage of the transformer T2 becomes E in Fig. 1, the voltage shown in Fig. 7 is applied to the input side of the waveform circuit F. The voltage is the sum of and E.

第7図へにおいてv4は矩形波の平均値曲線を示す。In FIG. 7, v4 indicates an average value curve of a rectangular wave.

へに示す電圧波形においても正の半波期間においては正
の矩形電圧波形のみを生じ、負の半波期間においては負
の矩形電圧波形のみを生ずる。
Also in the voltage waveforms shown in (b), only positive rectangular voltage waveforms occur during the positive half-wave period, and only negative rectangular voltage waveforms occur during the negative half-wave period.

かかるハ、へに示す電圧波形は同一出力電圧実効値にお
いて各矩形波の立上り、または立下り電圧値を第4図の
矩形波に比し1/2にすることができるから高調波電圧
の含有率を小さくできるので濾波回路Fを小さくするこ
とができる。
The voltage waveforms shown in C and B contain harmonic voltages because the rising or falling voltage value of each rectangular wave can be reduced to 1/2 of that of the rectangular wave in FIG. 4 at the same output voltage effective value. Since the ratio can be made small, the filter circuit F can be made small.

また、負荷短絡に際してはトランスT1の出力電圧波形
とT2の出力電圧波形を互いに逆相にすることによりT
1とT2の和の電圧を零とし負荷に流れる電流を基本波
は勿論、高調波電流をも零にすることができるので出力
側短絡保護を容易に行うことができる。
In addition, when the load is short-circuited, the output voltage waveform of the transformer T1 and the output voltage waveform of the transformer T2 are made to have opposite phases to each other.
Since the voltage of the sum of T1 and T2 can be made zero and not only the fundamental wave but also the harmonic current flowing through the load can be made zero, short-circuit protection on the output side can be easily performed.

更にサイリスタの転流についても第3図と同様転流コン
デンサに直流電源Eの2倍の電圧に充電できるので小容
量のコンデンサでも転流ミスを生じ難い。
Furthermore, regarding the commutation of the thyristor, the commutation capacitor can be charged to a voltage twice that of the DC power source E, as shown in FIG. 3, so commutation errors are unlikely to occur even with a small capacity capacitor.

以上に説明した如く、本発明によるインバータ回路にお
いては正の半波期間には正の矩形波電圧のみを発生せし
め、負の半波期間には負の矩形波電圧を発生せしめるP
WM方式を採用できるので濾波が極めて容易となる。
As explained above, in the inverter circuit according to the present invention, only a positive rectangular wave voltage is generated during the positive half-wave period, and a negative rectangular wave voltage is generated during the negative half-wave period.
Since the WM method can be adopted, filtering becomes extremely easy.

直流入力電圧が低い場合にも小容量の転流コンデンサで
確実な転流ができ、かつ、負荷短絡時においても2台の
インバータの出力電圧位相を逆にして負荷電圧を零にな
し得るので短絡保護が容易である。
Even when the DC input voltage is low, reliable commutation is possible with a small-capacity commutation capacitor, and even in the event of a load short-circuit, the output voltage phases of the two inverters can be reversed to make the load voltage zero, so there is no short-circuit. Easy to protect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来におけるインバータ回路図、第2図は第1
図における出力電圧波形説明図、第3図はサイリスタを
2個使用したインバータ回路図、第4図は第3図のイン
バータによりPWM方式制御を行った場合の出力電圧波
形説明図、第5図は本発明によるインバータ回路の実施
例回路図、第6図及び第1図は第5図における作用説明
図である。 図中、Eは直流電源、Thl〜Th4はサイリスタ、T
,TI,T2はトランス、Fは濾波回路、CI,C2は
転流コンデンサである。
Figure 1 is a conventional inverter circuit diagram, and Figure 2 is a circuit diagram of a conventional inverter.
Figure 3 is an inverter circuit diagram using two thyristors. Figure 4 is an illustration of the output voltage waveform when PWM control is performed using the inverter in Figure 3. Figure 5 is an illustration of the output voltage waveform when PWM control is performed using the inverter in Figure 3. Embodiment circuit diagrams of the inverter circuit according to the present invention, FIG. 6 and FIG. 1 are explanatory diagrams of the operation in FIG. 5. In the figure, E is a DC power supply, Thl to Th4 are thyristors, and T
, TI, T2 are transformers, F is a filter circuit, and CI, C2 are commutating capacitors.

Claims (1)

【特許請求の範囲】[Claims] 1 トランスの1次巻線の中性点で2分割される2つの
巻線に転流回路を有するサイリスタにより交互に直流電
源電圧を印加して、トランスの出力側に、交流電圧を発
生せしめるインバータを2台以上組合せ、それぞれのイ
ンバータの基本波形をトランスの出力の基本波形に同期
させ各インバータの点弧を異らしめると共に、前記イン
バータの出力側を直列に接続することにより、正の半波
期間には複数の正の矩形波のみをまた、負の半波期間に
は複数の負の矩形波のみを発生する如くしたことを特徴
とするインバータ回路。
1. An inverter that generates an alternating current voltage on the output side of the transformer by alternately applying a direct current power supply voltage to two windings that are divided into two at the neutral point of the primary winding of the transformer using a thyristor having a commutation circuit. By combining two or more inverters, synchronizing the basic waveform of each inverter with the basic waveform of the output of the transformer, making the firing of each inverter different, and connecting the output sides of the inverters in series, positive half-wave An inverter circuit characterized in that it generates only a plurality of positive rectangular waves during a period and only a plurality of negative rectangular waves during a negative half-wave period.
JP52139843A 1977-11-24 1977-11-24 inverter circuit Expired JPS585596B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52139843A JPS585596B2 (en) 1977-11-24 1977-11-24 inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52139843A JPS585596B2 (en) 1977-11-24 1977-11-24 inverter circuit

Publications (2)

Publication Number Publication Date
JPS5473237A JPS5473237A (en) 1979-06-12
JPS585596B2 true JPS585596B2 (en) 1983-01-31

Family

ID=15254800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52139843A Expired JPS585596B2 (en) 1977-11-24 1977-11-24 inverter circuit

Country Status (1)

Country Link
JP (1) JPS585596B2 (en)

Also Published As

Publication number Publication date
JPS5473237A (en) 1979-06-12

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