JPS5857760A - Photo semiconductor device - Google Patents
Photo semiconductor deviceInfo
- Publication number
- JPS5857760A JPS5857760A JP56156282A JP15628281A JPS5857760A JP S5857760 A JPS5857760 A JP S5857760A JP 56156282 A JP56156282 A JP 56156282A JP 15628281 A JP15628281 A JP 15628281A JP S5857760 A JPS5857760 A JP S5857760A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- impurity concentration
- junction
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
- H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
- H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
- H10F30/225—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H10F30/2255—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers form heterostructures, e.g. SAM structures
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- Light Receiving Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は半導体光検出器に係り、特に高感度、低暗電流
高速性の実現に好適な受光素子に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor photodetector, and particularly to a light receiving element suitable for realizing high sensitivity, low dark current, and high speed performance.
従来は、第1図(a)および(b)に示すようにメサ型
あるいはプレーナ型構造の受光素子が提案されている。Conventionally, a light receiving element having a mesa type or planar type structure as shown in FIGS. 1(a) and 1(b) has been proposed.
半導体基板O1上に第1の導電型の半導体層02および
第2の導電型の半導体層03が形成され、更に電極08
.09が設けられている。第1図(a)の様なメサ型構
造では、高い電界が接合端面に露出することになるため
、表面保穫膜の性質によって素子特性が左右されること
になり、実用上望ましくない。一方、第1図fb)のプ
レーナ構造(公開特許公報昭55−1:32079号)
では、メサ型構造に比べて安定な動作が得られると期待
される。第1図(b)の構造では、InP半導体基板1
上にn+型InP層2 + InGaAsP層3.およ
びn型InP層が形成されている。6はたとえばCd拡
散層でこの拡散端面でpn接合が形成されている。7は
絶縁層、8.9は電極である。しかしながら、次に述べ
る様な欠点がある。A first conductivity type semiconductor layer 02 and a second conductivity type semiconductor layer 03 are formed on a semiconductor substrate O1, and further an electrode 08 is formed.
.. 09 is provided. In a mesa-type structure as shown in FIG. 1(a), a high electric field is exposed at the bonding end face, so the device characteristics are influenced by the properties of the surface protection film, which is not desirable in practice. On the other hand, the planar structure shown in Fig. 1 fb) (Publication of Patent Publication No. 1987-1:32079)
It is expected that this structure will provide more stable operation than a mesa structure. In the structure of FIG. 1(b), the InP semiconductor substrate 1
There is an n+ type InP layer 2 + InGaAsP layer 3 on top. and an n-type InP layer. 6 is a Cd diffusion layer, for example, and a pn junction is formed at the end face of this diffusion layer. 7 is an insulating layer, and 8.9 is an electrode. However, there are drawbacks as described below.
禁止帯幅の大きい物質としてInP結晶を適用する場合
、蒸気圧の高いPが結晶成長後の素子作成プロセスの熱
処理工程に於て解離し、表面層は変質することが考えら
nる。それ故に、表面保護膜形成後の界面特性は不安定
となり、暗電流が大きくなる原因になる。When an InP crystal is used as a material with a large forbidden band width, it is conceivable that P, which has a high vapor pressure, dissociates in the heat treatment step of the device fabrication process after crystal growth, and the surface layer is altered. Therefore, the interfacial properties after the surface protective film is formed become unstable, causing an increase in dark current.
また、一般に半導体物質では、有効質量や禁止帯幅が小
さくなる程、及び不純物濃度が低い程、トンネル効果に
よって降伏を起す電界強度は低下するため、禁止帯幅の
大きい領域(例InP)中に形成されるpn接合面と禁
止帯0幅の小さい領域(例、InGaAaP )間の距
離Iが小さい場合には禁止帯幅の大きい領域に形成され
たpn接合がアバランシェ増倍作用を起す前に、禁止帯
幅の小さい物質の電界がトンネル効果を起すに充分な電
界に到達してしまい、トンネル降伏を起してしまう。In general, in semiconductor materials, the smaller the effective mass and bandgap width, and the lower the impurity concentration, the lower the electric field strength that causes breakdown due to the tunnel effect. When the distance I between the formed pn junction surface and a region with a small forbidden band zero width (e.g., InGaAaP) is small, before the pn junction formed in the region with a large forbidden band width causes an avalanche multiplication effect, The electric field of a material with a small forbidden band width reaches an electric field sufficient to cause a tunnel effect, resulting in tunnel breakdown.
一般に、トンネル電流は次式で表わすことができm :
有効質量、 q:電子電荷素置、1i=h/2π:hは
ブランク定数、
N:不純物濃度
E2=:禁止帯嘔、f:誘電舊、b−e電界強度接合が
階段型であると仮定すると、電界強度と動作電圧(トン
ネル降伏電圧vT)との関係は次式%式%
一方、γノ(ランシェ降伏電圧vAは次式で与えられる
。Generally, tunnel current can be expressed by the following formula:
Effective mass, q: Electron charge element, 1i=h/2π: h is blank constant, N: Impurity concentration E2=: Forbidden flow, f: Dielectric pole, b-e electric field strength Assuming that the junction is step-shaped Then, the relationship between the electric field strength and the operating voltage (tunnel breakdown voltage vT) is expressed by the following formula.On the other hand, the γ(Lanche breakdown voltage vA) is given by the following formula.
いま、InGaAsPからなるpn接合を例にとってV
T=vAなる不純物濃度を求めると、下記の様になる。Now, taking a pn junction made of InGaAsP as an example, V
When determining the impurity concentration where T=vA, it is as follows.
I n P fE、燭λ: 1.35μm):
〜3X1017an−”In0.79()aO,21
”0.47 PO,53(”、対応λ−1,211m)
:〜2X10 crn
In0.7fiGa0.25”0.56P0.44 (
E、対応λ=t、3μm)〜7 X 1015釘−
In0.61”0.39”0.81PO,+7 (”、
対応λ:!1.55μm)8 X l 014offl
”
アバランシェ増倍作用が有効に起るためには、v、r>
v□であることが必要となるため、不純物濃度は上記値
よりも低くすることが必要となる。従って第1図(b)
に示すような構造にすれば、禁止帯幅の大きい物質の不
純物濃度とjによっては禁止帯幅の小さい物質の不純物
濃度に対する制限はやや緩和されるが、アバランシェ増
倍作用を期待するためには、禁止帯幅の大きい物質では
vT>vAなる関係が成立すると共に、禁止帯幅の小さ
い領域での最大電界E、、、は、トンネル降伏時の電界
強度E、r(不純物濃度によっては、アバランシェ降伏
時の電界強vEA)よりも小さくなるように素子設計を
行なうことが重要である。距離1と禁止帯幅の大きい物
質と小さい物質の不純物濃度を各々NL、N、 とす
れば、上述した条件を満たすためには、それらの間には
少なくとも次の関係を満たすことが必要になる。I n P fE, candle λ: 1.35 μm):
~3X1017an-”In0.79()aO,21
"0.47 PO, 53 (", corresponding λ-1, 211m)
:~2X10 crn In0.7fiGa0.25”0.56P0.44 (
E, corresponding λ = t, 3 μm) ~ 7
Correspondence λ:! 1.55μm) 8 X l 014offl
” In order for avalanche multiplication to occur effectively, v, r>
Since it is necessary that v□, the impurity concentration needs to be lower than the above value. Therefore, Fig. 1(b)
If the structure shown in is made, depending on the impurity concentration of the material with a large bandgap width and j, the restriction on the impurity concentration of the material with a small bandgap width will be relaxed somewhat, but in order to expect avalanche multiplication effect, , in a material with a large forbidden band width, the relationship vT > vA holds, and the maximum electric field E in a region with a small forbidden band width is the electric field strength E, r at tunnel breakdown (depending on the impurity concentration, the avalanche It is important to design the element so that the electric field strength at breakdown is smaller than the electric field strength vEA). If the distance 1 and the impurity concentrations of substances with large and small bandgap widths are NL and N, respectively, then in order to satisfy the above conditions, at least the following relationship must be satisfied between them. .
の故に、NLと4及びE7に相互関係がありNL及びN
8が小さい程、 1は大きくする必要がある。Therefore, there is a mutual relationship between NL, 4, and E7, and NL and N
The smaller 8 is, the larger 1 needs to be.
例えばNL=1 xl 016 Cm−31N、 =2
810”cm″″lの場合、λ== 1.55・μmの
InGaAsPに対してIは約1.5μm以上となる。For example, NL=1 xl 016 Cm-31N, =2
In the case of 810"cm""l, I is about 1.5 μm or more for InGaAsP where λ==1.55 μm.
この例の場合、上述した関係を考慮すると、1を1μm
以下にするような素子設計では禁止帯幅に対応する波長
が1.3μm、あるいは1.5μmに対応するInGa
Aspを禁止帯幅の小さい物質として用いた素子構成で
は、トンネル効果がかなり影響し、有効なアバランシェ
ホトダイオードを作ることは困難になる。In this example, considering the above relationship, 1 is 1 μm.
In the following element design, the wavelength corresponding to the forbidden band width is 1.3 μm or 1.5 μm.
In a device configuration using Asp as a material with a small forbidden band width, the tunnel effect has a significant effect, making it difficult to create an effective avalanche photodiode.
一方、第1図(b)構造のホトダイオードを作成する場
合には、動作時の最大電界は小さくなるものの、禁止帯
幅の小さい領域の不純物濃度には制限が必要となる。禁
止帯幅の小さい領域で空乏層がW広がると、禁止帯幅が
大きい物質側の禁止帯1の小さい物質の電界強度E8は
次式で与えられる。On the other hand, when producing a photodiode having the structure shown in FIG. 1(b), although the maximum electric field during operation becomes small, it is necessary to limit the impurity concentration in the region where the forbidden band width is small. When the depletion layer widens by W in the region where the forbidden band width is small, the electric field strength E8 of the material with the small forbidden band 1 on the material side where the forbidden band width is large is given by the following equation.
空乏層が(t+W)であり、Wが1μmとすると、E、
がE?を越えない様にするためには、不純物濃度N、は
下記の値よシも小さくする必要が生じる。If the depletion layer is (t+W) and W is 1 μm, then E,
Is it E? In order to prevent the impurity concentration N from exceeding the following value, it is necessary to make the impurity concentration N smaller than the following value.
N :く約I X 10膜6cm−” foeλ=1
.55μmく約2×10 cm fOrλ=1.3μ
m上述の如く、物質のE7とN8との関係を考慮する必
要がある。化合物半導体では、Siと比べて光励起キャ
リアの寿命が極めて短いため、光電変換効率を上げるた
めには、光吸収領域は空乏層化する必要があること、及
び高速化を図るためには、接合容量Cを小さくするため
、空乏層を拡げる必要がある。接合容量は近似的に次式
で与えられる。N: approximately I x 10 membrane 6cm-”foeλ=1
.. 55μm approximately 2×10 cm fOrλ=1.3μ
As mentioned above, it is necessary to consider the relationship between E7 and N8 of the substance. In compound semiconductors, the lifetime of photoexcited carriers is extremely short compared to Si, so in order to increase the photoelectric conversion efficiency, the light absorption region must be made into a depletion layer, and in order to increase the speed, the junction capacitance must be reduced. In order to reduce C, it is necessary to expand the depletion layer. Junction capacitance is approximately given by the following equation.
Cニー S (61j+W
a:誘電率 S:接合面積
実用上要請される量子効率(250%)、及び接合容量
(く2PF)を考えると、空乏層Wが1μm程度拡がる
ことは必要と考えられる。C knee S (61j+W a: dielectric constant S: junction area Considering the practically required quantum efficiency (250%) and junction capacitance (2PF), it is considered necessary for the depletion layer W to expand by about 1 μm.
本発明の目的は、前述した欠点を除去することにより、
高感変で暗電流が小さく、高速性の受光素子を提供する
ことにある。The object of the invention is to eliminate the aforementioned drawbacks,
The object of the present invention is to provide a high-speed light-receiving element with high sensitivity and low dark current.
本発明の代表例を第2図に示す。第1の特徴は能動領域
となる領土帯幅の小さい物質層13の上に光の窓層とな
る禁止帯幅の大きい物質層14を形成し7、更に、14
の物質の組成原子を含んだ多原子の物質層15を形成し
、表面保護膜17で保護することによって、半導体と界
面との間の安定化を図ることにより、暗電流の低下、並
びに界面安定化を図った受光素子構造を特徴とする。A typical example of the present invention is shown in FIG. The first feature is that a material layer 14 with a large forbidden band width, which becomes an optical window layer, is formed on a material layer 13 with a small territorial band width, which becomes an active region.
By forming a polyatomic material layer 15 containing atoms of the material composition and protecting it with a surface protective film 17, the dark current is reduced and the interface is stabilized. It is characterized by a light-receiving element structure designed to
また、第2の特徴はこれまで説明してきたように領域1
4の物質と領域13の物質の不純物濃度N14とN8.
の間にN、4≧N、3 の関係があり、Ntsが2
X 10”cm””3以下にすることを特徴とした受光
素子構造を特徴とする。In addition, the second feature is the area 1 as explained above.
4 and the impurity concentration N14 of the material of region 13 and N8.
There is a relationship of N, 4≧N, 3, and Nts is 2
The light receiving element structure is characterized in that it has a width of 10"cm""3 or less.
本発明による実施例の一つを第2図に示し、その構造を
以下に説明する。One embodiment according to the present invention is shown in FIG. 2, and its structure will be described below.
約10” cm−” 以上o高不純物濃度のn+形In
P基板、11.上に公知の液相エピタキシャル成長法に
より不純物濃度が9 X 10”Cm−” 、厚さ1.
5μmのn形InP層、12.を形成し、続いて不純物
濃度が7 X 10Il1cm−” 、 F’J、さ1
.3μmのn形”lLSI Gaall ASO,!I
s P、、17層、13.を形成する。特に1.3μm
以上の波長の光を受光を十分な感度で受光せしめるため
に、このIn1−XGa As P は0.4
7≧X≧0.25の組成がYI−y
好ましい。なお、A8含有量は一般にGaの含有量に伴
なって決定される。Approximately 10"cm-" or more o High impurity concentration n+ type In
P substrate, 11. The impurity concentration is 9 x 10"Cm-" and the thickness is 1.5cm by a known liquid phase epitaxial growth method.
5 μm n-type InP layer, 12. is formed, and then the impurity concentration is 7×10Il1cm−”, F'J,
.. 3μm n-type “lLSI Gaall ASO,!I
s P,, 17 layers, 13. form. Especially 1.3μm
This In1-
A composition of 7≧X≧0.25 is preferable. Note that the A8 content is generally determined in accordance with the Ga content.
y=
0.48043+0.00327X
の関係式が存在する。引続いて不純物濃度が9 X 1
0”cm”” 、厚さ1.8μmのn形InPli!、
14、を形成し、最後に、不純物濃度7 X 10”c
m 、厚さ0.2μmのn形In、、 Gacl、、
As、2P(La層、15.を連続的に形成する。A
l2O3及び5in2膜を公知の気相化学反応法によっ
て形成した後、公知の選択ホトエツチング法によって不
必要部のAl2O3及びS + 02膜を除去した後置
に領域15を除去し、上記絶縁物を拡散マスクとして公
知の拡散法によって、ZnあるいはCd不純物を上記領
域14及び15中に導入し、拡゛散深さ0,7μmのP
+形の拡散領域、16.を形成する。拡散層、16.と
InP層、14.によってpn接合が形成される。pn
接合面と領域、]3.との間隔は11μmである。次に
、拡散マスクとして用いた絶縁嘆を除去した後、公知の
方去によって5in2膜を形成する。公知の選択的ホト
エツチング法によって、不用部のSin、を除去した後
、表面保碩膜、17が得られる。尚。The relational expression y=0.48043+0.00327X exists. Subsequently, the impurity concentration is 9×1
0"cm"", 1.8μm thick n-type InPli!
14, and finally, an impurity concentration of 7×10”c
m, 0.2 μm thick n-type In,, Gacl,,
Continuously form As, 2P (La layer, 15.A
After forming the 12O3 and 5in2 films by a known vapor phase chemical reaction method, unnecessary portions of the Al2O3 and S+02 films were removed by a known selective photoetching method, and then the region 15 was removed and the above insulator was diffused. Zn or Cd impurities are introduced into the regions 14 and 15 using a diffusion method known as a mask, and P with a diffusion depth of 0.7 μm is introduced.
+-shaped diffusion region, 16. form. Diffusion layer, 16. and InP layer, 14. A pn junction is formed. pn
Joint surface and area, ]3. The distance between the two is 11 μm. Next, after removing the insulating layer used as a diffusion mask, a 5in2 film is formed by a known method of removal. After removing the unnecessary portions of Sin by a known selective photoetching method, a surface preservation film 17 is obtained. still.
反射防止膜17′、は表面保護膜を適用するか、あるい
は、反射防止膜として適した厚さのS iOtあるいは
Si、N4を再度形成して適用した。この後表面電極、
18.及び裏面電極、19を形成した。本素子は適切な
ステムにマウントさn1素子としての動作が認められた
。As the anti-reflection film 17', a surface protective film was applied, or SiOt, Si, or N4 was re-formed and applied to a thickness suitable for an anti-reflection film. After this surface electrode,
18. and a back electrode 19 were formed. This device was observed to operate as an n1 device when mounted on a suitable stem.
以下に本実施例の構成及び動作を説明する。本実施例で
は、禁止帯幅狭い領#R13が禁止帯幅の広い領域によ
って囲まれているため、入射光は領域13中で吸収され
層構成となっている。また、表面層は禁止帯幅の広いI
nGaAsP層で形成され、そのトに表面保護用の絶縁
膜が形成されてへるため、界面での特性が安定となり、
暗電流の低減に好適である。この表面層の半導体響けこ
の下層の第2の半導体層と(1)格子整合をとり得る、
(2)同じ結晶系をとり得ふ、(3)高温にさらされて
も?42の半導体層よりも安定である等の性質を持つ。The configuration and operation of this embodiment will be explained below. In this embodiment, since the region #R13 with a narrow forbidden band width is surrounded by the region with a wide forbidden band width, the incident light is absorbed in the region 13, resulting in a layered structure. In addition, the surface layer has a wide forbidden band I
It is formed of an nGaAsP layer, and an insulating film for surface protection is formed on top of it, making the characteristics at the interface stable.
Suitable for reducing dark current. This surface layer semiconductor layer can (1) be lattice matched with the underlying second semiconductor layer;
(2) Can they have the same crystal system? (3) Can they be exposed to high temperatures? It has properties such as being more stable than the No. 42 semiconductor layer.
又、この表面層は、能動領域の半導体材料よりバンド・
ギヤ、プを大なる組成を選択する。壕だ、pn接合は前
述した考えに基づいて領域13より離れて形成されてい
ると共に、不純物濃度分布も配慮されているため、ハー
ドな接合特性を維持し、かつ、光励起キャリアを効率良
く接合へ集めるのに適している。また、電界分布を考慮
して空乏層の広がりを設定しであるため、接合容量を低
減し、高速化に適している◎
本素子を逆方向にバイアスすると、空乏層は接合直下の
領域14及び領域13に広がる。このため、領域13の
禁止帯幅に対応した長波長端の光波長まで効率良く吸収
し1発生した正孔はドリフト電界によってpn接合に集
められる。本試作pin ホトダイオードの主な特性は
、波長感度領域1.0〜1.55μm+量子効率fy5
%(1,3μm)接合容量o、spF’+暗電流は0.
1 nA (t、oV)以下である。This surface layer also has a higher band band than the semiconductor material of the active region.
Select a large composition of gears and pumps. The pn junction is formed at a distance from region 13 based on the above-mentioned idea, and the impurity concentration distribution is also taken into consideration, so that it maintains hard junction characteristics and efficiently transfers photoexcited carriers to the junction. suitable for collecting. In addition, since the spread of the depletion layer is set in consideration of the electric field distribution, the junction capacitance is reduced and it is suitable for high speed.◎ When this device is biased in the reverse direction, the depletion layer is It spreads to area 13. Therefore, the holes that are efficiently absorbed up to the long wavelength end light wavelength corresponding to the bandgap width of the region 13 and generated are collected in the pn junction by the drift electric field. The main characteristics of this prototype pin photodiode are: wavelength sensitivity range of 1.0 to 1.55 μm + quantum efficiency fy5
% (1.3 μm) Junction capacitance o, spF' + dark current is 0.
1 nA (t, oV) or less.
本実施例の効果を以下に説明する。The effects of this embodiment will be explained below.
ial InGaAsP層と絶縁膜との界面特性を用
いることにより、低電流の低減できる。By using the interface characteristics between the ial InGaAsP layer and the insulating film, the low current can be reduced.
lb) 前述した様な層構成にすることにより、トン
ネル効果による暗電流の増大を防止できる。lb) By forming the layer structure as described above, it is possible to prevent an increase in dark current due to the tunnel effect.
(C) 前述した様な層構成にすることにより、光励
起キャリアを効率良く接合に集めることができ、高感度
化できる。(C) By forming the layer structure as described above, photoexcited carriers can be efficiently collected at the junction, resulting in high sensitivity.
+d+ 前述した様な層構成にすることにより、光励
起キャリアをドリフト速度で接合へ集めることができ、
高速化できる。+d+ By forming the layer structure as described above, photoexcited carriers can be collected at the junction at a drift speed,
It can be made faster.
(e) 前述した様な層構成とすることにより、空乏
層帽を広くとることができるため、接合容量を小さくで
き、素子の高速化に効果がある。(e) By forming the layer structure as described above, the depletion layer cap can be widened, so that the junction capacitance can be reduced, which is effective in increasing the speed of the device.
別の実施例として光の入射方向をInP基板側とした場
合がある。第3図がこの例を示す装置断面図である。第
2図と同一符号は同一部位を示している。層15が表面
保護のためのInGaAsP層である。第2図における
実施例との相違点は電極19が拡散領域16の下部に位
置する領域の金属を除去する点、および電極18は入射
光不要のため全面に設けられている。である。As another example, there is a case where the incident direction of light is set toward the InP substrate side. FIG. 3 is a sectional view of the device showing this example. The same symbols as in FIG. 2 indicate the same parts. Layer 15 is an InGaAsP layer for surface protection. The difference from the embodiment shown in FIG. 2 is that the electrode 19 removes the metal in the region located below the diffusion region 16, and the electrode 18 is provided over the entire surface since no incident light is required. It is.
また、上述の例としてInP−InGaAsP系材料の
例を説明したが、材料系はこれに限られるものではない
。Further, although the example of the InP-InGaAsP-based material has been described as an example above, the material system is not limited to this.
たとえば、14層としてGaAjSb 、13Mlとし
てGarb 12層としてGaSb 、15ffiとし
てGaAjAs8b を用いるGarbを主体とした材
料系を用いても同様の趣旨の光半導体装置が実現出来る
。For example, an optical semiconductor device having the same purpose can be realized by using a material system mainly composed of Garb, with GaAjSb as the 14th layer, Garb as the 13Ml layer, GaSb as the 12th layer, and GaAjAs8b as the 15ffi layer.
本発明によれば、素子の界面特性が安定化できる上に、
素子の禁止帯幅及び不純物濃度、厚さを考慮した層構造
になっているため、素子の電気的性質(暗電流、接合容
t)並びに光電変換効率の向ヒに効果がある。According to the present invention, in addition to stabilizing the interface characteristics of the element,
Since the layer structure takes into consideration the forbidden band width, impurity concentration, and thickness of the device, it is effective in improving the electrical properties (dark current, junction capacitance t) and photoelectric conversion efficiency of the device.
第1図は従来の素子構造例を示す断面図であり、(al
、はメサ型、(b)はプレーナ型構造を示す。第2図お
よび第3図は本発明による一実施例の素子構造の断面図
を示す。
符号の説明
n 1 ・−=−n+型InP基板、02 ・−−−−
−n型InGaAsn 3−・・・p形1 n()aA
s 、 08 e O9−・”電極、1 + 11 =
・=・n+形InP基板、2 ・−−−−n+形InP
層、12・・・・・・n形InP層、3,13・・・・
・・n形InGaAsP層、4114−・−・−n形1
nP層、6゜16・・・・・・p形In(3aAsP拡
散層、7.17.17’・・・・・絶縁膜、15・・・
・・・n形InGaAsP層、8゜18・・・・・・p
形電極、9.19・・・・・・n形電極!fJ+ 巴
葛 2 図
q
嶌 3 図
1θ
第1頁の続き
0発 明 者 倉口−宏
国分寺市東恋ケ窪1丁目280番
地株式会社日立製作所中央研究
所内
0発 明 者 古賀康史
国分寺市東恋ケ窪1丁目280番
地株式会社日立製作所中央研究
所内FIG. 1 is a cross-sectional view showing an example of a conventional element structure, and (al
, indicates a mesa structure, and (b) indicates a planar structure. FIGS. 2 and 3 show cross-sectional views of an element structure according to an embodiment of the present invention. Explanation of symbols n 1 ・-=-n+ type InP substrate, 02 ・----
-n-type InGaAsn 3-...p-type 1 n()aA
s, 08 e O9-・” electrode, 1 + 11 =
・=・n+ type InP substrate, 2 ・---n+ type InP
Layer, 12... n-type InP layer, 3, 13...
...n-type InGaAsP layer, 4114---n-type 1
nP layer, 6°16...p-type In (3aAsP diffusion layer, 7.17.17'...insulating film, 15...
...n-type InGaAsP layer, 8°18...p
type electrode, 9.19...n type electrode! fJ+ Tomoe 2 Figure q Sho 3 Figure 1 θ Continuation of page 1 0 Inventor Kuraguchi-Hiroshi 1-280 Higashi Koigakubo, Kokubunji City Hitachi, Ltd. Central Research Laboratory 0 Author Yasushi Koga 1-280 Higashi Koigakubo, Kokubunji City Inside Hitachi, Ltd. Central Research Laboratory
Claims (1)
りも禁止帯幅が広く、かつ第1の導電形を示す第2の半
導体層が設けられており、項第2の半導体上に第1の導
電形を示す第3の半導体層が設けられ、第3の半導体層
上に第4の絶縁膜が設けられた層構成があり、項第2及
び第3の半導体層の一部に第2の導電形を示す第5の領
域を選択的に設けたp’n接合を有すると共に、第2の
領域の不純物濃度は第1の領域のものよりも同等かそれ
以上に高く、かつ第1の領域の不純物濃度は2 X 1
016cm−”以下にすることを特徴とする光半導体装
置。a first semiconductor exhibiting a first conductivity type; and a second semiconductor layer having a wider bandgap than the first semiconductor layer and exhibiting the first conductivity type; There is a layer structure in which a third semiconductor layer exhibiting a first conductivity type is provided on top, a fourth insulating film is provided on the third semiconductor layer, and one of the second and third semiconductor layers is provided. It has a p'n junction in which a fifth region exhibiting the second conductivity type is selectively provided in the second region, and the impurity concentration of the second region is equal to or higher than that of the first region, And the impurity concentration of the first region is 2×1
An optical semiconductor device characterized in that the thickness is 0.016 cm or less.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56156282A JPS5857760A (en) | 1981-10-02 | 1981-10-02 | Photo semiconductor device |
| KR8204346A KR900000074B1 (en) | 1981-10-02 | 1982-09-27 | Beam-checking semiconductor apparatus |
| EP82109103A EP0076495B1 (en) | 1981-10-02 | 1982-10-01 | Photodiode |
| DE8282109103T DE3277353D1 (en) | 1981-10-02 | 1982-10-01 | Photodiode |
| US06/880,118 US4740819A (en) | 1981-10-02 | 1986-06-30 | Photo semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56156282A JPS5857760A (en) | 1981-10-02 | 1981-10-02 | Photo semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5857760A true JPS5857760A (en) | 1983-04-06 |
| JPH0420274B2 JPH0420274B2 (en) | 1992-04-02 |
Family
ID=15624407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56156282A Granted JPS5857760A (en) | 1981-10-02 | 1981-10-02 | Photo semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5857760A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132079A (en) * | 1979-03-30 | 1980-10-14 | Nec Corp | Semiconductor device |
-
1981
- 1981-10-02 JP JP56156282A patent/JPS5857760A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132079A (en) * | 1979-03-30 | 1980-10-14 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0420274B2 (en) | 1992-04-02 |
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