JPS5858031B2 - digital logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a digital logic circuit, and more specifically, the present invention relates to a digital logic circuit, and more specifically, a method for immediately generating pulses having a pulse number or frequency equal to the pulse number difference or frequency difference between two pulse inputs. This relates to a digital logic circuit that outputs data to a digital logic circuit.

(2) Prior Art Counting the number of two pulses for a certain period of time and finding the difference between them is a means necessary for A/D conversion and the like.

Generally, a method is used in which two counters are used to count two pulses independently, and then these results are digitally subtracted.

This method often has disadvantages in terms of circuit size and processing speed, such as requiring two counters and having to wait for the counting result before subtraction.

(3) Purpose of the Invention The purpose of the present invention is to solve the above-mentioned problem, and when calculating the difference in the number of pulses between two pulses, a pulse having a number of pulses or a frequency equal to the difference in the number of pulses or the difference in frequency between the two pulses is determined. Provides digital logic circuits that output immediately,
The object of the present invention is to enable high-speed counting of pulse number differences with a relatively small circuit scale.

(4) General description of the invention In order to achieve the above object, the present invention samples the other low-frequency pulse with the higher-frequency pulse of the two pulse inputs, and detects the presence or absence of that pulse.

A circuit system is adopted in which when a negative pulse of a low frequency pulse is detected, one pulse of the high frequency pulse is immediately erased.

The digital logic circuit that implements this method makes it possible to count differences in the number of pulses with a small circuit scale and high processing speed.

(5) Examples Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram of a digital logic circuit 1 of the present invention and an example of a time chart of input/output pulses.

Here, if the two inputs are φ and ψ, the output is ω, and the respective frequencies are fφ, fψ, fω, then the following holds true.

However, it is assumed that fφ>fψ. Alternatively, the following holds true for the number of pulses pφ, pψ, pω in a certain period of time.

The frequencies of φ, ψ, and ω may vary over time as long as at least the magnitude relationship (1) is maintained at each time.

FIG. 2 is a block diagram showing the circuit system of the digital logic circuit of the present invention.

In circuit 2, input φ samples the input ψ pulse,
Detects the presence or absence of ψ pulse.

From the relationship (1), it depends on whether ψ has at most - pulses in one cycle of φ, and if circuit 2 detects - pulses, circuit 3 should immediately erase the pulses of φ by - pulses. , the desired output pulse ω can be obtained.

FIG. 3a is a diagram showing an embodiment in which the circuit 1 of the present invention shown in FIG. 1 is constructed using specific logic elements.

Circuits 4 and 5 are D-type edge-triggered flip circuits 4.
The value of ψ is sampled and held by the circuit 5, and the value of ψ is sampled and held by the circuit 5 at the falling edge of φ.

These pulses are ψ1 and ψ2 shown in the time chart of FIG. 3, respectively.

The presence or absence of a rising pulse of ψ can be detected by the logic levels of ψ1 and ψ2. If it is detected during the low level period of φ (first half cycle), it is a pulse C1, and if it is detected during the high level period of φ (second half cycle), it is a pulse C1. C2, respectively φ
Erases the pulse of the next cycle.

This makes it possible to obtain the desired output pulse ω.

That is, when a pulse of ψ (say 22) arrives in the first half cycle (say 20) of φ (assuming the rising edge of ψ is the arrival of the pulse), ψ2 goes to a low level at the beginning of the first half cycle 20, and φ In the second half cycle 21, ψ1 remains at a low level, while ψ1 becomes a high level at the beginning of the second half cycle 21.

Once, the inverted signal ψ2 of pulses φ, ψ1 and ψ2
The Nant's gate 8 to which the pulse φ is input outputs a low-level pulse in the second half cycle 21, and this pulse is directly input to the flip-flop 12, and is also input to the flip-flop 12 via the Nant's gate 10 to which the pulse φ is input.
is input.

In other words, the presence or absence of ψ pulse in the first half cycle of φ is
It can be determined based on the output level of the gate 8 that if the output of the gate 8 in the second half cycle of ψ is at a low level, there is a pulse, and if the output is at a high level, there is no pulse.

This is simultaneously stored in the flip-flop 12 in the second half cycle 21 of φ, and the output of the flip-flop 12 is a Nant gate 14 to which the inverted pulse φ of the pulse φ is input.

15 and flip-flop 16 to bring C1 to a low level 23 in the next cycle.

When C1 becomes low level, it is detected that pulse ψ has arrived in the first half cycle 20 of φ, and by inputting C1 to the ant gate 17, pulse 2 of φ is detected.
4 can be deleted.

That is, the high level pulse of φ is canceled by C1,
This becomes the output ω.

On the other hand, in the second half of the cycle with φ, for example 24, the pulse ψ is 2
6, the next first half cycle 2 of φ
5, ψ1 is at a low level and ψ2 is at a high level, so the Nant gate 9 to which the pulse φ, the inverted pulse ψ1 of the pulse ψ1, and the pulse ψ2 are inputted outputs several levels during this first half cycle 25.

This low level is sent to the flip-flop 13, either directly or via a Nant gate 11 which is powered by a pulse φ, and the output C2 of this flip-flop becomes a low level 27 in the next cycle of φ.

Therefore, by inputting C2 to the gate 17, the φ pulse of the next first half cycle 28 can be erased.

As described above, when the pulse ψ arrives in the first half cycle of φ, the φ pulse is erased at C1, and when the pulse ψ arrives at the second half cycle of φ, the pulse φ is erased at C2, and the desired output pulse ω can be obtained.

In the end, according to this embodiment, the presence or absence of pulse φ is sampled at each rise and fall of pulse φ. , when there is a pulse ψ, erase the pulse φ of the next cycle, (11) There is no double pulse at the falling edge of the pulse φ in the previous cycle, and there is a pulse ψ at the rising edge of the pulse φ in the current cycle.
The pulse φ of the next cycle is erased.

By such a method, a pulse having a frequency that is the difference between the frequencies of two pulses can be obtained.

However, in order to apply this embodiment, the pulse φ(71
) The high-level and low-level periods of the pulse ψ must be equal to or greater than the high-level and low-level periods, respectively, but this is always satisfied when the duties of the two pulses are equal, so it is not practical. There are not many problems above.

FIG. 4 is a diagram showing a specific logic circuit a and its time chart b in another embodiment of the circuit 1 of the present invention shown in FIG.

That is, in this embodiment, the frequency dividing circuit 6 forms an upper frequency divided output history whose level changes every time the pulse ψ rises.

This 2 2 output color is determined by the pulse φ or the input edge) The flip-flop 7 of the IJ register samples and holds each falling edge of the pulse φ, and outputs the pulse a and its inverted pulse a.
get.

Each pulse a is φ. A flip-flop 8.9 of the same type sampling at φ forms a pulse a delayed by one cycle of φ.

Pulse a is generated every falling edge of φ (, Pa/L/, ;'J'
to sample.

The fact that the pulse a changes from a low level to a high level indicates that the pulse ψ has arrived, and the same is true when the pulse a changes from a high level to a low level.

On the other hand, it is assumed that the pulse ψ does not arrive while the level of the pulse a is not changing.

Therefore, the desired pulse ω can be obtained by erasing the pulse φ only in a certain cycle φ in which the pulse a changes from a low level to a high level and in a certain cycle in which the pulse a changes from a high level to a low level.

Therefore, in this embodiment, the pulses a and b are input to the exclusive OR gate 10, the pulse C is formed, and the pulse φ is gated by the gate 11 using the pulse C to obtain the target pulse ω. .

In this way, in this embodiment, since the upper frequency divided pulse is used, the advantage is that it is possible to always obtain a pulse with a frequency difference between the two pulses, regardless of the duty of the pulses φ and ψ. be.

In both the circuits of Figures 3 and 4, the time delay from the detection of ψ to the erasure of φ is at most one cycle of φ;
It may be assumed that ω with a frequency difference of ω is output immediately.

(6) Summary As explained above, according to the present invention, it is possible to obtain a digital logic circuit that instantly outputs a pulse having a frequency corresponding to the frequency difference between two input pulses or a pulse number corresponding to the pulse number difference. When counting the difference in the number of pulses between two pulses over a certain period of time, the circuit and counter of the present invention are extremely effective, as the counting results can be obtained immediately.

[Brief explanation of the drawing]

FIGS. 1a and 1b are diagrams showing a block diagram of a digital logic circuit of the present invention and a time chart of input/output pulses,
FIG. 2 is a block diagram showing the circuit system of the circuit of the present invention, FIGS. 3 a and b are diagrams showing the specific configuration of the circuit of the present invention and a time chart b of the waveforms of each part, and FIGS. 4 a and b FIG. 2 is a diagram showing another specific configuration of the circuit of the present invention and its time chart b.

Claims (1)

[Scope of Claims] 1. Means for sampling the level of the second pulse in synchronization with the first pulse, and from the previous sampling output and the current sampling output by the sampling means, between these two sampling points. means for detecting whether or not the second pulse has arrived, and means for gating the first pulse in response to the output of the detecting means, A digital logic circuit that outputs a pulse with a frequency that is the difference in frequency between the pulses. 2. The sampling means includes a second means for sampling and holding the level of the second pulse at each rise and fall of the first pulse, and the detection means detects the level of the second pulse at each rise and fall of the first pulse. , the first and second
and a third means for detecting whether or not the second pulse is absent at the falling edge before the rising edge and the second pulse is present at the edge edge, based on the output of the means, and the falling edge of the first pulse. Sometimes, the outputs of the first and second means
fourth means for detecting whether or not there is no second pulse at the rising edge before the falling edge and there is the second pulse at the falling edge;
2. The digital logic circuit of claim 1 comprising means for gating said first pulses one by one in response to each of the outputs of said means. 3 A circuit for upper frequency dividing the first pulse, a means for sampling the output level of the frequency dividing path in synchronization with the second pulse, and a means for sampling the previous sampling result and the current sampling result of the second pulse. means for detecting whether or not the first pulse has arrived between these two sampling time points, and means for gating the second pulse based on the output of the detecting means, A digital logic circuit configured to output a pulse having a frequency corresponding to a frequency difference between the second pulse and the first pulse. 4 The sampling means is means for sampling and holding the first pulse in synchronization with the second pulse, and the detecting means delays the output of the sample and hold means by one cycle of the second pulse. and means for detecting a mismatch between the output of the delay means and the output of the sample and hold means.