JPS5859672A - Picture signal processing circuit - Google Patents

Abstract

PURPOSE:To process a picture image data of a multi-mode such as reduction and expansion of a picture image, etc., by generating a mode signal for displaying both a main picture image and a sub-picture image from a mode designating signal generating circuit, and setting a special effect operating time to the minimum when the picture image data is inserted. CONSTITUTION:A luminance signal and a color demodulating signal of a sub- picture are converted to digital signals by A/D converters 1000, 2000, and its outputs are controlled by a sub-picture timing signal 124, and are inputted to field memories 1400, 2500. Subsequently, a main picture timing signal generating circuit 3000 generates a timing signal 126 of a main picture corresponding to a display mode, and a mode designating signal generating circuit 2900 generates a mode signal 125 for displaying both the main picture and the sub-picture. By this signal, a special effect mode read out in a buffer memory 1600, etc. is designated. As a result, the special effect operating time is set to the minimum when insertion of a picture image of a picture image data is designated, and after it has been designated, the quantity of a data of the display picture image area is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing circuit that performs image signal processing on nine or more inputted video signals (two to two), and sometimes performs multi-functions such as enlarging and reducing a projected image. Regarding image signal processing circuits suitable for performing 〇In general, special processing for image signals ζ includes processing to enlarge or reduce human-powered image signals to an arbitrary size and display them, rotation of projected images, static geography, etc. This is a typical example. Fig. 1 shows an example of image processing for displaying the projected image screen (=main screen l) and the open-rki2 in which the image data is reduced by data compression and displayed in synchronization with the main screen. In this case, the main screen (= synchronously displaying the sub-screen (:) requires processing to reduce the image data density of the input video signal corresponding to the sub-screen. Data interpolation processing is required for enlarged display.

FIG. 2 shows a conventional image signal processing circuit 11!1 for generating a compressed signal of input video signal data for the sub-screen 42. In FIG. 2, the sampling frequency is 47so (
The sample plane digital signal 3 with fmos color I11 carrier wave number 3s9MH is input to the input switching circuit 4 (two units t1).

This input switching circuit 4 supplies one field memory 7.8+==0 for each field (knee 1 screen digital signal via a signal path 5.6) and the data of these field memories 7.8 are transferred to a signal path 9. . When one field memory 7 is in write mode, the other field memory 8 is in read mode.
Performs *+i control. This (from 2, 1 field °
Each data is stored in 1 field memory 7.8 times,
Using this data, data 13 for open screen display is obtained.

On top of this, multiple one-field memories are used to create images (g
In the signal processing circuit, 1 field)'? Although it is possible to store the corresponding memory and perform correlation calculations on data between fields, the use of multiple field memories results in multiple address circuit configurations and the 62 operation circuit becomes complex. It has its drawbacks. Another drawback is that only a single correlation calculation can be performed.

The WCS diagram is a complete solution to the problem of having multiple 1-field memories in 9 circuits as shown in Figure 2.The analog video signal for displaying the sub-screen is a luminance signal, Y9, color difference R-Y, B-Yc converted, this 6 signal 14
is passed through the multiplexer 15]=0 is guided to the converter 16 Here, the output of the multiplexer 16 is the A/D
The sample is sampled at a sampling frequency of about 4 MHz (:, a 5-bit quantized signal 17 is obtained, and a good signal is extracted from this signal 17 according to the reduction ratio of the sub screen). The arithmetic circuit 184 is then extracted. In this way, only the data necessary for the reduced display is supplied to the field memory 20 via the signal path 19. The data written in the field memory 20 (2) is read out at a predetermined timing and guided to the buffer circuit 224 via the signal path 21 and stored in the buffer circuit 22I: The stored data is displayed on the main screen. It is read out via the signal path 23 at a synchronized predetermined timing, and is converted into an analog signal ζ by the V controller 2442, and the necessary signal is obtained from the signal path 25(2). In the conventional image signal processing circuit shown in (=), the field memo 9 circuit can be reduced, but the calculations related to it depend only on the sampling calculation circuit 18 (;, so the reduction ratio is determined by the sampling calculation circuit 18. The calculation function of the sub-screen C2 is restricted (for this reason, the reduction ratio of the reduction screen III that can be displayed on the sub-screen C2 is determined by the calculation circuit), and the degree of freedom in setting the reduction ratio is restricted. 9. The circuit shown in FIG. 3 (=Therefore, the function of enlarging and displaying the image of the sub-m plane cannot be achieved.

In addition, the image signal processing circuit shown in FIG.
”79 Michi.

Mmsudaetal ”Fully Digital
ized Picture 1nPicture Te
1evision on 8system''', but it still has the nine problems mentioned above.

The present invention has been made in consideration of the above points, and allows the main screen and the sea bream to be displayed with a small field memory capacity.

The object of the present invention is to provide an image signal processing circuit capable of performing multi-mode image data processing such as image reduction, enlargement, and static image processing on a screen.

(Summary of the present invention) The present invention provides a predetermined horizontal,
- Sampling signals in direct cycles, performing a first correlation calculation on these signals, writing this result into the field memory, and performing a second correlation calculation to control the heeling data from the field memory. One of the main points is to control the size of the projected image.
By selecting a combination of the first correlation calculation and the second correlation calculation, the size of the displayed image can be controlled, and the image can be reduced or enlarged using a small field memory. In invention, Eirin signal (; against.

The above correlation calculation is performed between adjacent picture elements to increase the correlation of data to be complemented by the correlation calculation. The image signal processing circuit according to the present invention can compress and expand sampled data by performing the first correlation calculation on the input image signal 1 and then performing the second correlation calculation. That q! Performing one calculation of the i characteristic multiple times via the field meter makes it possible to reduce or enlarge the projected image by controlling the data compression ratio or data expansion ratio. It means that. Also,
If you stop writing to the field memory and continue reading it, it will stop and you will get a 9-picture payout, but in this case, by using a new circuit configuration for address access to the field memory IRC2, you can use a multi-mode ( ◎In other words, the present invention uses the input video signal to sample the data C: and performs the correlation calculation and interpolation of the data to the field memory C. Multi-mode image display can be achieved by efficiently performing Akuryūsu.

FIG. 4 shows the display positional relationship of images processed and displayed by the image signal processing circuit in this embodiment.

Now, assume that there are a video signal 211 as the main signal and a video signal 211 as the sub signal as the signals to be displayed. In the figure, under normal conditions, display device C
The entire surface of the carp is displayed, and a sub-screen is inserted and displayed. This inserted screen is usually displayed at positions P to P4 in the same figure, and is displayed in a size ranging from approximately the size of a 6-screen screen to the size of the entire screen. In addition, the display position of the IQlili screen is other than the above; the position of the center ring of the screen w6
: Can also be set and C: Reduction or enlargement can be displayed. ◎ The displayed image can be displayed using Field Mesori (where writing of a pair of image data is stopped and continuous output is continued). In this case, the main display image can be stopped for either the main screen 1 or the sub screen (◎) The reduction or enlargement display of the input image signal is performed by the first and second correlation calculations (2). In,
Perform the correlation operation of MTl on the input side of the field meter,
Performing the second correlation calculation on the output side has the effect of increasing the degree of freedom in reduction and expansion. In other words, the size of the display screen is controlled by controlling the calculation contents of the first correlation calculation and the calculation contents of the second correlation calculation (determined by the two). be done. This ml
The first correlation calculation and the second correlation calculation are performed on both the luminance signal and one color separation code.

Figure s5 shows a first luminance signal calculation circuit that performs the first correlation calculation performed on the luminance signal on the input side of the field memory. The first correlation calculation for the luminance signal performed on the input side of the field memory 134 is performed in the horizontal and vertical directions (as is the case with the second correlation calculation described later), but the correlation calculation circuit described in this embodiment It is better to think of it as a representative value generation circuit with a linear circuit and a gain of 1, rather than as an instantaneous companding circuit. In the figure, the nine portions surrounded by broken lines are the first luminance signal calculation circuit 130G that performs the correlation calculation of lit with respect to the luminance signal 4. This first luminance signal calculation circuit 1300 is an analog The luminance signal is converted into a sampling pulse φ0.
A signal quantized by 000 is input ◎This sampling pulse is normally 37so e 4/so (
/so=&5814(g) 6 tL is 4407M (/M= 15.75 kHz) 4 in this example
Second, simplify the configuration of control system circuits such as line memory and field memory.

The output of the above ~Φ converter tooo is the latch circuit 37
0, weighted by 1/8 via the latch circuit 371, and supplied to the front and rear adders ΣYbH2. 9. The above Y1 converter 100G has a data width of 2 to 1 IH period (IH) delay operation, $1 IH memory 260, @2(7)I
H/'&S261.9f circuit 8B0.5ch circuit 38
! After passing through ΣYis, it is weighted by 178 and is supplied to an adder ΣYis. The output of the lH memory 260 is signal-weighted via latch circuits 374, 376, 378, and supplied to the adder ΣY1g.
The output of the latch circuit 374 is weighted by IA and supplied to the adder ΣY.
iIH: As supplied (:, the adder ΣY with the weight of i
is supplied. And the second latch circuit 376
The output of ΣYim, ΣYtz 1 and the three-state circuit 4o56 are supplied with a weight of H.

Furthermore, the three-state circuits 406 and 407 are the three-state circuits 405, 406, and 407 whose inputs are the outputs of the adders ΣYI+ and Σstone, respectively.
2, a first correlation calculation result is obtained, and this □ result is written into the field memory 134. In □, the first correlation calculation performed on the input side of the field memory will be described. The first correlation calculation is performed based on the data sampled by the above-mentioned ~Φ converter 1000 (2), but which data is used to perform the next correlation calculation depends on whether the image is enlarged or reduced. The ratio to be used differs depending on the situation. In other words, the correlation calculation is performed using the processing mode for image 6 (=
Therefore, when the correlation calculation formulas correspond to each other, the sampled data to be calculated as i=is determined.・The designation of the correlation calculation according to this mode is performed by the three-state circuit 4051.
406゜407 H To the supplied mode signal +m:I
It is determined by m, 41111 j rn@+<6=. The first correlation calculation is performed according to the mode determined in this manner, but since this correlation calculation is essentially a representative value addition, the calculation process is based on the difference in sample times. The sampled data is the subject of calculation.

In FIG. 5, latch circuits 370, 374, and 380 function simply as latch circuits for latching sampling data.
8 functions as a delay circuit that delays data by one hour τ in the horizontal scanning direction. Also, 1 of #11 1 memory 2
601 second 1) 1 memory 261 stores l line period 1/
It operates as a delay circuit that delays data by fu. In Figure 5, the signal delayed by 2 twins relative to the current line (2) is T,
The signal delayed by 1 line is indicated by M, and the current line signal B is indicated in the horizontal direction (the two are +1 for the current signal. The signal delayed by time τ relative to the current signal (: is 0, the current signal -2 is delayed by no Good signal 1: is given a subscript of -1 @Based on the good signal defined in this way, mode 1: The first correlation calculation to be performed (= will be described next. The thin ice coefficient obtained by the correlation calculation of 1 is expressed as Hdi in the horizontal direction and Hdi in the vertical direction (=
It is assumed that is Vdi.

[Me mode] First, the main rigid surface is a normal analog signal (in the second animation,
Modes m and 6: in which nine strokes are displayed in a smaller size by performing digital processing on the sub-screen will be described.

In this mode (2, Hdl = %, Vd = 1, reduction coefficient Hdl is 54M + 34 (M - Kameko M + 1)
...Song (i) Correlation operation C: Yo... can be known. That is, with this word m., no reduction is performed in the vertical direction. In addition, in the horizontal direction, the latch circuit group and the is 2nd 1. ii. By controlling the memory, extract only the corresponding data as shown in Figure 6 (a) 4:, (:1.
An operation is performed on the expression. This calculation (=Therefore, each of the data M, , M+ in Fig. 6 is not weighted by shi≦, this is 1; the data obtained by adding the weighted h to the data area 0 itself is obtained as interpolated data 0 Note that the reduction coefficient Vid =xl in the vertical direction corresponds to the fact that in the horizontal direction in FIG. 6, data is discarded every time T (twice), but data is not discarded for every 42 times in the vertical direction.

[M-mode]

Next, let's look at mode m in which the main screen can be a normal analog signal: 1. The main screen is a digitally processed zoom-up image, and the size of the image can be reduced.

In this m-position mode, the data obtained by the ~Φ converter is extracted and this data is obtained as the output of the adder ΣY1g. Then, this data is stored in the field memory 134 without being discarded.

Therefore, in this mode the reduction factor at the input side of the field memory 134 is Hdi = 1. Vdmu=:1.

In the above two modes m and 9m, the main m plane processes the normal analog signal, but the next mole-processed image signal is displayed. The main screen displayed is shown in Figure 7 (
= % of the total signal on the display screen shown The hatched area (corresponding data) is zoomed up and displayed on the entire screen (; In this case, the hatched area (= data to be displayed) on the display screen in Figure 7 is Similarly to the above-mentioned mode 9m, data corresponding to data M(2) is sampled as a pigeon, extracted by adder ΣY1, and stored in field memory 134. The correlation operation and (;
Therefore, the data corresponding to the shaded part (2) in the full-screen Meijido 7 figure is zoomed up and displayed. - In this mode ml, the data in the displayed part is not rejected, and the reduction coefficient is Hd Todoro = l, As will be described later, since the shaded area in FIG. 7 is zoomed up by a factor of 4, the interpolation of the data is determined by the second correlation calculation.

[m:mode]

Mode 4: Mode m: is a mode in which the main screen zoomed up in the above-mentioned 97th Street is made to stand still, and then the sub-screen signal is led again to enable the insertion of a sub-screen. In this mode, since the image signal corresponding to the 1111 screen (2) is displayed in a reduced size, the first phase t!A operation is performed to reject and reduce the data on the input side of the field memory.
, the data to be subjected to the first phase pA calculation in the 7 mode uses three lines of data as T, M, and B from the converter 1000, as shown in FIG.
0 These data are also subjected to a correlation calculation of two pairs of Ml to obtain a reduction coefficient Hdi = 1/8.
(= indicates. That is, T@ g jJ −@ @ pigeon, M4
1, B, 4=Based on 5 types of data provided by Osho (:
1/2 Me+ 1/8 (T・+B@+M+1+M-
Data reduction is performed by discarding predetermined data among the data obtained by performing the correlation calculations 1)...(2).

(m: mode) Next, the main screen displays a still image with the image motion stopped on the entire screen based on the digitally processed signal. For this reason, the reduction coefficient for the human side of the field memory 134 is set to kidihVdi = l.Such a reduction coefficient is equal to the case of the above-mentioned - mode, so first The above formula (1) C shown in FIG. 6(a)
A reduction calculation of the mode of mz is obtained by a two-by-one correlation calculation.

[m-Hatake Mode] The m-naru mode is the above-mentioned mJ mode, and is a mode in which a digitally processed and reduced sub-screen is inserted into the main screen displayed in a static state. In this case, in order to reduce the sub-screen to be inserted, the reduction coefficient at the input side of the field memory 134 is I(dm=, Vd1=%). Target the data shown:,h
M, 10% (-T, +B.+M+z +M-■), which is obtained by performing the same correlation calculation as in the above Ene mode.

The mode of correlation calculation on the input side of the field memory 134 in this embodiment is as described above (2ff16s
ml*town, m, j, m:, ml mode can be defeated. Then, the first correlation calculation is performed by the luminance signal calculation circuit 1300 (2).If the correlation calculation is a calculation of data interpolation, the luminance signal calculation circuit 1300 of the gt When the correlation calculation is such that data is rejected, the first luminance signal calculation circuit 130G
functions as a low-pass filter for the data of the ~Φ゛ converter 1000. The 1ml correlation calculation for each mode is switched using a latch circuit.

The first correlation calculation is performed by controlling the 18 memories of the three-state circuit and gtsz according to the type of mode signal supplied to the three-state circuit. On the other hand, the luminance signal calculation circuit 1300 of the side 1 (field memory 13
4 is stored. The luminance signal data stored in the field memory is sampled by an M2 luminance signal arithmetic circuit (to be described later); therefore, a correlation computation process is performed. A second correlation operation is performed to interpolate data or reject data.This 1@2 correlation operation functions isometrically as a data (2 vs. 2) high-pass filter or low-pass filter. Therefore, the above ~ conversion l
The output of l1000 is ζξ(
Two. In this way 1. ~/p converter 1000 (the luminance signal data sampled and quantized is
The first and second correlation operations (: thus digitally processed to obtain proper data for the mode of reduction or enlargement of the movie).

Here, the second luminance signal calculation circuit (two luminance signal calculation circuits) that perform the second correlation calculation will be explained.

In FIG. 8, the dashed line portion is the luminance signal calculation circuit 150 of !2
Similarly to the first luminance signal calculation circuit 1300, the second luminance signal calculation circuit 1500, which has the opening indicating 0, calculates the current line signal B in the fl direction, and the signal T-゛1 delayed by two lines from this (2). The correlation calculation target is the delayed signal M.In addition, in the horizontal direction (when the data sampling period is T), is the calculation target in the horizontal direction.In 2:ζ, +11 current signal C2 with respect to the current signal is delayed by time T and the good signal is delayed by 01 hours 2τ signal 12 is marked with a saturation character of -1. Due to the circuit configuration, the mode of calculation performed by the second brightness signal calculation circuit 1500 is that of the first brightness signal calculation circuit (more than two), so the adders that add the weighted data are ΣYOI to ΣY , and the number of adders increases, and the accompanying adder ΣYa
The main circuit difference from the first luminance signal yL calculation circuit is that a three-state circuit for switching and controlling data such as t to ΣY06 is provided. However, this difference is due to the fact that the second luminance signal calculation circuit has a large number of correlation behavior modes, and is composed of a latch circuit that latches the calculation result, the first IH memory 802, and the IH memo 804 of g2. There is no fundamental difference between the two in regard to the circuit configuration 6 of the part that generates the data to be computed for the correlation computation to be performed. Additionally, the adders ΣY01 to χY0. The weighting coefficient for the data added in #I8 is shown in -2 in the diagram. The latch circuit group is driven by the clock pulse of m01, and the 1e2 IH memory 8o2-804 is driven by the clock pulse of 440/, and the mary state circuits 840 and 842 are driven by the clock pulse of m0.
1 clock pulse, the three-state circuit 84o.

842 is driven by a clock pulse of 2φ01.

5. The M2 luminance signal calculation circuit 1500 includes the first luminance signal calculation circuit 1500.
A second correlation calculation is performed based on the data in the field memory 134 in which the correlation calculation results performed by the luminance signal calculation circuit 1300 are stored, and thereby the reduction coefficient p on the output side of the field memory 134 is Hdo, Vd
o is calculated. Once the reduction coefficients, Hdj, Hdo/Vdi, and Vdo on the input/output side of the field memory 134 are calculated, the screen size of the display screen is determined. The reduction coefficient by the second correlation calculation is performed in accordance with the mode of the first correlation calculation described above. Next, the mode m@@ri on the input side of the field memory 134 described above
g B m11 mbm61 ml each mode (;
The output side mode (two modes will be explained), and the second correlation calculation in this case will be explained next.

(Mode m, (two modes)) The first mode is a mode in which a sub-screen, which is a digitally processed sub-screen signal, is inserted into the main screen which is displayed using normal analog signals. In mode m@@, the subscreen is displayed at the size of the L'16 screen, depending on the size of the subscreen to be inserted.
: There are 3 mode settings: mo, which displays the sub screen.

o mo, mode This mode makes the sub screen the main screen 1/16iIkiiiJ
This is a mode in which the reduction coefficient Hdj = % and Vdi = 1 have already been determined on the input side, but the reduction coefficient on the C1 output side is Hdo = li,
By setting Vdo = %, it is reduced and displayed on the "/161jj plane. In this case, the reduction coefficient H@='si is the horizontal direction I: 1 from 2 picture element data of the data read from the field memory 134. Similarly, by generating interpolated data with one reduction coefficient, 0 can be obtained.
a)-2 is shown. Note that the data to be subjected to the second correlation calculation to obtain this interpolated data is '-s + 'o *
This is 4 pixel data of m, , *B. These four data (54M for 2, 10%Be+S4(M+x +M
-1) ......(3) Perform the calculation 1; Obtain the interpolated data of the adder ΣY,, 1: m, and Oo fn. In this mode, the sub-screen signal is Digitally process and reduce the 9 sub-screens by % screen C2 and insert them into the main screen as in the - mode above. The reduction coefficient on the input side is Hdi=, and the reduction coefficient on the output side is Hd for Vd1=l.

:=l, Vd0=% Toshioni (=0 to get a reduced subscreen
@9IA(b) ('-1 as shown; The target data for the second correlation calculation is the third pixel data of M, , T, , B. In this case, the second correlation calculation is kM , +X(T・+B
(+)...It is indicated by (4).

a m, Crow mode In the above two modes 5, -do m, Hoi, and m-1, a sub screen was inserted on the main screen, but in this mode, the size of the sub screen to be inserted is displayed in full screen. . In other words, the subscreen is displayed on the entire screen, and the reduction ratio of the subscreen is 1.0 However, the reduction ratio on the input side is 1 (di = %, Vd
i = 1 Toshitail (7) '1? , on the output side, it is necessary to perform an operation to set ldi=,2 in the horizontal direction (= is the reduction coefficient). That is, on the input side, by setting Hdi=%, the data density of the picture element becomes (-), so on the output side, the horizontal direction C2 and # element data are interpolated, and the resulting horizontal picture element data is It is necessary to set the density to 1. In this way, in this mode, a correlation calculation is performed in which the data read from the field memory 134 (2) is doubled, and the data density is doubled (2). means to generate new data from the data retrieved from the field memory 134.
) indicates that in this mode, a new picture element data density, represented by two squares in the horizontal direction C, is generated and the picture element data density in the horizontal direction is doubled. As can be seen from the figure (in the two-fold direction (; indicates that no interpolation of pixel data is performed, so the reduction coefficient Vdo on the output side is Vdo = 1.
The above-mentioned calculation of doubling the picture data density in the horizontal direction by setting the reduction coefficient on the output side to Hdo = 24 is obtained by calculating the picture element data M, . . . M41 as the calculation object. The calculation in this case is Si ('o+M+*)...
... is shown in (5). In this way, in this mode, the reduction coefficient on the output side is Hdo = 2, Vd
By setting o = 1, the sub-screen can be displayed on the entire display screen using horizontally interpolated data.

(Mode for mode m) This mode is a mode in which the sub-screen signal shown in the diagonal line part I shown in FIG. be.

In mode mo42, three modes are set depending on the size of the sub-screen to be inserted: mode m for /16 screen display, mode m for 19% screen display, mode m for full screen display, and so on. In the mode device, the reduction factor on the input side is Hd
! =1. Since Vd1=1, the above m@, , m
,, .

ffho (/3 The size of the inserted screen is determined by the reduction coefficient on the output side of the three modes.

mo, mode This mode ridge sub-screen image data storm data 4 versus @2 brightness signal calculation) reduction coefficient Hdo, Vdo Hdo = %i, Vdo- = % through E-)
'is. ζNow, when extracting the data of the sub-screen, 62% of the data of the full screen is not extracted as shown by diagonal lines in Fig. 7, so the reduction coefficient of the image data is Hdl=
1. Vd1-1 (note that the tail is compressed by two in the tail).

This means that the screen reduction rate is 1 on the input side, but the image data reduction rate is 1. Therefore, the reduction coefficient on the output side is Hd.

= % and Vdo = %, a screen with a size of 6 (%) IXX) of the full screen is displayed.

Further, the content of the displayed image is %(1xlx%x%). In this mode, the calculation target of 312 correlation calculations is:
Figure 9(d) (T@ , B, , M, as shown in Figure 9(d))
,M.

This is Mal's five picture element data. Then, the second correlation calculation using this data is performed by the second signal calculation circuit 翿=(T,-)H・10M+M-1)...
...(61(: To be carried out accordingly.

m, mode This mode is a mode in which the reduction coefficient on the output side by the second correlation calculation ζ is Hdo x l , Vdo = l. As mentioned above, on the input side, the reduction coefficient force H
di = 1, Vdi = 1”eA40)C
No compression of the data corresponding to the image data is performed. However, on the input side, only the symbols of all the staff data on the sub-screen are extracted as shown in the diagonal line part (=) in Figure 7. Therefore, - is extracted in Figure 7 as a result of the correlation calculation. The image will be displayed on the special screen (-).

Therefore, the nine image data extracted by the ψ converter 00 in the t45 diagram are used for image display without interpolating or discarding the data.

Shin ml. Mode In this mode, from the second correlation calculation, the reduction calculation coefficient on the output side is set to 1 (do = = 2e vd'-2).
This is Cm, as shown in Figure 9(e) (: As shown in Figure 9(e), 1 field memory 34 extracts the data of 4 points marked with circles, and the data of 5 points marked with squares are interpolated. In this case, the displayed image is displayed by enlarging the imm of the electronic screen of the sub-screen shown in Figure 7 by 1 kit = a times C - 0 The data to be interpolated is the data M @ ,
M+, l: data for which the calculation of pair-shiK (Mo+M+z) is performed, similarly data B・, B1 and 3 ((
a, +B+t) data, data B
e v Bus @ T @ t T+1 (% of 2 (
B, +H◆, +T, +T+1)... Data, data T,, B, on which the operation of (7) was performed.

Data obtained by performing the operation of M (T 10 no) on C2,
Similar to this, Kan2 data T + 1 * B + 1 and No. (T
+1+'+1), which is the five data of the data, and then the data's! Mal ＞
Display m t- is obtained from 9 data including 4 data of H@*Bat.

(Mode for mode mll2) Let the reduction coefficient of the input side be l(d i −1e vd k
For mode m where = ', the reduction coefficient is 1do = 2 on the output side, and the town / town screen with Vd6-2 is associated. times (the knee is enlarged and the nine videos are displayed in full. Furthermore, the reduction factor H
do=2. Vd.

= 2 (2 is the above code ml. Similarly to Fig. 9 (
C) (=9 Perform data interpolation.

(Mode ml 2 vs r mode) Mode ml is a mode for inserting a sub screen into the digitally processed main screen image. 2+-Vdo=
This corresponds to mode mfi set to 4. Since the reduction coefficient on the input side is Hdi= and Vd1==%, a 146-sized sub-screen of the entire screen is inserted into the main screen displaying the digitally processed signal. The calculation for determining the reduction coefficient on the output side in this mode is the same calculation as in the above mode m1.

(Mode for mode m) In this mode, the main screen signal is digitally processed and displayed in a stationary state. This mode:
(For two pairs, find the reduction coefficient on the output side and perform the operation −f−−
)'42, 'reduction% number wo Hdo = 2. Vdo=
In this case, the reduction coefficient on the input side is Hdi=I and Vd1=1, so
The main screen image is displayed on the entire screen.
A calculation similar to the second correlation calculation performed with a plow (two-dimensional calculation).

(Mode for mode M1) Set the reduction coefficient on the input side to 1 (di=, Vdi=M, and insert the sub screen into the stationary main screen). 1'(do = 2*Vdo
71 and mode m4o are made to correspond. Correspondence 6: In a certain mode, an image of the still main screen image screen: the llIllilli side of the moving image is inserted and displayed. The second correlation calculation performed in this case is obtained by the same calculation as the calculation performed in the mode m16 described above.

As mentioned above, the combination of the JIH calculation mode performed at the input end of the field memory 134 and the calculation mode performed at the output side (screen display of modes 2 to 10 is possible/displayed). The field memory 134 (=
By controlling the storage status of the image data for the image data, it is possible to stop the writing of the 9th illustrator data to the field memory 1344 and continue to look at the current illustrator data. , Figure 8 above (
= Indicates that the brightness signal calculation circuit of 9M2 performs calculations to obtain a stationary 6V. The correspondence between the combinations of calculation modes on the input/output side of the field memory 1$4 described above is shown below (2@i2).

As mentioned above (=, in this practical example, image signals are processed in a wide variety of modes. The problems are how to carry out the multi-mode correlation calculation with a small memory capacity.These problems will be solved in the following (1=Detailed Means-2).

FIG. 1O shows a system block diagram of an embodiment of an image signal processing circuit according to the present invention that performs 1lkI image signal processing according to the mode shown in the table above. Here, 1. Digital processing of the overlapping image signal is performed by the circuit shown within the broken line in the figure.

In the image signal processing circuit shown in FIG.
A screen control receiving circuit 51 that optically transmits channel selection signals for the ii screen and sub-screen, signals specifying the strength of the audio (to be described later), etc. The screen control receiving circuit 51 receives the transmitted signals. A microcomputer is used in the decoder 53 to decode the input data 52 and output the signals corresponding to the transmitted signals 54, 5L, 56t, and the channel selection signal 57. 58
．． Operation mode control signal 59. The audio IF signal is outputted to each predetermined circuit. Also, fL obtained from the antenna 60
The P signal is guided to tuner A 61 and decoder circuit 5
The channel determined by the channel selection signal 58 of No. 3 is selected. The output 62 of this tuner 61 is guided to an IP detection circuit 63, and the IF detection circuit 63 receives the audio IP signal 64.
．． A video signal 65 is output. Here, audio IF signal 6
4 is guided to the audio circuit 66, and 1=the audio output 67 is guided to one input terminal of the audio switching circuit 68. The other input terminal of the audio switching circuit 68 is supplied with the output 0 of the audio selection circuit i9. Then, the decoder circuit 53
According to the audio switching signal 54, the audio output '11
．． 72 is obtained. The output cuff 1 of the audio switching circuit 68 is led to the main screen speaker 734 2, and the other output cuff 2 is led to the earphone 744;
Reference numeral 5 indicates a video signal switching circuit 75 (which is operated by two people), and a video signal switching circuit 75 (which is operated by two people), and a video signal from the video signal switching circuit 87 is also supplied. , the video signal switching circuit 75
selectively outputs a video signal 77 for the main screen and a video signal 78 for the sub screen.

Previously, from the 9 BP signal obtained by tuner B 79, the channel selection signal 57 signal (=therefore, the corresponding channel is selected.
1, and its detection output 82 is audio 1? (No. 11 and audio circuit 831 = supplied.

The audio signal 84 is then guided to the audio switching circuit 74. In the figure, the other input of the audio selection circuit 69 is an external audio input 8.
It is 5.

Here, the video signal selection circuit 81 = guided video 86 and external video i 88 are connected to the decoder circuit 53I.
: The video signal is selected according to the selection signal 56, and a video signal, signal 76, is obtained. In this 62, system 62 of the 1st ruler, the Tuna people.

61 or Video 16 obtained by tuner 8.79 (not limited to 2) - Zero-order (2) video signal processing that can also handle input signals 85.88 from external inputs, such as VTfL, video discs, etc. Specifically, the main screen video signal 77 is guided to the main screen luminance signal processing circuit 89, main screen color signal processing circuit 90C; -YO2゜R-Y
Get 93. The main screen control circuit 94 transmits control signals 95 and 96 for controlling the display image mode to the main screen brightness signal processing circuit 89. A main screen color signal processing circuit 90 is supplied to perform control glkh operation. Regarding the synchronization system, the main screen synchronization signal extraction circuit 97 extracts a horizontal synchronization signal HM 8YNC'gg and a vertical synchronization signal VM 8Y from the input video signal 77.
Separate NC99.

Then, the sub-screen luminance signal 78 is supplied to the sub-screen luminance 4F1 processing circuit mioo, the sub-screen color signal processing circuit 101, and the synchronization 111 extraction circuit to24:,m.

The subllll1 screen video signal 78 is sent to the subscreen luminance signal processing circuit 100. mlii side color signal processing circuit 101, synchronization signal extraction circuit 102, and the sub screen fbllh
ill03 generates a signal 1041105 that controls the luminance signal processing circuit 1009 and color signal processing circuit 101.

The luminance signal 106, which is the output of the sub-screen luminance signal processing circuit 100, is converted into a digital signal (2) by the Φ converter 1000. -Y signal 1071 B-Y 4
The signal G 108 is multiplexed at a predetermined timing by a multiplexer 110t.
09 is for color signal ~ Φ Compa-I! (; Guided. Above V
1> Converter 1000.1200 input signal at sampling frequency φm = 8807M1 (/Ml:
The output 111 of the ~Φ converter 1000 is s AT l
The first correlation calculation is performed by the luminance signal calculation circuit 13LJL). The result of this first correlation calculation is stored in the luminance signal field memory 1400. The data in the field memory 14L)0 is input to hill fMl by the signal 113i2 of the address generation control circuit 3100.
The extracted data is stored in the field memory 14.
On the output side of 00, the second brightness calculation result 115 is led to a buffer memory 1600.

In this way, C=1. By performing a two-step (two-way correlation calculation) on the turnout side 1 of the field memory 400, it is possible to set the display state of multi-mode images as shown in the table (2) described above.

The backup memory 16oO is read out at a predetermined main screen cycle, and the read buffer memory output 115 is
The luminance signal 117 is guided to the A converter 700 and taken out as an analog signal 117.The luminance signal 117 converted into an analog signal C is amplified by a buffer amplifier 1800 and outputted from a luminance signal switching circuit 19001.

On the other hand, the 8-Y and B-Y digital signals of the nine color signals multiplexed by the multiplexer 1100 are digitally converted by the ~Φ converter 200. converted to digital. The digitally converted signal 110 is subjected to a first correlation calculation in a first color signal calculation circuit 2400, and the data is stored in a field memory 2500.
4 The door is varnished. A second correlation calculation is performed using the data read from the field memory 2500, and the calculation result is sent to the R-Y/A-coder 2000 HR-Y signal 118 via the buffer memory 2700.
A BY signal 119 is guided to the YJiV muco/verter 210. And the output 12011 of each D/A converter
21 is led to an output circuit 3100 via a color signal switching circuit 2300 via buffer amplifiers 2100 and 2200.

The rigid horizontal synchronization extraction signal H8YNC122 and the duty synchronization extraction signal V8YNC123 are generated by the sub-screen timing generation circuit 280 that generates various timing signals for the sub-screen.
0 (: being guided @The various timing signal outputs 124 of this sub-screen timing generation circuit 2800 are respectively supplied to the digital processing circuit section E of the luminance signal. The signal is based on the output 59 of the decoder circuit 53 and is sent to the mode signal generation circuit 290.
0 (Each 1l-P-de signal 125 is generated at 2.) On the other hand, the main screen horizontal synchronization signal HM8YNCgB and the vertical synchronization signal VM8YNCgg are the main screen timing signals that generate various timing signals for the main screen. Generation circuit 30
001: Guided. This main screen timing generation circuit 30
The various timing signals 126 generated at 00 are supplied to the digital processing circuit section 1/42 for the luminance signal and chrominance signal 1', respectively. Field memory address generation circuit 3100) follows its output 113 to output field memory 1400, 2500 to sub-screen timing signal 1.
27 and main screen timing signal 128.

Output signal DG12 of main screen timing generation circuit 3000
Reference numeral 9 indicates a switching signal for switching between the main screen signal and the sub-screen signal. 130. B-Y signal output 1311 which is a color signal output B-Y signal output 1B2 is supplied to the cathode ray tube 134 via the output circuit 3200 @
Also, the horizontal synchronization reproduction signal /MDM 135 obtained from the main-plane timing generation circuit 3000.

Both reproduction synchronization signals of the vertical synchronization reproduction signal/YDM are led to a synchronization output circuit 33001, and this synchronization output circuit 3300 receives the horizontal deflection signal 137. I! A direct deflection signal 138 is output to the deflection yarn circuit.

As described above, in the embodiment of the image signal processing circuit according to the present invention shown in FIG. 10, the image signal processing circuit according to the present invention processes image data. Processing of image data according to the corresponding mode is performed.The processing of image data according to the various modes is performed by a first correlation calculation and a second correlation calculation on the input and output sides of the field memories 1400 and 2500, respectively. This is possible by performing multiple (b) correlation calculations on image data (2) (- image light 71 of more modes). That's right.

This means that multi-mode screen display can be performed without increasing the memory capacity of the field memory 1400 or 2500, depending on the type of operation according to mode C=. A fruitful example is the data processing of the bright ff signal and 9 color signals (: control means for controlling both signals (two corresponding addresses); a circuit that maintains the similarity and eliminates the need to complicate the circuitry of the address generation circuit. The above correlation calculation is performed for both horizontal and vertical image data, but for the horizontal direction, it is necessary to perform one ice period (= data writing and reading). This is because horizontal correlation calculation is performed (ζ= is required in order to extract the data to be subjected to the correlation calculation per second, but in this example, one horizontal period is winter two). The address generation control used to access the horizontal image data (C2) that reads two lines of data also has a circuit configuration that can follow the multi-mode image display (2 lines). , the present invention (=blocks corresponding to the two blocks in FIG. 10 showing an embodiment of such an image signal geographical circuit), Feature 1: This will become clear by explaining the circuit blocks within the broken line area. .

FIG. 11 is a block diagram showing in detail the circuit blocks of the sub-screen timing signal generation circuit 2800 shown in Mlo. The above sub-screen timing signal generation circuit 2800
1.8YNC1231!
li direct Xjl (No.
The timing signals required for displaying the sub-screens 0 and 11 are stored in the field memory 1400.250.
Timing signals for controlling the control circuit for generating address signals for 0, etc., address and write control signals for line memory that stores horizontal image data, horizontal direction signals for processing sub-screen image data, etc. Clock signals for data processing and clock signals for processing vertical data (divided into two types).

First, if we look at the reference clock used to process horizontal image data, we will see that - all things considered (two horizontal synchronization signals 8YN
C is input and the other terminal I: A comparison signal is supplied and the synchronization signal 'a 8YNC is input to the oscillator 280.
21 functions as a synchronization signal. Oscillator 28
02 generates a clock pulse φ-=880/us that defines the horizontal timing. This signal φ.

is frequency-divided by two in the frequency divider 2803. Here, the branch unit 28
Signal φ which is the inversion of the output of 03. , and so on. This signal φa
m-Fi, the counter eTfL128041 is supplied with a clock pulse, and this counter CTR(1) 28
04 output is 1 horizontal tinging signal generation circuit 2805
(=Added 0 horizontal tiling wandering signal generation circuit 2805
generates a signal 4 which determines the horizontal phase of the sub-screen as one of its outputs, and this signal is applied to the phase comparator 2801 as a phase comparison reference signal for the position comparison.

The counter CTR(1) 2804 is configured with a nine-stage frequency dividing circuit, and divides the frequency by 440 in synchronization with the rising edge C of the signal φ-0. Therefore, the above counter CTR (
1), the final output stage 4: is the horizontal frequency / us - the output of the 8th stage (: is 27 inertia), and the frequency of the above horizontal frequency a is obtained.
The /, - signals are counter CTI-L (7)2 which functions as a vertical counter for determining the vertical phase of the sub-screen.
8064: is added, and the signal with the horizontal frequency of 2/s+m is added to the counter CTJ6S 2807 += of a circuit that performs phase rotation of the vertical phase by a countdown operation. In addition to the signals H and I that determine the horizontal phase, the horizontal timing signal generation circuit also generates a counter CTR (1) 2804 and a line that generates the address of the line memory in the display mode for zooming up the sub-screen. A signal H, , which resets the counter CTR (2) that controls the memory address generation circuit 2808, and a signal H, which controls the line memory and inputs the sub-screen data into the field memory 14υ0°2500 according to the sub-screen mode. Timing signal H, (Htt.

■! Cao) occurs.

Note that the line memory address generation circuit 2808 is
The counter eTk% (1
) 2804 or counter (2) 2809 pulses and line memory = corresponding address 'fH No. AD
ot +AD6g, the shi that generates AD@g, and
The line memory control signal generation circuit JJI2810, which is composed of flip-flops that operate in response to the signal ttas'/l generated by the horizontal tying signal generation circuit 2805 and the vertical reference signal, loads and reads data. Next, the signals to be controlled are shown in Fig. 51111 (=, vertical timing system C=, vertical synchronization signal V in the mJm direction,
8YNC is supplied to the synchronous signal width detection circuit 28111. This synchronization signal width detection circuit 28'll counts the pulses from the counter CTR(1) 2804 during the pulse width period of the applied vertical synchronization signal V, 8YNC, and determines whether the signal can be regarded as a synchronization signal based on this count value. As a result of the determination, only a signal that can be regarded as a synchronization signal is supplied to the phase comparison circuit 28121. This phase comparison circuit 2812 inputs the comparison pulse generated by the phase comparison pulse generation circuit 2813 based on the output of the counter CTR (5), and compares the phase of this with the reference phase. /CTfL (generates a reset pulse for 612807. From this reset pulse (2), a pulse obtained by frequency-dividing the horizontal synchronization signal 2/&Im by 525 is obtained as the output C2 of the phase comparator circuit 2812. In this case, C
2, the phase comparison circuit 2812 and the phase comparison pulse generation circuit 2813 (=the applied signal V- is the signal V applied to the synchronization signal width detection circuit 2811;
8YNC is a signal indicating whether or not there is a capacitance error range -1 when the frequency is divided by 525 and the phase is compared with the pulse generated by the phase comparison pulse generation circuit 2813. If it is outside the capacitance error range, The synchronization signal width detection circuit 2811
The above-mentioned counter CT (6) 2807 is reset by the output of ◎ In other words, vm is the signal that defines the mode of whether or not the synchronization signal is an unstable synchronization signal seen in video games, etc. The vertical reference signal obtained in this way is supplied as a reset signal to the vertical counter CT (7) 28064, and is also supplied to the line memory control signal generation circuit 28104@and the vertical counter C1'a. (7) 2806 is supplied to the vertical timing signal generation circuit 2814. This vertical timing signal generation circuit 2814
0.2500 count address generation counter reset signal V! 0, that is, the vertical timing signal generating circuit 2814 generates a pulse for capturing image data in the vertical direction of the sub-screen.

Line-related signals such as AD, . *Signal H? which functions as a horizontal data acquisition pulse for the vlO field memory? Other than sφA, etc., 1= also generates a pulse signal for driving a rounding control circuit that controls the address of the field memory and an 8/P conversion signal for converting serial format sub-screen image data into parallel format data.

Based on this signal φgo (Nifield memory 1400.
2500 field memory control signal to counter CTl'L (3) 28151 counter (4)
28161 Field memory control signal generation circuit 2ff
17. It is generated by the % reduction timing generation circuit 28184m. Above field memory 1400.2500
A timing signal for transmitting and receiving data by time-sharing C data in 7-bit units is generated at 1 counter C'I'a <3) 2815 in the normal mode of the first side. This signal includes a signal that determines whether the column address or row address is (upper bit or lower bit), and a signal that controls the address of field memo IJ 140G, 2500 (m%, line enable signal wg).
There is a hometown. On the other hand, counter CTR(4) 2816 is
The sub-screen data capture mode is half of the normal mode in the horizontal direction. It is used to generate a timing control signal for time-sharing data. Here, the control signal for transmitting and receiving data by time-sharing the image data of the sub-screen in the data compression mode is the data reduction timing generation circuit 2.
Field memory control signal generation circuit 28 via 817
181: Supplied. This field memory control signal generation circuit 2818 operates in the normal mode and 61j (I
I data is compressed and stored in the field memory 140.
0.2500 +=Generates a control signal to time-divisionally transmit data into upper bits and lower bits.

In addition, the above field memory 1400 * 2500 (2) stores the data itself (2 is the data control 1 signal in serial form, in the image display mode where the main screen is an analog signal display and a sub screen is inserted into this, the above % data Obtain the output of the seed size timing generation circuit 2817 = ψ conversion timing signal generation circuit 28191: Therefore, it is obtained.Here, in the mode table mentioned above, insert the sub screen with the main screen still and nine strokes displayed. Susoichido lnl Hml
In Hml, the image data is 178 horizontally (:
Please note that the compressed image data is compressed in the horizontal direction (-1/8) and then the data is converted from serial format to parallel format (2), the signal is 44.
Counter 28 that operates using 07Ws as a clock signal
A data conversion control signal is obtained by a 1/8 data reduction timing signal generation circuit 2821 which receives the output of the counter 28 as input. This control signal is supplied to the ψ conversion timing signal generation circuit 2819 (2).As a result, the output of the ψ conversion timing signal generation circuit 2819 (= is in any mode (2) shown in the table above). , to obtain a timing control signal for converting image data from a serial format to a parallel format (= 0) Note that the image signal includes both the luminance signal and the 1-envelope signal, but the output of the ψ conversion timing signal generation circuit (2 obtains both the conversion timing signal Y, 8/P for the luminance signal ζ=, and the conversion timing signal C, 8/P for the two color signal values.

As mentioned above, in the screen timing signal generation line zsoo<= shown in FIG. ADat *
At the same time as ADos is generated (-, field memory 14
The control signal for generating the address 00.2500 is generated, and while these signals are being generated, R1'' is generated.The sub-screen tiling signal generation circuit 280 shown in FIG. 11 will be described in more detail.
0 is the standard four-way 1 based on the horizontal synchronization signal H, 8Y1'llC of the sub screen, and the vertical synchronization signal V, 8YNC.
The number generates address signals for the twin memory ships 2, and controls the control system and synchronization system for the field memories 1400 and 25004. In this case, the counter CTR (612807
*Synchronization signal width detection circuit 2811. Phase comparison circuit 2812
゜Details of the phase comparison pulse generation circuit 2813 are shown in Figure 12.
Show two. Here, the synchronization signal width detection circuit 2811
Count pulses of the counter CTJI) 2804 shown in Figure 1 are counted during the period of the applied vertical synchronizing signal, and if the predetermined number of counts is not made, the internal counter is reset. The phase comparison pulse generation circuit 2813 operates in response to the mode signal V- corresponding to the stability zone of the vertical synchronization signal.

In this case, the phase comparison pulse generation circuit 2813 supplies a phase comparison pulse to the phase comparison circuit 28124, and this phase comparison circuit 2812 resets the counter CTJ612807 that counts down the signal 27m-, and at the same time is used as a vertical synchronization signal. signal vaml and its output C
Two occur.

For a long time, the line memory address generation circuit 2808 of the sub-screen timing signal generation circuit 2800 generates the address AD01 #ADH1 for the line memory 2, but the line included in the luminance signal calculation circuit 1300 in the GIO diagram The memory configuration is shown in Fig. 13. In Fig. 13, the line memory L@wL snow* which stores the luminance signal data of the sub-screen in the horizontal direction (Law L4 is essentially a delay of one water period) It functions as an element.And,
Figure 11 - Line memory address generation circuit 28 shown in 〇
Address signals AD, , , AD, □A generated at 08
D0. Later, the address signal ADol is sent to the line memory L,
, the address signal AD, , addresses the line memory L, and the address signal AD,@ addresses the line memories L and L4. Each line memory L, ~L41
is a RAM (
RandomAccess Memory) configuration. The common output terminal signal of the line memory L@eLm serves as an input signal to the other line memory LIIL4. The common output terminal signal of the line memory LIIL4 is a signal delayed by two horizontal periods with respect to the common input signal of the line memories L, , L. The image data of the luminance signal of the sub-screen to be performed on the input side of the field 1400; In addition, each line memory L, -L, (
Second, the write control signals w and g generated in the line memory control signal generation circuit 2810 in FIG. 11 are taken %1.
(2) Signal R is applied to control data exchange.

In this way, one address signal AD, , AD6g, ADl for two line memories L, ~L, l
are obtained by the line memory address generation circuit 2808, but these address signals differ depending on the image mode (2) shown in the table above.This will be explained using FIG. 14. Details of line memory address generation circuit 2808 and line memory address generation circuit 2810 in the figure are shown.

The line memory control signal generation circuit 281o is composed of flip-flops 7'FF, and the line memories L1 to L
, signals W and R are generated to reduce the loss ν of data transfer. On the other hand, line memory address generation circuit 2808
The outputs of the counter CTR11) 2804 s counter CTJ2) 2809 which uses 440/+n as a clock pulse shown in FIG. The above line memory address generation circuit 2808
is the counter CT supplied as a signal defined as address (No. 8) according to the input mode signal (=
R(1) 2804. Counter C°mul (2) 280
The count value of 9 is sent to the three test circuit 18. ~ No. 18 (:
Optionally (outputs 2. This is C2, the line memory address (No. 1 ADO 1) corresponding to the image display mode (2)
t Adol t Obtain ADOI. Address signal AD01. ADo stem ADo t-
The need to occur depends on the screen display mode (two
This is due to the difference in the amount of image data written to the line memories L, -, L41. That is, in the case of the normal screen display mode, image data corresponding to the entire screen is written to the line memory L, ~L41=, but as shown in FIG. 2 Only the corresponding image data (the image data in the center of the screen indicated by the fi+ line) is imported into the line memo L, ~L, l2. Warpage (=The amount of image data to be written is different, and the time to write the line memory L, ~L41, which functions as a delay line for one horizontal period is different between both modes. Problem due to the difference in the writing time of this data C2) is the line memory address generation circuit 280
81=Above address AD61 e ADot to output
w AL) (11 in both modes, three-state circuit'
This problem can be solved by controlling with ra and 'rs4.

The value of the above address ADoz r AD6 @ e ADol is the counter CTR (1) shown in FIG.
2804 I Counter CTR (2) 2809 The difference is that the count value is controlled by the three-state circuits 'rs, , 'rs.

Writing and reading of the line memories L to L are controlled so that when Ll and La are in the data write mode, ζ2 is in the data start-up mode, and line memories L, L4 are in the data start-up mode. Now, when the line memory L is writing, the line memory L reads data from one horizontal period before, and after that one horizontal period, the data from the line memory L is written to the line memory L1. After this one horizontal period, when the data in the line memory L4 is read (2), the calculation target data T, M, and B, which are the calculation targets of the second correlation calculation, are obtained. In this case, the above addresses AD and tmADu are *Tsu/ri CTR (132804
Since the preset values for 1 color//CTR(2) 28o9 are different, the image data writing time and gun ejection time are different between the writing mode and the standardization mode in the line memories LI, L. However, the line memory L that sends and receives image data delayed by two horizontal periods with respect to the current data
, , L4 uses a common address signal D@a. Here, the counter that defines the address address for the line memories L, L4 is the counter CTR(1).
2804, and the counter CTJI) 2804 that functions as this address counter is a normal one-page display page (CTJI) 2804.
This is a counter that defines an address for two. The address address corresponding to the count value of this address counter CTRII) 2804 (=the above line memory L, , L,
The readout address of the three-step memory L, ~L, is set by the counter CTR (1), which performs the count operation of the digital address corresponding to the normal image display mode, regardless of the write mode or C2'. )
2804 determines its address. Since the flip-flop Fv1 constituting the line mesh control signal generation circuit 281O uses the pulse HfL8 every horizontal period as a clock signal, the line memories Ll-L4 continue writing and reading data every horizontal period. do. As a result, regardless of the image display mode,
The line memories L, ~L4 operate as delay lines for one water period, but in this case, the data read timing depends on the counter value of the counter CTR (1) 2804. -C as shown in Figure 7
2. Even if the image display mode is zoom up mode and the image data for % screen is written, the reading of the image data is read out at the same time as the data for the entire screen is read. Therefore, in the zoom up mode memory l,
, ~ If written to L4, the T obtained by reading the data is
, M, B, the data density of #gl correlation calculation target data is % at the time of data writing.

In this way, the line memory functions as a data processing speed converter to read data at a constant speed (2) to read data at a constant speed.

This is because the preset values of the counter CTJI) 28G4 and the counter CTR(2) 2809 are different. 〇Figure 15 shows the horizontal direction timing signal generated by the two sub-screen timing signal generation circuits 2800 shown in Figure 11. FIG. Horizontal timing system is 88
4, which is obtained by dividing the output of the oscillator 2802 that oscillates at 07s by 2.
Various tie/tie signals are generated based on 40/v=φ-0. The signal 118 generated by the horizontal timing signal generation circuit 2805 is a pulse for each horizontal period, and the counter c'ra(t) 2804 * counter (, 'TIL
IJ) 2809, and is used as a reset pulse for the line memory control No. 16 generation circuit 281G, the data small timing generation circuit 21i17 * field memory control signal generation circuit 2818, and the data small timing signal generation circuit 28211: control for Used as a signal. Also, the signal HRgF e 2/Il
l e /as is the rounding operation (
= Use. The signals u,, l HY@ are pulses that determine the timing of capturing image data in the horizontal direction. , writes image data to line memory rims 1 to L, l:, during normal operation, and H! , - is a signal that determines the timing of writing image data in the zoom-up mode.

When writing the above-mentioned line memories L, to L4 (1 image data), it is the output signal of the 7 lip-flops of the line memory control signal generation circuit 2810 that controls writing to the write memory 2. ~
Counter CTR (1) 2804, counter CTR (2) that determines the address when writing L and L data
The count value of 2809 is shown in the same figure (= shown. - As can be seen in the figure, the initial count value of counter CTR (2) 2809 is counter CTJI) 1 with respect to the initial value of 2804
It is 15 base. Also counter CTR (2) 2809
The clock frequency of counter CTR(1) 2804 is equal to h. In addition, the above signal H? I is normal image processing 3! -e-do, H? l is used for signal processing in zoom up mode. Here, l in the horizontal direction!
The pulse H tube that takes in the image data of the I1 screen is classified according to the mode table described above.
ljT.

(m)+mj+ml+ml)+)IT, (m:+m,
)----(g)tl) It is expressed by a logical formula.

Similarly, when it comes to loading image data in the vertical direction, the timing of writing vertical data differs between normal image display mode and zoom-up display mode, but this timing relationship is 16 Figure 1 shows. In the figure, signal V,
indicates the vertical image data capture timing in the normal mode, and svl indicates the timing in the zoom-up display mode. That is, at this time, the vertical image data acquisition timing pulses VT, , VT and the clock signal /
The relationship with the counter address of ws e counter (7) 2806 is shown. In this case, the vertical data acquisition pulse VT is given by the motor table tD m)”t: Correspondingly, Vy = VTI (m@ + m: + m@+ms) + vT * (m * + m t)... ...It is shown by the formula (9).

- Even when the image display mode is the reduction mode, the timing of capturing data in the vertical direction is defined. However, regarding the import of horizontal image data, in the reduction mode, the horizontal image data is discretely processed according to the reduction rate.
Import the data. In the reduction mode, which is represented by m in the mode table mentioned above, it is necessary to reduce the image data in the horizontal direction to 1:A, and the timing pulse for inputting 11 images in the horizontal direction is also set to the frequency of /w in the normal mode. You need to be yourself.

Further, when horizontal saving data is extracted in normal mode C: and image data is extracted at a rate of % I:, the horizontal data capture timing pulse needs to be %/as. The horizontal image data capture timing pulse V? according to the reduction mode of these display images? 0 is (
- Mode Table - Expressed by the following formula using two reduction modes: Vvo=Vts (K/ns・ms+M/ws
・m; ) −・・as In Figure 17, normal mode chime = timing pulse to capture horizontal image data/
me *Timing pulse 3AI in % reduction mode*
Timing pulse in reduction mode to sav %4/M-
The relationship between the color and the count value of the counter eTJ7) 2806 is shown.

In this manner, the data extracted and subjected to M/D conversion according to the display image mode 1 is taken into the field memory 1400, 2500 (:,) at the above-mentioned timing.

The color signal of the image data of the sub-screen is processed by time-sharing two signals of R, -Y, and B-Y signals at the input side of the color signal calculation circuit 240G, which is a preprocessing of the color signal field memory 250G. There is a need to. In this case, the multiplexer i ioo time-divisionally multiplexes the color signals into serial signals in the order of R-Y, B-Y, R-Y, B-Y, etc. Signal, ship-
The timing of converting the Y signal and B-Y signal into serial form is shown in the relationship C with the luminance signal. In FIG. 18, φO− is the luminance signal t sampled l
The four timings for multiplexing the color signal as described above with respect to the signal φO- which samples this luminance signal, which is a signal generated by the horizontal quiescent signal generation circuit 2805 of the l1-specific timing signal generation circuit 2800, are as follows. This is done at the timing shown in FIG.

(Hereinafter referred to as margin G 〇 (Field memory 1400.2500) Next, field memory 1400.2500 stores the first correlation calculation result.
Let's talk about 2500.

FIG. 19 shows a field memory 1400 that stores correlation calculation results for luminance signals and a field memory 2500 that stores correlation calculation results for color signals. The luminance signal field memory 1400 follows the control signal generated by the luminance signal d8/P conversion timing signal generation circuit 2819.

The image data is converted into parallel form by the 8/P conversion circuit 1410 and stored in the luminance signal field memo 1J1420. Also, at this time, the memory address is generated by a field memory address generation circuit 1440 controlled by a field memory control circuit 1430. When reading the luminance field memo IJ1420 data, the P/8 conversion circuit 1460K performs P/8 conversion of the data in response to the timing signal from the P/B ting generation circuit 1450 in order to perform the second correlation operation. . In addition, field memo data for storing color signals subjected to correlation calculation shown in FIG. 19 are stored in the color signal field memory 2.
520. The successive data is then converted into serial data by a P/8 conversion circuit 2530.

For field memories 1400 and 1500 K, as mentioned above, the timing signal #1 for converting data from parallel form to serial form is used to control the upper address address, the control signal that controls the address at position )'', and this address. A control signal, a write enable signal W, is required to control the field memory itself in accordance with the control signal.

FIG. 20 shows the 11th section which controls the field memory.
Field memory control signal generation circuit 2818 shown in the figure
The details of the and number data reduction timing generation circuit 281 are shown below. In FIG. 20, a counter CTR14) 2816 is a counter that generates a timing pulse for converting image data for a luminance signal from a serial format to a parallel format in a normal image display mode, and is an output signal of the horizontal tying generation circuit 2805. Reset is applied at H□ and synchronized with signal H0. This counter CTR1
4) Convert data from serial form to parallel form using 2816 system group sp・58Pl+SP**
Obtain SP1+8P4. Note that the counter CTR (412816) of this % reduction timing generation circuit 2817 generates the 8/P conversion tie pulse (412816) that reduces the horizontal direction data of the luminance signal to a signal in the normal image display mode. The field memory control signal generation circuit 2818 generates a signal 880fus+440f
In response to the signal va, a signal for controlling the field memory is generated from the output of the counter CT R13) 2815.

The foot memory uses DRAM in this embodiment, and is a signal necessary for this control. Column address strobe signal CAG that controls the address,
A field memory control signal generation circuit 2818 obtains a row address rope signal RAS, a column address gate signal CAG for controlling address signals, a row address gate signal RAG, and a write enable signal.

The counter CT R(3) 2815 mentioned above in FIG.
.

It shows the timing relationship between the pulses of the counter 1412816 and the data sampling control signal system for the luminance signal field memory 1420. In this figure, the sampling interval of data shown from 8Pa to 8P4 is lφ, 0, and sampling of period data of lφ1o is stopped between sampling one data and sampling the next data. Data? /8 conversion and the signal φso ” for data sampling.
The time interval of the period can be said to have a negative effect on the processing speed of the % field memory. In addition, W in figure 1
ET is a timing pulse that reduces horizontal image data to A in normal display mode.

In normal image display mode. Having looked at the S/P conversion of data for the feed memory, next we will discuss the 8/P conversion of data when the image display is in the reduction mode.

In the normal image display mode, in order to effectively use the storage capacity of the field memory, the image data is reduced in the horizontal direction. For the present invention, display 1! j
As shown in the table above, ll can be reduced across multiple modes. To reduce the size of the display screen, the display data is reduced to A before storing the data in the field memory (modes mB and rnB in the table above). 8 of the data in this case
/T' conversion is obtained by the circuit shown in FIG. 22. FIG. 22 shows data reduction timing generation circuit 2821.8/P timing signal generation circuit 281.
The circuit part related to the reduction mode of the G display 1m plane, counter CT Rf512820, is shown. @22 In the figure, the counter CT R (512820 is the counter, φ0
．． is used as a clock pulse, and five pieces of data are extracted during this time, so the data is reduced to . Then, a signal Ill having a horizontal frequency of one screen is a reset signal, and the output of this counter CT R+5) 2820 is gated by a reduction timing generation circuit 2821, and the display mode is set to m-1m in the table above. 8/P of 111 data
Generates a conversion timing control signal. That is, as shown in the figure, the data reduction timing signal 8P@;
8P;,! 9P;.

occurs in circuit 2821. A time chart of these timing signals is shown in FIG. In addition.

In FIG. 23, sp of the timing signals:
, sp; are omitted.

The timing signal 8P2, sp; ~ sp;, waT generated by the data reduction timing signal generation circuit 2821 is
' is led to the three-state circuit TS of the 8/P tine signal generation circuit 2819, and is controlled by the mode signal mζ0ms. Here, for the three-state circuit TS.

Timing signals spo, sp, , sp, , sp, , sr, , ws when the display image mode is the normal mode.
'r is led to the above three-state circuit 8T,...
According to the image mode applied to 8T, an 8/P conversion timing signal is obtained at the output of the 8/I' conversion timing signal generation circuit 2819. In this manner, a 97P conversion signal of image data for a luminance signal is obtained.

On the other hand, the 8/P conversion timing signal for the 11 color signal data is the conversion signal sp·, SP, described above in FIG.

8P, , 8F4.8P4 and flip-flop Ii'l
Output Q of Fo.

Q is made by Toyoshi. The above 7 rigs 70 rigs FFL11
1. , an inverted signal of the writing enable signal W8T of the image data of the luminance signal to the field memory 142o is input, and is reset by the signal HasK. This FF,
The output of three-state circuit T8. ．． T8. It is a control signal for Since the chrominance signal is serially converted into R-Y and B-Y signals alternately by the aforementioned multiplexer 1100, the timing of 8/P conversion is 1illIl! as in the case of the luminance signal. l! It is not possible to perform 8/P conversion at the timing of the data. That is, for one color signal, serial KR-Y, B-Y.

From the data group RY, . . . , it is necessary to extract every other signal only the RY signal or only the B-Y signal. The mode signal shown in FIG. 22 determines whether one of the RY signal and the BY signal is extracted and the data is reduced in size or in size depending on the mode.

When this mode signal is m.10 m- in the mode classification of the display image, the color signal data is reduced to A, and the tie diagram in this case is shown in FIG. In FIG. 24, the signal φ
. , KR-Y, B-Y signal data come every cycle of , but reducing the data to % means that the signal j
This corresponds to sampling each data corresponding to data 8P to 8P one by one during the og IQ clock period. Even when reducing the color signal data shown in FIG.
By extracting one Y signal and one B-Y signal, the data is reduced to color signal data H.

In the figure, taking the color signal data corresponding to sp and c' as an example, time A during 10 clock periods of clock i'ol
Since the RY signal data is sampled at , the data has been reduced by %.

Similarly, sp, c', sp, c'...sp,
The color signal data corresponding to c' are respectively reduced to a. In this case, the data corresponds to the timing signals 8P, C' to sp, c', and the data is [''(R-y)e(n-y), (a-y)
, 1-y)*(a-Y)) parallel data K in the order
8/P converted. Then, the set of first-order parallel-converted data is inversely K [(FL-Y), (B-Y
), (RY), (BY), (BY)]. The sets of S/P-converted (RY) and (BY) signal data alternate. In addition, in FIG. 24, the RY signal is sampled at time 1 A, and
Since B-Y is sampled at time B after rO, the phase error between R-Y and B-Y can be suppressed.

The time difference between the sampling times of the RY signal and the BY signal is at most two clock periods between times E and F. In this way, in the S/P conversion timing signal generation circuit shown in FIG. 22, although data is reduced and data is extracted at discrete times, the difference in sampling time between color signals B-Y and 1'L-Y is large. In order to suppress the occurrence of B-Y and R-Y (It) phase errors, the display screen mode in FIG. 25 is m'l or ms, and the mode signal applied in FIG. 22 is m'l or ms. ', +ml, the timing chart shows the case where the color signal data is reduced to %. The calculation kc has already been explained using No. 51 Oka and FIG. 8.

In FIG. 26, the first
The correlation calculation will be comprehensively explained.

In the 26th river, the luminance signal calculation circuit 1300 and the latch circuits Lat 1 to 12 of the color signal data 112400 each have a latch function of latching data. However, the clock signal φ, which is applied to the latch circuits Lat20 to Lat31 as four clock signals φ. It functions as a geometric delay element having a delay time of .tau., which is 2 minutes.

' First, the first correlation calculation for the luminance signal will be described for each of the latch circuits lat l to 3.

Image data Ty of the (n-1) line diagram, data My of the n line diagram, and data BY of the (n+1) line diagram are respectively derived. Here, if the output of the latch circuit Lat 21 is taken as a reference time, the input data of the E-lock circuit Lat 21 advances by a time τ, and the output data of the latch circuit Lat 22 lags by a time 2τ. Here, -1 for the delay of time τ, 09 for the current time, +1 for the advance of time
When the subscript of is defined, the operation target of the first correlation operation is B(
IY, M+tv, MOY, 'Ji-sv,
It is expressed by five pieces of data of Tov. The relationship between these five pieces of data is made to correspond to the display-plane di image data, and the sample positional relationship of the data is shown in FIG. 2nd above
In the luminance signal calculation circuit 1300 in FIG. 6, SX, . Further, s81"'-'l is an adder that adds the critical data after a predetermined calculation. The output of the adder 8 is led to the latch circuit Lat8, and the output of the calculation 4S is sent to the latch circuit. The image data Mo is guided to the latch circuit Lat 9. The image data Mo is guided to the latch circuit Lat 7.
9 constitutes a three-state circuit. In this case σ)
The three-state states of the latch circuits Lat7 to Lat9 are determined by the mode signal and the clock signal φOS. A signal obtained by wire-ORing the outputs of these latch circuits Lat7 to Lat9 is determined by the data YMI of the first correlation calculation result for the luminance signal. This operation result data YMI B* can be expressed by the following logical equation according to the mode classification based on mode truth described above.

YM iris = (Mt+Mt) to (O+N 詿; )((0,
25 (M+IY +M-凰y)+O-5MOY)
+(M', +M, )(0,125(M+IY+M-
IY+ROY+T@Y)+0.5M0Y)...
...0υ On the other hand, if we look at the color signal calculation circuit 1400.

For color signals, it is necessary to extract the RY signal and the BY signal and perform calculations. In color signal calculation, R-Y signal, B-Y
A time-division operation is performed on any one of the signals transmitted every time τ.

Therefore, regarding the horizontal data, the reference time data CMoo)e is a signal delayed by 2τ from this (M-unique).

The signal (M+2a) that is two steps ahead is the object of calculation. The first correlation calculation result CMf for the color signal obtains the outputs of the latch circuits Lat 10 to 12 as a wired oasis. The first correlation calculation result CMI for this color signal is expressed by the following equation.

Cut=(M1+Mt)May+(Mo+Mo)(0,
25(M+xy+Mk-ty)+o,sMoy)+(
M'++Ms ) (0,125(M+ty+!IJ-t
y+Bov+Toy)+0.5Moy) ---1
13. In Fig. 26, the weighting coefficients for the data applied to the multiplication circuit are 0.5, 0.25, 0.1.
25, but in order to configure this, a circuit configuration may be used in which a predetermined coefficient is determined by an adder using a bit shift method. Also, the data as the calculation result is rounded to 6 bits, b, *Final output data YMl * Ck
it becomes 6-bit data.

In this way, the first correlation calculation of the 1-party data shown by both equations 1141 and 19) is isometrically not as effective as the filter having the well-known comb filter characteristics as the 1-party data.

(Generation of timing signal when changing 8/P, S/P data) As mentioned above, the result of the first correlation calculation obtained by processing the data in this way is that the luminance signal data is field memo! At 1400, the color signal data is stored in field memory 2500 as an 8/P converted signal. In order to further perform a second correlation calculation, the data stored in these field memories 1400 and 2500 are read out and then subjected to P/3 conversion. This has already been observed using Figure 819, but Figure 8 of the data is shown in Figure @28.
The details of the circuit that performs /P and P/8 conversion are shown below. Second
In Figure 8.

Latch circuits Lat 1411 to 1415 of the configuration are introduced.

Each of these latch circuits receives a conversion timing pulse 8 generated by an 8/P conversion tying/signal generation circuit 2819.
Po-8P4 is led and latch circuit Lat141
The output of 1 to 1415 is a latch circuit L consisting of 30 bits.
At 1416. This latch circuit 14
The signal W8TY generated by the 8/P conversion timing generation circuit 2819 is given as the 16 clock signal. 8/P converted image data is obtained as a 30-bit output of this latch circuit Lat1416. This 8/P
The converted signal data rate is 1 step faster than the data rate before S/P conversion! I! Display mode is ml +
When the mode is indicated by m'@, it is a・, mt+ml
In Japanese, it is a number. becomes. This means that in the mode table mentioned above, when the display mode is m (for horizontal data when the display mode is , , m, , m) kli = = % binding 1 When the display mode is rn', , m, Hdi = This corresponds to the fact that =.

Looking at the P/8 conversion for the data of one color signal, the circuit configuration is approximately the same as the P/8 conversion circuit for the luminance signal. The 8/P conversion timing signal of the color signal data is controlled by the three-state circuit TS in the image display mode.

In other words, when the image display mode is m1+ml *8P(
IY~8PJY t Used as 8/P conversion timing pulse.

If the mode is (ml+m,) (the display mode is ml, m
.

In other cases), 8P, C' to s P, c' are used as timing signals for S/P conversion. That is, the 8/P conversion timing pulse for luminance signal data is also used as the 8/P conversion timing pulse for color signal data when the oiii display mode is ml+ml. Original luminance E′
The signal data density of the chrominance signal is % for @, which is 8/P.Although the switching timing is different, it is 8/P for the brightness LF signal.
In order to reduce the number of circuit elements by using the T' conversion timing signal as a timing signal for 8/PK conversion of color signal data, this embodiment uses 8/PK conversion for the luminance II polarization system and the color signal system.
/P The circuit configuration is such that the timing generation circuit is not separated. In this way, the S/P for the luminance signal system and color signal system
Sharing the conversion timing signal circuit according to the display mode can reduce the number of circuit elements, and the combination of the data reduction coefficient required for the luminance signal and the color signal reduction coefficient can be reduced in the circuit configuration. This can be easily satisfied without complicating the image display mode, and many image display modes can be set. In addition.

In this embodiment, the field memories 1420 and 2520 for transmitting and receiving data for 8/P-converted image data have the same bit configuration as 211.2.

The data sampling circuit for performing the first correlation calculation on the field memory 1420 and 2520 and converting the image data into 87P has been described above.
The case of conversion will be described next.

The data stored in the field memories 1420 and 2520 are processed by the P/S conversion circuit 1460 for the luminance signal data and for the chrominance signal data in order to perform the second correlation calculation. P/8 data exchange is performed at 2530.

Timing control of data PI3'R conversion in the -P/8 conversion circuits 1460 and 2530 is performed by a P/8 timing generation circuit 1450.

FIG. 29 shows details of the P/8 timing generation circuit 145°. The P/8 timing pulse generation circuit 1450 essentially consists of a shift register, and receives the 8/P conversion timing signal SP generated by the 8/P conversion timing signal generation circuit explained in FIG. 20 above and the signal -01. As input, output data s, l s, l...S,
. occurs. Figure 30 shows the tying yard.

(Generation of field memory control signals and address generation for field memory address control) So far, we have talked about 8/P conversion and 8/P conversion of data when sending and receiving image data to and from field memory. Next, regarding the circuits that control the address of the field memory and generate address signals, the field memory control circuit 1430 and the field memory address generation circuit 144° in Figure @19, we will particularly explain how the addresses are controlled depending on the display image mode. Regarding this, please refer to FIG. 31 showing details of the field memory control circuit 1430 and the field memory address generation circuit 1440.
The shift register 8R1 of the field memory control circuit 1430 in the figure is the horizontal force register 4C shown in FIG.
The output φ of T R (1) 2804 is used as a clock signal, and the signal VT expressed by the above-mentioned formula 9 is input. The output of this shift register 8R (CsD+B) is in phase with the mode signal (m'l+m,) that selects the mode where Hdi=% in the mode table mentioned above, the preset data injection signal P+G, and the data preset signal PG. obtain. 11
A signal vT@, which is a signal that defines the timing of line data extraction and is expressed by equation 10, is input to the shift register SR. The output B of this shift register SR2, Ft
Thus, the preset signal PG' of the write address counter CTR(W) of the field memory is obtained. In addition, FIG. 32 shows the above-mentioned signals φt, VT, PTG, RG, VT, .
A timing chart of PG' is shown.

Factors for determining an address when writing data stored in the field memory include whether or not the displayed image is in zoom-up mode, and whether the displayed image is held still.

FIG. 33 is a diagram showing the address area of the #i field memory in relation to the optical diagram, and FIG. 33(a) is, for example, m
The figure shows the entire address area when the image display mode is m, and shows the address area corresponding to 2201 (H: indicates one line). In this case, the reduced data of the sub-screen is stored in the address area of the shaded area. Further, FIG. 33(b) shows the address area of the field memory when the display mode is m:, in which case the reduced data of the sub-screen is stored at the address of the diagonal area. 33rd
As you can see by comparing (1) and (b) in the figure, (b)
The area shown by K has only a smaller area corresponding to 11OH. this is.

In m'l %--do, -Image data input is #! 1
As shown in FIG. 7, the amount of m-image data is small because it is performed on the cutout portion of all 1& planes. in this case.

To obtain a zoomed-in image, data interpolation is performed on the output side of the field memory. Even though the image is zoomed up in this way.

The field memory capacity may be small.

This is because correlation calculations are performed twice on the input and output sides of the field memory.

Writing of wig data on the sub-screen as shown in FIGS. 33(a) and (b) with the K slope is done by
This is done by having the person who wrote the terrible data skip the addresses other than the slope part. By pressing in this manner, the ms data of the main screen is written, and further data is written to the field memory.

By reading out the data written in the field memory in this way by specifying the address in the normal mode, a screen in which the sub-screen is interposed between the main screen and the main screen is obtained.

To explain the address skip mentioned above, refer to the above l.
The signals shown in FIG. 32 are related to address control on the l&1IIdj plane.

Field memory control circuit 1430 in FIG.

In the field memory address generation circuit 144o, the signal RG is led to a reset terminal of a field memory write address generation circuit CTR (W) consisting of a 13-stage frequency dividing circuit. In addition, the preset data throat signal P
+G is the control of buffer T81441) 1442.1443 and latch circuit Lmt
1444 reset terminal.

The output of the buffer 1442 is connected to the control circuit 4 of the buffer 1445, and leads the preset data PR8 to the address line A U wt. This preset data #'i
, which determines the start address at which the 1Iiii11 data of the secondary 1Iij plane is stored, and in this embodiment is +2356.
It is 9 places. In addition, the output of the above G) 1443 controls the buffer T81446 and sets the start address -
(+4692) to address line person DWI.

In the region where the signal PTG is "0" shown in FIG. 32, the address line AT)wz is connected to the address line ADW1. Address line ADW is led to adder 581447. A skip address button +24 for skipping addresses as shown in FIG. 33 is led to a latch circuit 1444 for skipping addresses +24 in order to write image data on the -Iiii side. The output of this latch circuit Lat1444 is led to an adder 81447, and the output of this adder is sent to a counter CTR (W) CT R
The preset gate signal (W) is obtained by the logical sum PG'+PG of the signal PG' and PG shown in FIG. In addition, the input signal of the address counter CTR (W) is % (
VT(m, +m,)+VT@)HT-W8TY is supplied from the output of the gate circuit 1431 by logical logic operation.

On the other hand, the field memory read address ^DR is buffer T! 91448 and is selectively outputted by signal WE'. This switching K makes it possible to write data for IH and to release data for 2H within 18 periods. The reason why 2H worth of data is read out in addition to IH data storage during the IH period is because when performing their second correlation calculation, 3 lines worth of data (
T.

By making M and B) necessary. In other words.

Please write the data for the upper IH within the IH period.2
By controlling the address from which H worth of data is read, correlation calculations can be performed twice on the input/output side of the field memory, and display 11! ii Image modes can be set in a wide variety of ways.

Note that the address of the field memory is buffer 5r (X
, ), 5T(l()). In this case, the address of the upper bit is outputted via 8T(H) and the address of the lower bit is outputted via 8T(L).

This switching control is shown in FIG.
It is controlled by K.

Also, 1Il is connected to the input of the shift register 8R in FIG.
j When a control signal for a mode for keeping the gyoza is input, the gate circuit 14'32 is closed. As a result, the signal WB, which is a write permission signal for the field memory, is cut off. As a result, writing of image data to the field memory is stopped.

In this case, the signal VR8, which is the reference signal for the vertical period, is used to reset the data so as not to stop writing data in the middle of one image data for l vertical screens. In this way, even though we have stopped writing new friend itiw data, by continuing to publish artist data one after another, we can stop the situation.
An m image is displayed.

(Main Screen Timing Signal Generation) Next, details of the main screen timing generation circuit 3000 that generates timing signals related to the display of the main screen r1irjB will be explained using FIG.

#! In Figure 34, the main screen horizontal synchronization signal HM8YN
C is derived from the phase comparison 53001 K and t. This phase ratio Mosquito 3001 KF! , horizontal 7-) iback signal) IF
B is added. The output of the phase comparator i 3001 is guided to the oscillation i 13002, and the phase comparator 3001 performs control such that the phase difference between the horizontal synchronizing signal HM8YNC and the horizontal flyback signal (IFB) becomes zero.

Oscillation frequency φmViφm of the above oscillator 3002==88
0formCfHM main screen horizontal frequency), this signal is %
The signal is guided to a frequency dividing circuit 3003. The output m0 of this frequency dividing circuit 3003 is led to a main screen horizontal counter CT RQ (13004) consisting of nine division stages, and the output of this counter CTl11 is led to a main screen horizontal timing circuit 3005. .1+, the above counter CTR (
II is a vertical counter C for each of the signals f decoy*2Tmx
TR (to) 3006. Vertical counter for synchronous playback (:'
, 'r R(to) 3007. Furthermore, the output of the time counter C'l'R trout 3004 is sent to the vertical synchronization detection circuit 3008 of the main screen 414. The counter CTR (213006) is a counter consisting of nine frequency division stages, and the output of a predetermined stage is led to the main screen timing generation circuit 3008K.

The vertical synchronization signal VM8YNC is subjected to vertical synchronization in the above-described correction synchronization signal detection circuit 3008 to obtain a detection signal VtM.

the above*? The CTRC5 [13007r/) output is guided to the self-1) set pulse generation circuit 3009, which is controlled by the mode signal V#, and sends the self-reset signal and comparison pulse to the vertical synchronization pull-in circuit 3010. K output. The vertical synchronization pull-in circuit 3010 of E is controlled by the mode signal VM and generates a vertical reset signal VRM, and also supplies a 41111 drive signal fvDM to the synchronization output circuit 3300.

In addition, the above-mentioned counter main # horizontal counter CTRI! (1
The output of 3004 is generated by a horizontal drive signal generating circuit, and this signal is supplied to the synchronous output circuit 33.00.

The outputs of the main plane horizontal timing circuit 3005 and the vertical plane timing 3012 are outputted by an output x-7 address generation circuit 3013, a display effect signal generation circuit 3015 that gives a special effect to the display on the sub-plane, and an analog signal switching at the output stage. Analog switching control circuit 3014 that generates signal DG
is supplied to.

Main l1iWi timing generation circuit 30 shown in FIG.
00, the phase comparator 3001 is connected to the vertical synchronization detection circuit 30
When the display mode supplied with 08K is m. In this display mode, the oscillation 93002 freely oscillates at the center frequency. As a result, when the display image 1 is displayed in a static state, the oscillation @3002 is caused to freely oscillate and a synchronization signal is generated in the internal circuit.

That is, when displaying an image rM* in a stationary state, synchronization is continuously performed using the output signal of the oscillating i12000 in a 7-rerun pattern, and even if the channel of the chainer 61.79 is changed, the displayed artist to prevent it from being affected.

In addition, the mode signal applied to the ti vertical period pull-in circuit 3010K is handled by the vertical synchronization pull-in circuit 301O.
This signal determines whether or not the VM is within the pull-in range.
= O, a synchronization signal is generated by the secondary countdown operation performed by the counter CTR (n3007° vertical synchronization pull-in circuit 3010. self-reset pulse generation circuit 3009). Then, the mode signal VM
In this case, the synchronization system is set to external synchronization in preference to the mode signal m@s+m. In other words, when in the 1 display ubi image stop mode and the applied synchronization signal is outside the pull-in range d of the vertical synchronization pull-in circuit, the synchronization signal is internally generated by a countdown operation. FIG. 35 shows a timing chart of signals related to the countdown operation for obtaining the synchronization signal for the main screen according to the internal period. Th TOM in the diagram
indicates a comparison pulse. As can be seen from the figure, the driver pulse width of the vertical drive signal fv-ew is 11.5 Tgm.
(T+nB horizontal period of main l1i1 plane).

The main screen synchronization signal system signal is determined by K as described above, and the phase difference Tx and pulse width between the horizontal drive pulse fMDM and the output fsw of the color CTRQ13004 mentioned above are determined in accordance with the horizontal output circuit of the display unit lid. 'rw e-vertical period retraction circuit 3010. It can be made variable by configuring the horizontal drive signal generation circuit as shown in FIG. Third
Monostable horizontal drive signal generation circuit 3011 having the circuit configuration shown in Figure 5 - Multivibrator M
By controlling the capacitance value of *CVI in the capacitor C' that determines the time constant of M, the above phase difference T! , Pulse width Tw
is controlled. This signal /HM and horizontal drive signal /H
Signal 9 II whose phase difference Tx with DM and pulse width are controlled
The relationship with M is shown in FIG.

(Horizontal and vertical display position definition of display screen 11i) Next, the main screen timing generation circuit 3000 generates a signal to define the position of the display screen in the horizontal and embroidery direction. As described in FIG. 4, the display position of the sub-screen is indicated by P, -P in the same figure, and is set to be displayed in the ninth cabinet. It
For example, to display the screen on tflt in the right corner, p, -
1, and other positions P, ~P4
shall be defined in the same way. And the 34th
As shown in FIG. 38, the main screen horizontal timing circuit 3005 in the figure defines the horizontal display position according to the display position shown in FIG. 4 based on the horizontal reset signal HMR. A signal QMM' defining a horizontal display expressed by the following logical expression is generated based on the signals T-XI-TX according to the timing chart of FIG.

GMH' = THIM (Ps+Pa)l'Ot
+TH*v (Pt +Pm)111+11 +T
HIM(PM+P4)IIg11+TI4M(P1+
Pl)a@+THIM(m,@-)m,, )...
(13) On the other hand, regarding the position regulation in the !j vertical direction, the self-portrait screen timing circuit 3012 calculates the following equation based on the signals 'rvtm to Tma4 according to the timing chart of FIG. Signal GMV that specifies the vertical position indicated by a logical formula
occurs.

GMV=TVIM(Fs+P4)mo1
+Tvsv(P1+P1)s@,+Tvi(Pg+
1'4)+aw+Tu4(Pt+P-sn+TvaM
(Town e+mos)...04 The display area is determined by taking the logical product of the regulating signal G' and the signal ~ which defines the vertical direction.

(Display effect, switching with analog signal) FIG. and details of the display effect signal generation circuit 3015. ND to the gate circuit of the output sofa address generation circuit 3013 performs a logical AND operation of the signal GMM' that specifies the display position in the horizontal direction and the signal GMv that specifies the display position in the flrM direction, and then displays the display screen. It outputs a signal GMII that defines the display position of. This signal GMHFi shift register 5R31
and is added to Dekatasha counter CTR0II of this shift register 8R31. Counter CT R
L'll is a counter consisting of nine counters, which uses the result of the A-B output logical operation of the shift register as a reset number 1, and generates a starting address signal for the output buffer memory to be described later.

The output buffer address generation circuit 3013 determines whether the output buffer address generation circuit 3013 outputs an output buffer address generation circuit 3013. The gate circuit AND is closed in response to a selection signal Ml indicating whether to display an image obtained by digitally processing the digital data. The logic value of this gate circuit AND is used as a control signal DG to determine whether or not to control the period in which an analog signal is displayed and the period in which a digital signal is displayed in one horizontal period. In addition, shift register 8R32
The output of the signal GMV' generates a signal GMV' whose phase is delayed by one horizontal period with respect to the above-mentioned signals G and vK. Since the calculation takes time, the actual display of the first wife is used as a control signal to delay the actual display by 2H.

(Display Effect) As for the display effect, in this embodiment, since the display on the sub-screen is instantaneously displayed, a display method is used in which the door gradually opens without any confusion.

In the display effect signal generation circuit 3015, a signal VRM having a pulse width of the l-period in the main wIJrI4 is used as a time reference signal for performing display effects. Counter CT R30 to which this signal VRM is input
The second stage output of 0 and the third stage output are selectively switched by an external control signal by a switch 8W. Now, if the switch 8w is connected to the power supply shaft, the output signal CP of the gate circuit OR becomes a clock signal of y seconds. Furthermore, if the above switch 8W is grounded, a clock pulse of yIs seconds is obtained. The above signal CPN performs 1 display effect81
This results in 300 clock pulses. The above command signal is rlJ
Then, the signal Prd obtained by performing the operation of 100 on the outputs A and B of the shift register 8R300 is obtained at the output of the gate circuit AND2. This signal Prd/d is used as a down-counting counter DCTRI consisting of 7 stages.

Cow yfiUCTRItDATAI for up counting,
2 (in this embodiment, it is 40). The position on the screen from which to start the door effect on the displayed image is defined by the preset data at the time of success. The above counter DCTRI.

The clock signal of UCTR2 is the signal Cps obtained by ANDing the above signal CP, the output indicated by C of the machine register 8R300, and the output of the gate circuit NAND1.
Use vo. This time, the p-clock signal is recorded, and the down counter DCTRI counts down.

Then, the up counter UC”rRl is 80 (Qs=Q
v=1), the clock signal is blocked by the output of the gate circuit NAND1 (CPNYG=1).

Furthermore, the 7-bit output of down counter DCTRI is supplied to converter CPAI. Similarly, up counter υ
The 7-bit output of CTRI is also provided to comparator CP^2. On the other hand, the output I of the shift register 8R31 is reset by the inverted signal, and the output ■ and the signal φ
The 7-bit output of the counter 078301, which uses the AND with m・(4407g) as a clock signal, is sent to the comparator CP.
It is supplied to AI, 2. Comparator CPAI fault output CMP1. The coincidence output CMP of the comparator CPA2 is led to gate circuits NAND2 and NAND3, respectively. The outputs of the gate circuits NAND2 and 3 are applied to the set terminal 10 and reset terminal i of the Bibi 7 lip-flop FF30, and the output of this FF30 generates a signal indicating that the door is full due to the door effect. . In order to perform the door effect of gradually opening the display surface without disturbing the 1fIi image in the initial stage, the front station counters IJCTRI and DCTRI are preset before the display effect operation is performed. FIG. 41 is a timing chart showing that the display effect is performed after the counter is preset. As shown in the figure, after the signal MDOP for effecting the display effect is generated, preset data is generated for the counters UCTRI and DCTRI, and then the clock signal CPNvo for these counters is generated.

Further, a timing chart for explaining the display effect is shown at 1g42+31. In the same figure, the clock signal CPNV
G l shows the relationship between the counter address of the down counter, the counter address of the up counter, and the matching outputs of the comparators CPA I and 2, respectively. As can be seen from the figure, the counter addresses are all based on 40, up-counting,
Performing a down count. This means that the image display corresponding to the color address 40 is expanded horizontally. To enlarge the display screen, use flip-flop FF30
As the output signal pulse +il expands as shown in FIG. 42, the display image on the sub-screen expands. Note that the display effect is based on the display mode signal and the flip-flop PF3.
By performing a logical sum operation with the output of 0, this is performed according to the size of the sub-screen determined for each display mode.

(The following is a margin.) (Reading control of data in field memory) The image data stored in the field memory needs to be read out in order to perform the second correlation calculation. In this case, the image data of the sub-screen stored in the field memory at the timing of the sub-screen must be replaced with the timing of the main direction and displayed. The control circuit for this purpose is the field memory read address generation circuit 3100 shown in Figure $10. The block circuit configuration of this field memory read address generation circuit 3100 is as follows.
Shown in Figure 3. 1lls43 In the field memory read address generation circuit 3100, the main 111i1mG generated in the main-plane horizontal timing circuit 3005
The field memory read timing circuit 3020 generates six field memory read timing signals by inputting the timing signals G, GM, and G.

This field memory read timing generation circuit 30
In response to the timing signal 671 generated at 20, data for one line period (ITug) in the opposite direction is read out from the field memory during the l line period (l TMM) on the main surface, or data for two lines is read out from the field memory. The field memory data continuation monitor circuit 3021 determines whether the field memory data is to be output or not depending on the display image mode. One output of this field memory data continuation monitor circuit 3021 controls a line memory address generation circuit 3022 and generates a line memory address 697 in the line memory address generation circuit 3022.

Further, the other output 677 of the field memory read monitor circuit 3021 and the sub-screen timing signal 672 are led to a field memory read clock generation circuit 3023 that generates a continuation clock for the field memory.

This field memory read clock generation circuit 302
The output 682 of the field memory read address generation counter 3024 is used as a clock signal of the field memory read address generation counter 3024. In addition, the skip timing generation circuit 3025 generates a timing signal for skipping the read address of the field memory in accordance with the number of lines in which data is to be discarded when the second correlation calculation is to be performed. .

The skip data generation circuit 3026 is a circuit for generating a timing signal for skipping the read address of the field memory according to the bust display mode.

The skip data indicating how many read addresses of this skip data generation circuit 3026 are to be skipped and the field memory read address generation counter 3
The count value of 024 is added by an adder 3027.

The output of the adder 3027 is preset to the value of the counter button 24 by the output 680 of the skin timing generation circuit 3025. As a result, the value of the field memory read address generation counter is skipped, and the read address of the field memory is skipped. By skipping the addresses in the field memory in this way, the required number of lines of data of the image data in the field memory is read out.

In addition, the buffer memory write clock control circuit 3028 in FIG. 43 operates according to the image display mode, which is a clock for the buffer memory of the luminance signal ratio capacitor circuit 1600 and the color signal output buffer circuit 2700 shown in FIG. Occur. The clock signal generated by the panzer memory write clock generation circuit 3028 is sent to the buffer memory write address generation circuit 3029, which generates the address 694 of the buffer memory according to the image display mode signal 690.

In this way, the field memory read address generation circuit 3100 extracts only the image data corresponding to the line necessary for performing the second correlation calculation from the field memory, so that the field memory read address generation circuit 3100 skips the field memory read address. have the ability.

$ 4' Figure 4 shows the circuit block 302 shown in the 43rd factor.
Details of 0°3021, 3023, and 3025 are shown.

In Fig. 44, the main direct timing signal G,
Mma' 618 and GMM 607 are interrogated by shift registers 5R700°8R701 and 8R704, respectively.

The clock signal φ of these shift registers 8R is -21
11! Data '4r of sub-m plane shown in Q: Timing signal BP for φ conversion.

Use.

8R700A/81700B/8P4) The output 674 of the AND gate 703 that performs the logical operation is the field memory read address. Reset counter 3024.

On the other hand, the output of left register 8R704 (8R704A
・The output cuff 45 of the AND gate circuit 706 of the 8R704B/8P4) is a reset signal of the RIH kakunta 733 consisting of one stage and a line memory address signal 71 which will be described later.
1.

Here, the output B, 732 of the shift register 8R 704 is defined as Tsukuda.

FIG. 45 shows the 87P conversion timing signals 8P, 321, 8P, 323 of the sub-blood data, and the main screen timing signal GM Maro 05. Outputs 674, 48 of gate 703
The timing chart of the output signal GH732 of the output cuff 45 of No. GMH607, Game) 706 and the shift register 8R704 is shown. To explain FIG. 44 with reference to FIG. 45, the output signal GH732 of the shift register 704 synchronized with the clock signal CP 321 is used as the clock signal of the RIH counter 733. Signal G
When H732 rises, the above RIHFI' output Q734
stands up. At this time, the output of the gate circuit 725 is the output (8F, +8P, ) signal 726 of the OR gate 705.
get. Further, the above signal 726 is added to the clock of the IH data monitor counter 727 (8P+8Pa
) is the number of stitches on the clock. One output 728 of the counter 727 at address 32 becomes IIJ and the signal 8P.
319 is input, the AND logic of the gate circuit 729 is established, and the output of the gate circuit 731 causes the RIHFP 7
33 is reset. The output RIH signal 734 of the RIHFP 733 is a signal that is "1" during the period when data for one period (8F, +8F4 clock, period of 32 clocks) is read out from the field memory.

The RIH signal 734 is guided to the shift register 8R746, and synchronized with the falling edge of the signal RIH (8R746A
・SR746B, 8P, ) Obtains the reset signal 711 of the karine memory address counter as a result of AND operation. Furthermore, (2) A of the gate circuit 707 is a mode signal (
m, .) 741 and the output Q739 of FF3, which will be described later, are ANDed to obtain a field memory preset signal 6801. The output B of the left register 8R746 is inno (-
It is reversed by Tough 15 and the counter 718 (referred to as R2HFF) +m+o) 712, mH・mH713
When each is "0", the IH data read period 11J is performed in the same way as the RIHFF described above. Now, when the image display mode signal 738 is rlJ, R2HFF718
The Q output R4720 of is led to 8R736 o (m
The field memory preset signal 743 is generated by the AND of s.mot)i3R736A-8R736B-8P. Note that the gate circuit 702 generates a signal that defines the field memory refresh period of the DRAM configuration, and the result of the AND operation of this signal with (8F, 18P4) is added to the signal 710.

FIG. 46 shows a time chart of the earthen signals among the signals treated in the $44 diagram above.

In FIG. 46, within the period of GH732, the signal RIH73
4°R2H720 occurs. That is, main screen ITII
The figure shows that data for 2H of the sub-screen can be read from the field memory during the M period.

It should be noted that determining whether to read 18 minutes of data from the field memory or to continue reading 2H of data from the field memory within the signal GH cycle is determined by the second control on the field memory output side according to the image display mode family described above. It depends on how reduction and expansion operations are performed when performing correlation operations.

(Address skip when reading data from field memory) FIG. 47 shows the field memory read address generation counter 3024 of the field memory read address generation and arithmetic control circuit 3100 shown in FIG.
, adder 3027 , skip data generation circuit 3026
, line memory address generation circuit 3022 ,
/(soft memo 911 included clock control circuit 3028,
This circuit shows the details of the buffer memory write address generation circuit 3''29.The output 682 of the field memory read clock generation circuit 3023 is a field memory read address counter 75 consisting of 13 counters.
0 H is led. The reset signal for this counter 750 is a reset pulse 674.

m in the image display mode family. The field memory preset signal 680 generated by the skip timing generation circuit 3025 in the 2m, .m61 mode is connected to the preset terminal of the counter 750, and the counter is preset to a preset value 689 at the rising edge of the signal 680. Further, the output 684 of the counter 750 is led to one input terminal of the adder 751, and the other input terminal of the adder 751 is the skip data 687 determined by the skip data generation circuit 3026. This skip data is +64 address (advance the field memory address by 6) 752 and -32 address (
3 to field memory address 1:2J16i) 7
Fifty-three diplants were prepared. This skip data is controlled by the mode signal 685 indicated by the image display mode l1l (1' m61), m...m (data 752 with a value of +64 is ml in the 11 mode)'1. 32 value data 753 is added as skip data to the adder 3027 (line memory address specification) to the line memory address generation circuit 3022 (
R2H720) Signal 723 is left register 8R75
8 and the P/8 timing (see FIG. 29) is also synchronized by signal 757. The output cuff 59 of the shift register 8R758 is ANDed with the clock signal φ- (gate 76o) and the line memory address counter 76
2 clock input. Further, the line memory address counter 762 generates a line memory address for storing data read from the field memory in the line memory.

The reset signal for the counter 762 is the line memory address counter reset signal 711.

The above signal CR2H720) 723 is also used as a clock signal for FF3763, and is used as a clock signal for FF3763.
3Q, LmRFF3Q, and LmW are line memory loading and unloading signals.

On the other hand, signal (RIH) 734, (R2)1')
720 is each 4t/7 register 8R766, 8M 76
5 and synchronized with the above-mentioned signal 8!757. In addition, V foot register 8R766 output cuff 67 and 8R
The 765 output cuff 68 is led to 81769 and 81789, respectively, and is delayed by two clocks of the clock signal φIo. Here, the above left register 8R767 (7) B output '%: RIH', 8R789a) B output t'
12H'RIH' and a signal 767 are input, and the output thereof resets the buffer memory write address counter 774 from the output cuff 72 of the NOR gate circuit 771. Further, the signal R2H' is guided to the NOR gate 771 via the OR gate circuit 773. That is, the signal RIH'
A reset signal is obtained for the counter 774 before the rising edge of sR2''. Gate circuits 778, 779, and 780 provide clock signals to this counter 774.The clock rate of the clock signal □ of the counter 774 is indicated. It differs depending on the coefficient of horizontal data reduction/enlargement on the Field-on-Mori output side in each mode of the 1Ill image mode.The clock signal of the counter 774 can be written as the following equation.

Counter 775's 9o Tsukushin J,, -("""m"""Hζφs+f
f1orRIHζφ−0+m@,,R2H'・CTR8
Ql - song... song (1# The 9-bit output 694-1 of the counter 774 is led to the buffer memory.

(Buffer memory heat up and read timing)
A flip-flop (FF4) 693 controls the continuous writing of data to the buffer memory.
This is a one-stage counter that operates at the rising edge of the signal G□607 described above. This (FF4) 639 reset is a field memory read address generation circuit 3020 discrete reset signal 674.

In this manner, in the image signal processing circuit shown in FIG. 10, the field memory read address generation and arithmetic control circuit 3100 generates the field memory read address (signal 684 in FIG. s43).

The line memory addresses of the arithmetic circuits 1500 and 2600 (signal 697 in the figure jl1%43) and the address of the output buffer memories 1600 and 2700 (
A signal 694) in FIG. 43 is obtained.

(Data complementation and nesting when calculating phase s1 of 's2)
The data reduction/enlargement calculation circuits 1500 and 2600 according to each mode signal in the display mode table mentioned above will be described.
This will be explained using time charts in Figures (Hatake) to (e). Note that the main timings in the figure are field memory read timings RIH734 and R2H720.

and field memory read address counter preset signal 680. Operation period RIH'790 or R
2H720 and l Analog switching signal DG16 indicating the period during which digitally processed signals are displayed in the horizontal scanning period
7 is shown.

FIG. 48(a) shows a time chart when the image display mode is indicated by m..m@I. According to this figure, 2H worth of pretal processing was performed from the field memory during one period of 0MM607, which is one horizontal scanning period of the main screen.
Image data follows. The reduction operation in this mode is R
This is performed in a period of 2H'791, and the calculation results during this period are read into a buffer memory to be described later. The data read into the buffer memory will be read and displayed during the DG167- period. Further, at the rising edge of the preset signal 680, the field memory read address is skipped by 2H of the sub-plane in this mode. As a result, data for two lines required for performing the second correlation calculation in this mode is read out during a period corresponding to one line of main blood.

FIG. 48(b) shows a time chart in the m(1"1111S!" mode and the ml" m@I mode. In this mode as well, as shown in the mode table, the two times of T and B are
Since the calculation target is a line, it is necessary to extract data spanning two lines.

Figure 48 (C) is a time chart in OS mode.
The data written to the buffer memory during the IH' period is
An interpolation operation is performed to double the data density in the horizontal direction,
The table will be shown in the next DG period.

Fig. 48(d) shows a time chart of fJ.01 mode, and since it is Hdowl and Vdoxl, in this mode, it is only necessary to process the data of the same line, and the field memory data is GM, and only IH data in one cycle. is read from field memory and displayed.

- FIG. 48(6) is a time chart for the m1o mode, in which a preset signal for the field memory continuing address counter is generated by the output of flip-flop FF3 of the field memory address generation circuit 322 shown in FIG. This input is returned by the input signal. Therefore,
18 minutes of field memory.

The data will be read out twice.

As shown in FIG. 48 (1) to (e), the data in the field memory in each mode is read out, and the read data is subjected to reduction-enlargement operations in the IRH' or 2RH' period. and stored in buffer memory.

(Second correlation calculation) Using Figure 49,'! The phase@threshold calculation of JI2 has already been described, but the interpolation and rejection of data when performing reduction and expansion operations will be further described using FIG.

Figure 49 shows this example (interpolation and rejection of data concerning only the mode that performs characteristic calculations among the two modes).

FIG. 49 (Hata) is an explanatory diagram when calculating the horizontal reduction coefficient Hdo-=-% p vertical reduction coefficient Vdo=mass in the "o' m01 mode. In the same figure,
0yu shows data lined up for each data line read from the field memory. The same applies to the following description.

In the m...mg11 mode shown in (-) in the figure, for example, n line data and n+1 line data are read from the field memory and reduced using the data indicated by arrows and the own data. conduct. 0 in the diagram
The marks are data interpolated in the horizontal direction and are displayed one after another on the m display lines of the main screen. In this case, data obtained from two lines of data of n+4° and n+5 is displayed on the m+1 line of the main screen. Unfortunately, in the vertical direction, data for three lines of sub-l1iIiiiI has been discarded.

FIG. 4B shows calculations in m/black mode. Department H
dox2. New data is interpolated to the part marked Δ in the figure by the calculation such that Vdo=1. This interpolation data is created from only the l line.

Figure (e) shows calculations in ml (l mode).

That is, Hdom2. The case of calculation of Vdox2 is shown. In line m in the figure, interpolation calculations are performed using data on both sides. For the m+1 line, data is interpolated by performing upper and lower interpolation and interpolation calculations using four points on the diagonal. In this case, to generate interpolated data for l line, T
(n) t M (n + 1) a B(-”
2) requires three lines of data.

In the block diagram of FIG. 1810, the arithmetic circuit that performs the above-mentioned arithmetic operation is the field memory output side luminance signal ti4 calculation circuit 1500. Field memory output side color signal calculation circuit 2
It is 600. Both arithmetic circuits 1500 and 2600 have the same circuit configuration except for a part.

FIG. 50 shows details of the luminance signal calculation circuit 1500.

The luminance signal calculation circuit 1500 uses line memo 9802, 8
03° 804 and 805, and an arithmetic circuit 801 that performs a reduction or enlargement operation according to each mode. P/8 conversion output data Y@135 of the field memory is led to line memories 802 and 803. The address of the line memory address is supplied from the output 697 of the line memory address generation circuit 3022.

In addition, the control signal for reading data from each line memory is provided by flip-flops FF3Q and FF3ζ of the line memory address generation circuit 3022 shown in Figure i11%47.
is supplied.

The above luminance signal Y, 135, IH play signal 806
, 2H play signal 807 are each supplied to a latch circuit consisting of 6 bits. The output of each latch circuit is defined in Fig. 27. The signal to be calculated is B+I Y@e BeY
@ #M+IYos 1li16Y@j M-I
Y6 p T+IY@e TeYe s T-IY@
It is shown in FIG. 50 using the symbol #TeYe. In the figure, each signal 801, 808, 809, 810, 811,
812, 813 ) 1 M 26 is led to an arithmetic circuit consisting of a multiplication circuit and an adder similar to the first correlation arithmetic circuit shown in the figure. The operation will be explained below by drawing the calculation formulas in each mode with reference to the drawings.

! The output of the latch circuit shown in J50 is mQ' ml, 0.5 in mode MOYII +0.2581￥o +
The calculation result for the luminance signal which is divided by 0.125 (M-tYo + M++Ye) is obtained. The clock of the latch circuit 815 is φL (described later using Figure 111445), and the T terminal has the m, mat signal 81.
7 is added. In addition, the calculation in m6-ffl/yi mode is 0.5MoYo + 0.25 (B, Y, +
T(IY, ), and the operation result is led to the latch circuit 818. The clock of the latch circuit 81g is the φ axis, and the m...m view is applied to the T terminal. In addition, in the water calculation, as shown in FIG. 49(b) (C), -.

Mode m-line operation and ml. m of mode, (m+2)
It is understood that the line operations are common. That is, m,
In the Q mode, the signal that determines the m line, m+2 line, etc. is the signal shown in Fig. 44 Fii'4784, and the ml. =FF
The signal subjected to the 4Q AND operation and the logical operation result in the mol mode are the same. In addition, in the arithmetic circuit shown in FIG. 50, the latch circuit 834 has M. Y, the signal is led to the latch circuit 834, 0.5014Yo +M+,
yo) is derived. This latch 834.
The clock φ of 831 becomes the φ10 signal. On the other hand, φno is connected to the T terminal of the latch circuit 831.
11s6 is added to the T terminal of 34, and the latch circuit 83
1, the output of 834 is wired ORed and the latch circuit 8
It has been added to 43. The clock of the latch circuit 843 is φ1=2φme, and the T terminal has mH+ml(1−
FF4Q 844 is added. Image display mode is ml
- Since no calculation is performed in the mat mode, the M@Y signal is directly led to the latch circuit 837. Latch circuit 837
The clock is at the φ station, and the T terminal is ``at 838.'' And ml.m.

Mode calculation is 0.5M, Y, + 0.125 (M
+iYo +M-, Y, ÷BoYe+ToY), the calculation result 820 is led to the latch circuit 821 I:. The clock φ of the latch circuit 821 is φL, and the 1' terminal has m
A wealth mot signal is added. Further, in the calculation corresponding to the m+1 line shown in FIG. 18) in the m, mode, the calculation result can be obtained by the calculation of two types. In this case, 3
%50 Figure 6=, lap time 11f, 824, interpolation calculation using upper and lower 2 line data 0.5 (ksoy・
The calculation result 820 of +T@Y.) is equalized. -force,
The latch circuit 827 has 0.25 (BoY・+T, Y,
+Bya, Y, +T, Y, ) calculation result 828 is derived, and the latch circuit 824. 827 clock' and T
The terminals will be similar to the above-mentioned lap 1 paths 831 and 834 2. That is, the clock terminal of the latte circuit 824, the T terminal 825, and the latch circuit 827 lock terminal have φ.
The axis is asked. The T terminal 829 of the latch circuit 827 has l.
s6 signal is added. Then, the clock of the latch circuit 840 at the final stage becomes φ1, and the T terminal 841 has m
, . . . FF4'Q signal is added.

Data 1 in which each latch circuit output above is wired-ORed
37 is written into the buffer memory 42.

(Correlation calculation for color signal) The second correlation calculation for the luminance signal (; has been explained using Fig. 450, but next, the second calculation for the color signal is m
In olo-mode, it is equivalent to brightness signal calculation except for small calculations. Figure 51 shows the reduction operation circuit in "Ol mode.m)
−m(1, color signal calculation result in mode, (0,
5M@C6+0.25 B@C6+ 0.125 (M
+, c, + M-IC's)) 890 is lat f[! l! You will be directed to Route 1 891. Nao above M.C.s
Symbols such as B6CO... are given in accordance with the symbols in FIG. 50.

The output of the latch circuit 891 which uses the first φ as the a-lock signal,
893. and LM 890 are guided to a 6-bit data selector 894. This data selector 894 has a control X terminal 895, and when the X terminal is "1", the signal LA 8901 is output 896,
When J, it operates to direct signal Lm 893 to output 896.

Now, C'l'R81Q is connected to the X terminal, signal Ik is led, and φL (φL=CTR8I
Q1φ-0) and m...ff161 to T terminal 899.
When a signal is applied, the output of the circuit is o1@ ” 0
A reduced signal in one mode is obtained. In Figure 52,
Figure 51: shows a time chart of data during correlation calculation for the indicated color signals.

In this FIG. 52, the calculation results synchronized with the clock φso, the data of 890 points are, for example, RY', B-Y,
It flows in the order of RY,... By controlling this data flow using the multiplex signal CTR81Q*42 and latching φ with the signal, the output 126 of the latte circuit 897 has R-Y', B-Y', and R.
-Y', . . . color signal data reduced to h is obtained.

FIG. 51 shows the correlation ti411# circuit for the color signal. In the m@II mode as well, the nine reduction operation is performed with a circuit configuration similar to that in the m6@gn@ mode. The color calculation output 126 obtained according to each mode is stored in a buffer memory.

(Writing data to the output buffer memory) Figure 53 shows a specific circuit diagram of the luminance signal ratio buffer 160G and the color E number output buffer 2700. Figure 53 shows the buffer memory write address 694-1. The write/read control signal (FF4 output in FIG. 47) address 566 is guided to switching buffer circuits 856, 857, 858, 859. The switching buffer circuit receives control signals 694-2, 6
Data buffer line memory 850 according to 94-3
, 851 . , 853 , 854 with write and read addresses 860 , 861 . Now, when the control signal 694-3 is rlJ, the line memories 851, 8
54 is in write mode, convolution address 694-1 is led to address 861, and data is written. At this time, the control signal 694-2 is IOJ, and the line memories 850 and 853 read data according to the read address 860. The buffer line memory luminance signal output 852 is directed to a launch 862 for phasing with the chrominance signal. The output of the latch 862 is further passed through two stages of latches 863 and 864 to obtain a 6-bit luminance signal output Yout 139. The color signal buffer memory output 855 has different R-Y and B-Y signal trains depending on the mode.

FIG. 54 shows a signal train in rn2@+mas mode.

FIG. 55 shows a signal train in the ml.+rnos mode.

To further explain the circuit of FIG. 53 with reference to FIG. 1JS54.55, the latch circuit 865 in FIG.
The latch circuit 866 is a latch circuit for signal detection.
This is a signal detection latch circuit. In each latch circuit, B-
Y, 1 (-Y signal is detected by each latch circuit ζ: guided clock φm-ysst, and φl-Y 82
This is done by controlling 2. In addition, counter FF58
The inverted signal φ of 614 (see FIG. 40) and 0 867 are input to the input of 70. The input of the counter FF6871 is led to the Q1 output of the FF5870. The reset terminals of the counters 870 and 871 are connected to the buffer memory read address input counter reset signal 616 (fourth
(see figure 0) is wrapped. This allows latte clock φ
1-Y881. φl-Y 822 is obtained by the following formula.

φm-y-(men"mtoJ・φm01+FF6Qm
+ mos"+e ・-, HFF5Q4"1tBda,
,,v = (mas + 1111cn) ・φ−m・
FF6Q*+maa+m*t*lIm+nJf'5
Q1''/Q7) Gate circuits 874, 875, 87
6, 8'l'l, 879, and 880 are gate circuits that realize the logic of the above two equations. Figures 54 and 55 show the bow V; mode and "os + m@1 mode."
These timing charts are shown below.

As you can see from the timing chart, φl-Y 88
1.

By giving φa-Y, 882, lat y-8
The B-Yout 129 signal is obtained from the output of 65,
The R-Yout 128 signal is obtained from the output of the wrap 866. Also, in Figure 53, Yout 139, B
-Yout 129, R-Yout 128 and φ,. The clock φDm 883 of the 1867 inverted signal low deviation converter is equal to each D/A converter circuit.

In the block diagram of Fig. 1θ mentioned above, You13
9 is led to the D/A converter 1700 Y-DAC 140 and replaced with an analog signal. Similar 1: R-You
t 128 is led to R-YDAC2000 and converted to an analog signal, B-Yout 129 is led to B-YDAC2
100+2 is converted into an analog signal. The converted analog signal is sent to buffer amplifier circuits 1800 and 21.
00 and 2200, subjected to DC level adjustment and gain adjustment, and analog-converted, the luminance signal is led to a luminance signal switching circuit 1900. The color signal is guided to a color signal switching circuit 2300.

The analog switching signal DG mentioned above is a double switching circuit 1900.

2300, and the signal DG is in the rlJ period lt&
When DG167 is rOJ, the output circuit 3200 is a digitally processed image signal.
-Y, B-Y are led to the switching circuit output 130, 1
31 and 132 are led to an output circuit 3220, and an output circuit output 133 drives a CRT 134.

(Effects of the present invention lA) As is clear from the above description, according to the present invention, the main 11
! When inserting the sub-surface into the 1iiiin and projecting it, the 1st . Second phase! Since 1M calculations are performed, many types of calculations can be set for image data, and the display form of the bust can be set across multiple modes. This image mode selection is not limited to the size of the display image direction, but also applies to the selection of whether to display a moving image or still image tJI, and the mode selection of whether or not to display a zoomed-in image. Iris blooms.

Also, when inserting a sub screen into the main ik'f11, the image data is the main ik'f11! Within one horizontal period in the Ii direction, digitally processed image data corresponding to one horizontal period of the sub-VIA blood is loaded into the field memory, and the sub-m-m data is sequentially output, so that the line correlation correlation calculation is performed. can operate on multiple lines of data. This means that even when correlation calculation is performed in the horizontal direction, not only the current line but also #image data t of other lines are subjected to the correlation calculation, so that an image with high resolution can be obtained.

In addition, regarding the synchronization system, when inserting a sub-TM screen on the main screen, image processing is performed instead of the main synchronization system that is synchronized with the sub-screen, so disturbances in the synchronization of the inserted image will not occur. . Furthermore, regarding the synchronization of the main screen and the sub-screen itself for iK,
It is determined whether the supplied synchronization signal is within the internal synchronization pull-in range or not.

If it is within the pull-in range, it is synchronized by internal synchronization, and if it is outside the pull-in @1, the circuit is configured to reset one part with the synchronization signal supplied by the internal synchronization system and shift to the internal synchronization thread after ε. The synchronization system can be kept stable.

In history, correlation calculation is the first. Since the correlation calculation is performed separately into the second correlation calculation, if the correlation calculation is performed by a single calculation, the capacity of the field memory must be large, but in the present invention, the correlation calculation 2. The capacity of the field memory required is relatively small. This means that if the display product of the sub-screen to be inserted is reduced, 1III image data will be rejected, but this data will be rejected multiple times on the input/output side of the field memory, so the capacity of the field memory will be reduced. This is understandable because it requires less. Furthermore, since the circuit configurations of the field memories for the luminance signal and the color signal are approximately the same, the circuit configuration of the first address path can also be approximately the same, so that the image signal processing circuit according to the present invention can be integrated. It also has a very effective effect.

[Brief explanation of the drawing]

FIG. 1 is a general explanatory diagram without inserting a graphic image iI[l in the raw direction, FIGS. 29g and 3 are block circuit diagrams showing a conventional bust signal processing circuit, and FIG. FIG. 5 is an explanatory diagram illustrating the image display position displayed by the image signal processing circuit according to the present invention (the first correlation calculation circuit of the image signal processing circuit according to the second embodiment). 6 and 7 are diagrams explaining the operation of the circuit shown in FIG. 5, FIG. 8 is a circuit diagram showing the second correlation calculation circuit of the image signal processing circuit according to the present invention, and FIG. 9 is a diagram explaining the operation thereof.
sio diagram is a circuit block diagram showing the entire image signal processing circuit according to the present invention, FIG. 11 is a circuit block diagram of the sub-screen timing value generation circuit in FIG.
A circuit diagram showing the approval synchronization detection circuit in the figure, FIG. 13 is a circuit block diagram showing the field memory input line memory,
414 is a circuit block diagram showing a line memory address generation circuit, 151fi is a timing chart of the circuit in FIG. 14), 11416 and 17 are timing charts for explaining the vertical timing of the sub screen),
Figure 8 is a timing chart explaining the color signal multiplex timing, $19 is a timing chart for explaining it), Figure 1126 is the first correlation calculation circuit diagram, and the second
Figure 7 is an explanatory diagram, and Figure 28 Ha II! 1i*theta (7
) 8/P, a circuit diagram for explaining a P/8 conversion circuit; FIG. 29 is a circuit diagram showing a circuit that generates a timing signal for P/8 conversion; FIG. 30 is a timing chart thereof; FIG. 31 is a circuit diagram showing a field memory address generation circuit, FIG. 32 is a timing chart for explaining the same, FIG. 33 is an explanatory diagram for explaining address skipping, and FIG. 434 is a main I! 11 is a circuit diagram showing the timing generation circuit, Figure 35 is a timing chart for explaining vertical synchronized playback, Figure %36 is a horizontal diagram,
A timing chart to explain the vertical drive signal generation circuit, FIG. 43 is a detailed circuit diagram of diagram s38, FIG. Figure 50 is a circuit diagram for performing the second correlation calculation, Figure 51 is a diagram showing a circuit for performing correlation calculation for color signals, and Figure 52 is a timing chart for explaining it. It is. 1420... Bright GT signal field memory 1430...
... Field memory control circuit 1440 ... Field memory address generation circuit 1600 ... Luminance signal output buffer circuit 2700 ... Color signal output buffer circuit 2
520... Color signal field memory 2806... Horizontal timing generation circuit 2808... Line memory address generation circuit 2800... Sub direction timing generation circuit 2811... Synchronization signal width detection circuit 2812... Phase comparison Circuit 2813... Phase comparison pulse generation circuit 2814...
Vertical timing signal generation circuit 2817...% data reduction timing generation circuit 2818...Field memory control signal generation circuit 2821...% data small timing signal generation circuit 2900...Mode signal generation circuit 3000...Douga direction timing generation circuit 3025...
・Skip timing generation circuit 3026...Skip data generation circuit 3028...Buffer memory write clock sIj control circuit 3100...Field memory address generation circuit (7317) Agent Patent attorney Nori Chika
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C) M+ is also one Figure 50 Figure 51 Figure 52 Ij 53 Figure 2jS Figure 54 φa-y 551-:1 φtov Procedure Amendment (Method) % formula % [l, Indication of incident Special request Showa JS6 xasg1a No. 2,! 1i Ming's name 一儂Bigo魁jl1gl路3、Relationship with the case of the person making the amendment Patent Applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent Address: 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo 100 Tokyo Shibaura Electric Co., Ltd., Tokyo Office, February 33, 1988 (shipment date) 6. Target of amendment [Engraving of attached specifications (3 pages to 1 m, 133 ver.). (No markings on the contents) :2] Engraving of book 114tf & accompanying drawings. (No question history for 1 answer) L.

Claims (1)

[Claims] The main Idii side um volatile polarization code and the 11th screen image signal are processed, one screen &C the other IIkI image are inserted, and the
Or either -11117! In a single signal processing circuit capable of enlarging and displaying the i signal, - a means for handling the image 10 brightness signal and the color demodulation 1d signal V; % converter circuit that converts the ffi luminance 1d signal and the color demodulation signal into digital 16 signals, and the sub-II according to the mounting mode that generates the timing signal of the sub-plane. 11 side timing signal generation circuit, memory 1gl Ayu which stores memory under the control of the above-mentioned % Humpertata power supply sub-image timing signal, and main 1aI according to the display mode.
mode specifying means for specifying a mode signal S' that displays both the main screen timing of the lth+ tie-building No. 1♂ V @ generated time and the main screen -1;
A back-up memory circuit that stores data from the memory circuit under the control of the No. 1 screen timing signal according to the front mode No. A 4-converter circuit that converts the output of the warp circuit into an analog signal, and a special effect mode that is read into the buffer memory in order to set the time in which the image display area of the specified inserted image is expanded to a predetermined area. II! The means for obtaining the specified mode signal V and the special effect activation time! Ii image data 11
! An image signal processing circuit having at least a display/large area suppressing means for minimizing the data t' when specifying the input and increasing the data t' after the specification. (hereinafter referred to as Yashiro)